CN102289237B - Dual-mode on-chip power supply circuit - Google Patents

Abstract

The invention discloses a dual-mode on-chip power supply circuit. Aiming at the defects that the existing linear on-chip power supply circuit has a small ripple, but has a limited output voltage regulating range, and the existing switch on-chip power supply circuit has a large output voltage regulating range, but has a large ripple, the power supply circuit disclosed by the invention combines the advantages of the linear on-chip power supply circuit and the switch on-chip power supply circuit, so that an output voltage, i.e. the ripple, is low and the output voltage regulating range is large. The power supply circuit disclosed by the invention comprises an on-chip reference source unit, an overvoltage and undervoltage logical unit, an error amplifier unit, a power output unit and a high voltage JFET (Junction Field-effect Transistor) and is characterized in that a grid of the high voltage JFET is connected to an output end of the error amplifier unit; an output end of the on-chip reference source unit is connected to one input end of the error amplifier unit; and an output end of the power output unit is connected to the other input end of the error amplifier unit.

Description

A kind of double mode internal power circuit

Technical field

The invention belongs to the chip design art field, relate in particular to the design of a kind of internal power circuit.

Background technology

The sheet internal power circuit is the power module that is integrated in semi-conductor chip inside.Its effect is mainly to obtain electric energy from external power source (for example 220V civil power), and flat the acceptable galvanic current of other modules of Conversion of Energy chip internal, and gives inner other module for power supply.At present, power supply can't reach the level of external power source on the technical indicators such as ripple amplitude, setting range, power consumption in sheet, still, in sheet power supply have design objective flexible, with low cost, can be integrated etc. the incomparable advantage of external power source.Therefore, the interior power supply of sheet will become another developing direction of following power supply.

Mainly contain at present two kinds of form sheet internal power circuits, linear sheet internal power circuit and switch plate internal power circuit.The structure of linear sheet internal power circuit comprises reference source unit, error amplifier unit and PMOS transfer tube in sheet as shown in Figure 1.Vin is provided by external power source, can be the DC voltage with the violent ripple of the amplitude of oscillation, V ₀Be output voltage, power supply be provided for inner other modules.On main performance, this power technology is very ripe, can reach very high degree of stability, and ripple is also very little, and the interference and the noise that do not have the switch plate internal power circuit to have.But this power supply also has very large defective, and that is exactly that oneself power consumption is high, the output voltage range of adjustment is limited, the application of the linear sheet internal power circuit that these shortcomings greatly limit.

Switch plate internal power circuit structure as shown in Figure 2, comprise over-and under-voltage logical block, high pressure JFET, the high pressure JFET here refers to the above JFET of the withstand voltage 200V of a kind of drain-source, Vin is inputted by external power source, the grounded-grid of high pressure JFET, the over-and under-voltage logical block is to control the Kai Heguan of NMOS pipe MN1 pipe, indirectly controls the switch of NMOS pipe MN2 pipe, to reach control whether to the purpose of capacitor C 0 charging; Vout is output voltage, power supply is provided for inner other unit.The structure of over-and under-voltage logical block as shown in Figure 3, wherein Output is the grid that outputs to the MN1 pipe of Fig. 2 circuit, A11, A12 are two comparers, A13 is the S-R latch, BP is the BP point current potential in Fig. 2 circuit.The relative the first efficient of this power supply is higher, the output voltage setting range is larger, and still, its shortcoming is that ripple is large, and is inapplicable in the demanding situation of sheet internal power circuit.

Can find out, the ripple of linear sheet internal power circuit is little, but the output voltage range of adjustment is limited; The output voltage setting range of switch plate internal power circuit is large, but ripple is also large.

Summary of the invention

The objective of the invention is to have proposed a kind of double mode internal power circuit in order to solve the problem of above-mentioned existing internal power circuit existence.

to achieve these goals, technical scheme of the present invention is a kind of double mode internal power circuit, comprise reference source unit in sheet, the over-and under-voltage logical block, the error amplifier unit, power stage unit and high pressure JFET, external power source is input to the drain electrode of high pressure JFET, the source electrode of high pressure JFET is connected to the first input end of power stage unit, in sheet, the output terminal of reference source unit is connected to an input end of over-and under-voltage logical block, the output terminal of over-and under-voltage logical block is connected to the second input end of power stage unit, the output terminal of power stage unit is connected to another input end of over-and under-voltage logical block, it is characterized in that, the grid of high pressure JFET is connected to the output terminal of error amplifier unit, in sheet, the output terminal of reference source unit is connected to an input end of error amplifier unit, the output terminal of power stage unit is connected to another input end of error amplifier unit.

Described interior reference source unit comprises: resistance R 11, R12, R13, R14, R15, PMOS pipe MP11, MP12, MP13, MP14, triode Q11, Q12, Q13, Q14, Q15, Q16, Q17, NMOS manages MN11, wherein an end of resistance R 11 is connected to sheet internal power circuit output terminal, and the other end is connected to the collector of triode Q11; The collector of triode Q11 and base stage short circuit, the emitter of triode Q11 are connected to the drain electrode of NMOS pipe MN11; The drain electrode of MN11 and grid short circuit, the source electrode of MN11 is connected to publicly, the source electrode of PMOS pipe MP11 is connected to sheet internal power circuit output terminal, and the grid of PMOS pipe MP11 is connected to the collector of triode Q11, and the drain electrode of PMOS pipe MP11 is connected to an end of resistance R 15; The other end of resistance R 15 is connected to publicly; The source electrode of MP12 is connected to sheet internal power circuit output terminal, and the grid of PMOS pipe MP12 is connected to the drain electrode of MP11, and the drain electrode of MP12 is connected to the collector of triode Q13; The base stage of triode Q13 is connected to the collector of triode Q14, the emitter of triode Q13 is connected to publicly, the source electrode of PMOS pipe MP14 is connected to sheet internal power circuit output terminal, the grid of PMOS pipe MP14 is connected to the grid of MP13, and the drain electrode of PMOS pipe MP14 is connected to the drain electrode of PMOS pipe MP12; The source electrode of PMOS pipe MP13 is connected to sheet internal power circuit output terminal, the grid of PMOS pipe MP13 and drain electrode short circuit, and the drain electrode of PMOS pipe MP13 is connected to the collector of triode Q15; The base stage of triode Q15 is connected to the drain electrode of PMOS pipe MP12, and the emitter of triode Q15 is connected to the end of R12; The other end of resistance R 12 is connected to the collector of Q14; The base stage of triode Q14 is connected to the collector of triode Q17, and the emitter of Q14 is connected to an end of resistance R 14; The other end of resistance R 14 is connected to publicly; The end of R13 is connected to the emitter of triode Q15, and the other end of resistance R 13 is connected to the collector of triode Q17; The collector of triode Q17 and base stage short circuit, the emitter of triode Q17 is connected to publicly; The collector of triode Q12 is connected to sheet internal power circuit output terminal, the base stage of triode Q12 is connected to the drain electrode of PMOS pipe MP12, the collector of triode Q16 is connected to the emitter of Q12, the base stage of triode Q16 is connected to the base stage of triode Q17, and the emitter of triode Q16 is connected to publicly; The emitter of triode Q12 is namely the output terminal of reference source unit in sheet.

Described over-and under-voltage logical block, comprise resistance R 21, resistance R 22, resistance R 23, Sheffer stroke gate A1, Sheffer stroke gate A2, Sheffer stroke gate A3, phase inverter B1, phase inverter B2, phase inverter B3, comparator C 1 and comparator C 2, wherein, one end of resistance R 21 is connected to sheet internal power circuit output terminal, and the other end of resistance R 21 is connected to the negative input end of comparator C 2; Resistance R 22 1 ends are connected to the negative input end of comparator C 2, and the other end of resistance R 22 is connected to the positive input terminal of comparator C 1; R23 one end is connected to the positive input terminal of comparator C 1, and the other end of resistance R 23 is connected to publicly; The positive input terminal of comparator C 2 is connected to the output terminal of reference source unit in sheet, and its output terminal is connected to the input end of phase inverter B1; The negative input end of comparator C 1 is connected to the output terminal of reference source unit in sheet, and its output terminal is connected to the input end of phase inverter B2; The output terminal of phase inverter B1 is connected to the input end of Sheffer stroke gate A1; Another input end of Sheffer stroke gate A1 is connected to the output terminal of Sheffer stroke gate A2, and the output terminal of Sheffer stroke gate A1 is connected to the input end of Sheffer stroke gate A2; Another input end of Sheffer stroke gate A2 is connected to the output terminal of phase inverter B2; The input end of Sheffer stroke gate A3 is connected to the output terminal of comparator C 2, another input end of Sheffer stroke gate A3 is connected to the output terminal of Sheffer stroke gate A1, the output terminal of Sheffer stroke gate A3 is connected to the input end of phase inverter B3, and the output terminal of phase inverter B3 is the output terminal of over-and under-voltage logical block.

Described power stage unit comprises resistance R 40, NMOS pipe MN41, diode D40, NMOS pipe MN42 and electrochemical capacitor C40, and an end of resistance R 40 is connected to the source electrode of high pressure JFET, and the other end of resistance R 40 is connected to the drain electrode of NMOS pipe MN41; The grid of NMOS pipe MN41 is connected to the output terminal of over-and under-voltage logical block, and the source electrode of NMOS pipe MN41 is connected to the anode of diode D40; The negative electrode of diode D40 is connected to publicly, the drain electrode of NMOS pipe MN42 is connected to the source electrode of high pressure JFET, the grid of NMOS pipe MN42 is connected to the drain electrode of NMOS pipe MN41, the source electrode of NMOS pipe MN42 is connected to the positive pole of electrochemical capacitor C40, the negative pole of electrochemical capacitor C40 is connected to publicly, and the positive pole of electrochemical capacitor C40 is the output terminal of sheet internal power circuit.

Beneficial effect of the present invention: double mode internal power circuit of the present invention is by organically combining linear power supply circuit and switching power circuit, make the present invention combine the advantage of linear power supply and Switching Power Supply, namely ripple is little, the output voltage range of adjustment is large.

Description of drawings

Fig. 1 is a kind of existing internal linear power circuit.

Fig. 2 is a kind of existing interior switch adjuster power supply.

Fig. 3 is a kind of circuit diagram of realizing of over-and under-voltage logical block in Fig. 2.

Fig. 4 is the circuit diagram of double mode internal power circuit of the present invention.

Fig. 5 is the interior reference source cell schematics of the sheet of the embodiment of the present invention.

Fig. 6 is the over-and under-voltage logical block schematic diagram of the embodiment of the present invention.

Fig. 7 is the power stage cell schematics of the embodiment of the present invention.

Embodiment

The invention will be further elaborated below in conjunction with accompanying drawing and specific embodiment.

double mode internal power circuit of the present invention as shown in Figure 4, comprise reference source unit 1 in sheet, over-and under-voltage logical block 2, error amplifier unit 3, power stage unit 4 and high pressure JFET J0, external power source Vin is input to the drain electrode of high pressure JFET J0, the source electrode of high pressure JFET J0 is connected to the first input end of power stage unit, in sheet, the output terminal of reference source unit 1 is connected to the input end of over-and under-voltage logical block 2, the output terminal of over-and under-voltage logical block 2 is connected to the second input end of power stage unit 4, the output terminal of power stage unit 4 is connected to another input end of over-and under-voltage logical block 2, it is characterized in that, the grid of high pressure JFET J0 is connected to the output terminal of error amplifier unit 3, the output terminal of reference source unit 1 is connected to an input end of error amplifier unit 3 in sheet, the output terminal of power stage unit 4 is connected to another input end of error amplifier unit 3.

For the ease of writing conveniently, the below makes following regulation: the output voltage signal of sheet internal power circuit is designated as: Vout; In sheet, the reference voltage signal of reference source unit output terminal output is designated as: S5; The signal that the error amplifier unit amplifies output terminal output is designated as: S4; The signal of over-and under-voltage logical block output terminal output is designated as: S3; The voltage signal of the source electrode of high pressure JFET is designated as: S1.

The error amplifier unit 3 here is a modular unit commonly used, can select according to particular problem, at this, its structure no longer is described in detail.In order to make the present invention clearer, the below specifically describes the structure of reference source unit 1 in sheet, over-and under-voltage logical block 2 and power stage unit 4 respectively, need to prove, double mode internal power circuit of the present invention is not limited to these structures.

In sheet, reference source unit 1 as shown in Figure 5, comprise: resistance R 11, R12, R13, R14, R15, PMOS pipe MP11, MP12, MP13, MP14, triode Q11, Q12, Q13, Q14, Q15, Q16, Q17, NMOS manages MN11, wherein an end of resistance R 11 is connected to sheet internal power circuit output terminal, and the other end is connected to the collector of triode Q11; The collector of triode Q11 and base stage short circuit, the emitter of triode Q11 are connected to the drain electrode of NMOS pipe MN11; The drain electrode of MN11 and grid short circuit, the source electrode of MN11 is connected to publicly, the source electrode of PMOS pipe MP11 is connected to sheet internal power circuit output terminal, and the grid of PMOS pipe MP11 is connected to the collector of triode Q11, and the drain electrode of PMOS pipe MP11 is connected to an end of resistance R 15; The other end of resistance R 15 is connected to publicly; The source electrode of MP12 is connected to power supply signal Vout, and the grid of PMOS pipe MP12 is connected to the drain electrode of MP11, and the drain electrode of MP12 is connected to the collector of triode Q13; The base stage of triode Q13 is connected to the collector of triode Q14, the emitter of triode Q13 is connected to publicly, the source electrode of PMOS pipe MP14 is connected to sheet internal power circuit output terminal, the grid of PMOS pipe MP14 is connected to the grid of MP13, and the drain electrode of PMOS pipe MP14 is connected to the drain electrode of the MP12 in the 3rd branch road; The source electrode of PMOS pipe MP13 is connected to sheet internal power circuit output terminal, the grid of PMOS pipe MP13 and drain electrode short circuit, and the drain electrode of PMOS pipe MP13 is connected to the collector of triode Q15; The base stage of triode Q15 is connected to the drain electrode of PMOS pipe MP12, and the emitter of triode Q15 is connected to the end of R12; The other end of resistance R 12 is connected to the collector of Q14; The base stage of triode Q14 is connected to the collector of triode Q17, and the emitter of Q14 is connected to an end of resistance R 14; The other end of resistance R 14 is connected to publicly; The end of R13 is connected to the emitter of triode Q15, and the other end of resistance R 13 is connected to the collector of triode Q17; The collector of triode Q17 and base stage short circuit, the emitter of triode Q17 is connected to publicly; The collector of triode Q12 is connected to sheet internal power circuit output terminal, the base stage of triode Q12 is connected to the drain electrode of PMOS pipe MP12, the collector of triode Q16 is connected to the emitter of Q12, the base stage of triode Q16 is connected to the base stage of triode Q17, and the emitter of triode Q16 is connected to publicly; The emitter of triode Q12 is namely the output terminal of reference source unit in sheet, and the reference voltage signal of generation is S5.

Its input signal is the output signal Vout of integrated circuit, R11, Q11, MN11, MP11, MP12, R15 is start-up circuit, and in the circuit power up, the MP12 tube grid begins to be low level, be high level again, make MP12 pipe unlatching work, make band-gap circuit partly open work, power on complete after, turn-off the MP12 pipe, thereby can partly not exert an influence to band gap.

Q14(Q14 is formed in parallel by 8 identical triodes), Q17, R14 produces the PTAT electric current, R12, the end of R13 is connected, and the other end is respectively the BE junction voltage of Q13 and Q17, can be similar to and think equal, the collector current I of Q14 and Q17 _C14And I _C17Only depend on R12 and R13, its PTAT electric current I _PTAtFor:

$I_{\mathrm{PTAt}}=\frac{\mathrm{\Δ}{V}_{\mathrm{BE}}}{R_{14}}=\frac{V_T\ln \frac{I_{c17}}{I_{s17}}-V_T\ln \frac{I_{c14}}{I_{s14}}}{R_4}=\frac{V_T\ln \frac{I_{c17}*I_{s14}}{I_{c14}*I_{s17}}}{R_4}$

$=\frac{V_T\ln \frac{I_{c17}*b}{I_{c14}}}{R_{14}}=\frac{V_T\ln \frac{R_{12}*b}{R_{13}}}{R_{14}}$

Here, b is Q14, the ratio (being made as 8 here) of Q17 launch site area, Δ V _BEBe the voltage difference of the BE of Q14 knot with the BE knot of Q17, I _s17And I _s14Be respectively the Leakage Current of Q14 and Q17, V _TBe thermal voltage, R ₁₄Resistance value for resistance R 14.

The PTAT electric current that produces produces pressure drop on R12, form reference voltage N3 with the VBE voltage stack of Q13, it is namely the emitter voltage of Q15, Q12, Q16 is efferent duct, improve the driving force of reference source, S5 voltage approximates the size of N3 voltage, is the final reference voltage of reference source unit output in sheet.

By upper analysis as can be known, reference voltage S5 is:

$\mathrm{<figure-callout\; id="5"\; label="S"\; filenames="HDA0000045740070000032.png"\; state="\{\{state\}\}">S</figure-callout>}5=V_{\mathrm{BE}}+\frac{R_{12}{V}_T\ln \frac{R_{12}*b}{R_{13}}}{R_{14}}$

Here, V _BEBe the voltage of the BE of Q13 knot, R ₁₂, R ₁₃, R ₁₄Be respectively the resistance value of resistance R 12, R13, R14.

Over-and under-voltage logical block 2 as shown in Figure 6, comprise resistance R 21, resistance R 22, resistance R 23, Sheffer stroke gate A1, Sheffer stroke gate A2, Sheffer stroke gate A3, phase inverter B1, phase inverter B2, phase inverter B3, comparator C 1 and comparator C 2, wherein, one end of resistance R 21 is connected to sheet internal power circuit output terminal, and the other end of resistance R 21 is connected to the negative input end of comparator C 2; Resistance R 22 1 ends are connected to the negative input end of comparator C 2, and the other end of resistance R 22 is connected to the positive input terminal of comparator C 1; R23 one end is connected to the positive input terminal of comparator C 1, and the other end of resistance R 23 is connected to publicly; The positive input terminal of comparator C 2 is connected to the output terminal of reference source unit 1 in sheet, and its output terminal is connected to the input end of phase inverter B1; The negative input end of comparator C 1 is connected to the output terminal of reference source unit 1 in sheet, and its output terminal is connected to the input end of phase inverter B2; The output terminal of phase inverter B1 is connected to the input end of Sheffer stroke gate A1; Another input end of Sheffer stroke gate A1 is connected to the output terminal of Sheffer stroke gate A2, and the output terminal of Sheffer stroke gate A1 is connected to the input end of Sheffer stroke gate A2; Another input end of Sheffer stroke gate A2 is connected to the output terminal of phase inverter B2; The input end of Sheffer stroke gate A3 is connected to the output terminal of comparator C 2, another input end of Sheffer stroke gate A3 is connected to the output terminal of Sheffer stroke gate A1, the output terminal of Sheffer stroke gate A3 is connected to the input end of phase inverter B3, the output terminal of phase inverter B3 is the output terminal of over-and under-voltage logical block 2, and the signal of generation is S3.

The output Vout of sheet internal power circuit is input to the resistor network that is in series by R21, R22, R23, by producing D1, D2 signal after the resistor network dividing potential drop.D1, D2 signal respectively in comparator C 1 and comparator C 2 with sheet in the S5 signal that produces of reference source unit 1 compare, wherein, S5 be the reference level that has nothing to do with Vout.More namely produce digital signal D3 and D4 signal.D3 and D4 obtain the output signal S3 of final over-and under-voltage logical block 2 by a series of logical operations, its truth table is as shown in table 1:

Table 1

Vout voltage	D3,D4	S3
			Vout<4.8V	00	0
4.8V<Vout<5.8V	01	0
			Vout>5.8V	10	1

The structural drawing of power stage unit 4 as shown in Figure 7, comprise resistance R 40, NMOS pipe MN41, diode D40, NMOS pipe MN42 and electrochemical capacitor C40, one end of resistance R 40 is connected to the source electrode of high pressure JFET, and the other end of resistance R 40 is connected to the drain electrode of NMOS pipe MN41; The grid of NMOS pipe MN41 is connected to the output terminal of over-and under-voltage logical block, and the source electrode of NMOS pipe MN41 is connected to the anode of diode D40; The negative electrode of diode D40 is connected to publicly, the drain electrode of NMOS pipe MN42 is connected to the source electrode of high pressure JFET, the grid of NMOS pipe MN42 is connected to the drain electrode of NMOS pipe MN41, the source electrode of NMOS pipe MN42 is connected to the positive pole of electrochemical capacitor C40, the negative pole of electrochemical capacitor C40 is connected to publicly, the positive pole of electrochemical capacitor C40 is sheet internal power circuit output terminal, is the output signal Vout of sheet internal power circuit.Can find out, an end of the resistance R 40 here is as the first input end of power stage unit, and the grid of NMOS pipe MN41 is as the second input end of power stage unit.

It is digital signal that input signal has S1 current signal, S3.When S3 was low (high level equals Vout, and low level is 0), MN1 managed shutoff, and at first the S1 signal charges to the MN42 tube grid until the MN42 pipe is opened by R40, and then, S1 charges to electrochemical capacitor C40 by the MN42 pipe.Generally, the size of S1 signal is subjected to error amplifier unit 3 adjustings, can be that the Vout signal stabilization is in the 5V left and right with electrochemical capacitor C40 top crown current potential.When Vout holds owing to occurring ultralight year or zero load, when current potential is increased to 5.8V suddenly, S3 becomes height (the S3 logical value sees Table 1) under the over-and under-voltage logic control, MN41 manages unlatching, and the grid potential of MN42 pipe is dragged down, and the MN42 pipe is turn-offed, the S1 signal is flowed through R40, MN1 extremely publicly, to C40 charging, until C40 top crown current potential is the Vout current potential when returning to 4.8V, S3 will be height again.Wherein, consider between MN41, the source leakage of MN42 pipe and will bear the above pressure reduction of 10V, preferably use the above middle pressure pipe of withstand voltage 15V.

The sheet internal power circuit course of work of the present embodiment is as follows:

In sheet, the reference source unit is take the output voltage signal Vout of sheet internal power circuit as power supply, produce a stable level signal S5 who has nothing to do with Vout, S5 is input to error amplifier unit and over-and under-voltage logical block as differential amplification and reference level relatively.

Error amplifier unit 3 has determined the size of Vout signal, and the below equals the course of work of 5V double mode internal power circuit as example illustrates take Vout.In order to stablize the voltage of Vout signal, the Vout signal will feed back to error amplifier unit and over-and under-voltage logical block, Vout in the error amplifier unit with sheet in the S5 signal that produces of reference source unit compare, the difference signal that Vout signal and S5 signal produce is amplified by the error amplifier unit, produces the S4 signal.The S4 signal is input to the grid of high pressure JFET J0, and during higher than 5V, the S4 signal diminishes when Vout voltage, controls the current signal S1 that high pressure JFET J0 reduces to power Vout is reduced; During lower than 5V, it is large that the S4 signal becomes as Vout, controls high pressure JFETJ0 and increase current signal S1 Vout is raise.Vout will be stabilized in like this 5V left and right.

Meanwhile, Vout also can feed back to over-and under-voltage logical block 2, in this unit with sheet in the S5 signal that produces of reference source unit compare, produce the S3 signal, as Vout too high (higher than 5.8V) to such an extent as in the time of only can't regulating by error amplifier unit 3, the S3 signal can stop utilizing the charging of S1 signal by power ratio control output unit 4, and Vout is descended; When (being not less than 4.8V), S3 signal controlling power output circuit utilizes the S1 signal to continue charging in Vout drops to error amplifier unit 3 adjustable extents.

Here utilize high pressure JFET J0, make double mode internal power circuit that wider input voltage regulation scope can be arranged, and then increased the output voltage range of adjustment.

Here the explanation usefulness of the present invention as an example of 5V example, if only utilize the over-and under-voltage logical block output signal be controlled between 4.8-5.8V, obviously ripple is larger; If only utilize the error amplifier unit, when output signal extremely higher (for example high to more than 5.8V) occurring, all the time at continued power, so returning to normal value (5V), voltage needs the longer time due to the source electrode of high pressure JFET.Error amplifier of the present invention unit 3 and over-and under-voltage logical block 2 are used in combination, stable output signal is in the 5V left and right, ripple is very little, come the power ratio control output unit to have the NMOS in 4 to manage MN41, MN42 by over-and under-voltage logical block 2, make its function with switch, and then make voltage return to normal value (5V) short time of needs hatred.

Those of ordinary skill in the art will appreciate that, embodiment described here is in order to help reader understanding's principle of the present invention, should to be understood to that the protection domain of inventing is not limited to such special statement and embodiment.Everyly make various possible being equal to according to foregoing description and replace or change, all be considered to belong to the protection domain of claim of the present invention.

Claims (4)

1. double mode internal power circuit, comprise reference source unit in sheet, the over-and under-voltage logical block, the error amplifier unit, power stage unit and high pressure JFET, external power source is input to the drain electrode of high pressure JFET, the source electrode of high pressure JFET is connected to the first input end of power stage unit, in sheet, the output terminal of reference source unit is connected to an input end of over-and under-voltage logical block, the output terminal of over-and under-voltage logical block is connected to the second input end of power stage unit, the output terminal of power stage unit is connected to another input end of over-and under-voltage logical block, it is characterized in that, the grid of high pressure JFET is connected to the output terminal of error amplifier unit, in sheet, the output terminal of reference source unit is connected to an input end of error amplifier unit, the output terminal of power stage unit is connected to another input end of error amplifier unit.

2. double mode internal power circuit according to claim 1, it is characterized in that, described interior reference source unit comprises: resistance R 11, R12, R13, R14, R15, PMOS pipe MP11, MP12, MP13, MP14, triode Q11, Q12, Q13, Q14, Q15, Q16, Q17, NMOS manages MN11, and wherein an end of resistance R 11 is connected to sheet internal power circuit output terminal, and the other end is connected to the collector of triode Q11; The collector of triode Q11 and base stage short circuit, the emitter of triode Q11 are connected to the drain electrode of NMOS pipe MN11; The drain electrode of MN11 and grid short circuit, the source electrode of MN11 is connected to publicly, the source electrode of PMOS pipe MP11 is connected to sheet internal power circuit output terminal, and the grid of PMOS pipe MP11 is connected to the collector of triode Q11, and the drain electrode of PMOS pipe MP11 is connected to an end of resistance R 15; The other end of resistance R 15 is connected to publicly; The source electrode of MP12 is connected to sheet internal power circuit output terminal, and the grid of PMOS pipe MP12 is connected to the drain electrode of MP11, and the drain electrode of MP12 is connected to the collector of triode Q13; The base stage of triode Q13 is connected to the collector of triode Q14, the emitter of triode Q13 is connected to publicly, the source electrode of PMOS pipe MP14 is connected to sheet internal power circuit output terminal, the grid of PMOS pipe MP14 is connected to the grid of MP13, and the drain electrode of PMOS pipe MP14 is connected to the drain electrode of PMOS pipe MP12; The source electrode of PMOS pipe MP13 is connected to sheet internal power circuit output terminal, the grid of PMOS pipe MP13 and drain electrode short circuit, and the drain electrode of PMOS pipe MP13 is connected to the collector of triode Q15; The base stage of triode Q15 is connected to the drain electrode of PMOS pipe MP12, and the emitter of triode Q15 is connected to the end of R12; The other end of resistance R 12 is connected to the collector of Q14; The base stage of triode Q14 is connected to the collector of triode Q17, and the emitter of Q14 is connected to an end of resistance R 14; The other end of resistance R 14 is connected to publicly; One end of resistance R 13 is connected to the emitter of triode Q15, and the other end of resistance R 13 is connected to the collector of triode Q17; The collector of triode Q17 and base stage short circuit, the emitter of triode Q17 is connected to publicly; The collector of triode Q12 is connected to sheet internal power circuit output terminal, the base stage of triode Q12 is connected to the drain electrode of PMOS pipe MP12, the collector of triode Q16 is connected to the emitter of Q12, the base stage of triode Q16 is connected to the base stage of triode Q17, and the emitter of triode Q16 is connected to publicly; The emitter of triode Q12 is namely the output terminal of reference source unit in sheet.

3. double mode internal power circuit according to claim 1, it is characterized in that, described over-and under-voltage logical block, comprise resistance R 21, resistance R 22, resistance R 23, Sheffer stroke gate A1, Sheffer stroke gate A2, Sheffer stroke gate A3, phase inverter B1, phase inverter B2, phase inverter B3, comparator C 1 and comparator C 2, wherein, one end of resistance R 21 is connected to sheet internal power circuit output terminal, and the other end of resistance R 21 is connected to the negative input end of comparator C 2; Resistance R 22 1 ends are connected to the negative input end of comparator C 2, and the other end of resistance R 22 is connected to the positive input terminal of comparator C 1; Resistance R 23 1 ends are connected to the positive input terminal of comparator C 1, and the other end of resistance R 23 is connected to publicly; The positive input terminal of comparator C 2 is connected to the output terminal of reference source unit in sheet, and its output terminal is connected to the input end of phase inverter B1; The negative input end of comparator C 1 is connected to the output terminal of reference source unit in sheet, and its output terminal is connected to the input end of phase inverter B2; The output terminal of phase inverter B1 is connected to the input end of Sheffer stroke gate A1; Another input end of Sheffer stroke gate A1 is connected to the output terminal of Sheffer stroke gate A2, and the output terminal of Sheffer stroke gate A1 is connected to the input end of Sheffer stroke gate A2; Another input end of Sheffer stroke gate A2 is connected to the output terminal of phase inverter B2; The input end of Sheffer stroke gate A3 is connected to the output terminal of comparator C 2, another input end of Sheffer stroke gate A3 is connected to the output terminal of Sheffer stroke gate A1, the output terminal of Sheffer stroke gate A3 is connected to the input end of phase inverter B3, and the output terminal of phase inverter B3 is the output terminal of over-and under-voltage logical block.

4. double mode internal power circuit according to claim 1, it is characterized in that, described power stage unit, comprise resistance R 40, NMOS pipe MN41, diode D40, NMOS pipe MN42 and electrochemical capacitor C40, one end of resistance R 40 is connected to the source electrode of high pressure JFET, and the other end of resistance R 40 is connected to the drain electrode of NMOS pipe MN41; The grid of NMOS pipe MN41 is connected to the output terminal of over-and under-voltage logical block, and the source electrode of NMOS pipe MN41 is connected to the anode of diode D40; The negative electrode of diode D40 is connected to publicly, the drain electrode of NMOS pipe MN42 is connected to the source electrode of high pressure JFET, the grid of NMOS pipe MN42 is connected to the drain electrode of NMOS pipe MN41, the source electrode of NMOS pipe MN42 is connected to the positive pole of electrochemical capacitor C40, the negative pole of electrochemical capacitor C40 is connected to publicly, and the positive pole of electrochemical capacitor C40 is the output terminal of sheet internal power circuit.

Images