CN109787567B - Dual-mode signal amplifying circuit for signal receiver - Google Patents
Dual-mode signal amplifying circuit for signal receiver Download PDFInfo
- Publication number
- CN109787567B CN109787567B CN201711106775.7A CN201711106775A CN109787567B CN 109787567 B CN109787567 B CN 109787567B CN 201711106775 A CN201711106775 A CN 201711106775A CN 109787567 B CN109787567 B CN 109787567B
- Authority
- CN
- China
- Prior art keywords
- node
- signal
- output
- current source
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Amplifiers (AREA)
- Logic Circuits (AREA)
Abstract
The invention provides a dual-mode signal amplifying circuit, which comprises: a first input terminal and a second input terminal for receiving the differential input signal; a first output terminal and a second output terminal for providing a differential output signal; first to third current sources; a first switch located between the first current source and the first node and controlled by the first input end; the second switch is positioned between the first current source and the second node and is controlled by the second input end; a third switch located between the first node and the fixed potential terminal and controlled by a third node; a fourth switch located between the second node and the fixed potential terminal and controlled by the third node; a fifth switch located between the second current source and the fixed potential terminal and controlled by the first node; and a sixth switch located between the third current source and the fixed potential terminal and controlled by the second node.
Description
Technical Field
The present invention relates to a signal receiver, and more particularly, to a dual-mode signal amplifying circuit used in a signal receiver.
Background
The performance of the signal receiver is degraded by the interference of out-of-band signals (out-of-band signals). The unit gain bandwidth (unity gain bandwidth) of the signal amplifying circuit in the signal receiver is increased, so that the capability of the signal receiver for resisting out-of-band signal interference can be improved. The capacitance of the compensation capacitor in the conventional signal amplification circuit is reduced, which can increase the unity gain bandwidth of the signal amplification circuit, but the side effect can cause the stability of the signal amplification circuit to be deteriorated, thereby causing negative influence on the operation performance of the signal receiver.
Disclosure of Invention
Therefore, how to effectively increase the unit gain bandwidth of the signal amplification circuit and improve the stability of the signal amplification circuit is a problem to be solved.
The present specification provides an embodiment of a dual-mode signal amplification circuit for use in a signal receiver, comprising: a first input terminal for receiving a first input signal; a second input terminal for receiving a second input signal; a first output terminal for providing a first output signal; a second output terminal for providing a second output signal; a first current source configured to generate a first current according to a bias signal; a second current source configured to generate a second current according to the bias signal; a third current source configured to generate a third current according to the bias signal; a first switch, located between the output end of the first current source and a first node, and controlled by the first input end; a second switch, located between the output end of the first current source and a second node, and controlled by the second input end; a third switch, located between the first node and a fixed potential terminal, and controlled by a third node; a fourth switch, located between the second node and a fixed potential terminal, and controlled by the third node; a fifth switch, located between the output terminal of the second current source and a fixed potential terminal, and controlled by the first node; a sixth switch, located between the output terminal of the third current source and a fixed potential terminal, and controlled by the second node; a fourth current source configured to generate a fourth current according to the bias signal; a seventh switch, located between the output terminal of the fourth current source and the second output terminal, and controlled by the first input terminal; and an eighth switch, located between the output terminal of the fourth current source and the first output terminal, and controlled by the second input terminal.
The present specification further provides an embodiment of a dual-mode signal amplifying circuit for use in a signal receiver, comprising: a first input terminal for receiving a first input signal; a second input terminal for receiving a second input signal; a first output terminal for providing a first output signal; a second output terminal for providing a second output signal; a first current source configured to generate a first current according to a bias signal; a second current source configured to generate a second current according to the second input signal; a third current source configured to generate a third current according to the first input signal; a first switch, located between the output end of the first current source and a first node, and controlled by the first input end; a second switch, located between the output end of the first current source and a second node, and controlled by the second input end; a third switch, located between the first node and a fixed potential end, and controlled by a third node; a fourth switch, located between the second node and a fixed potential terminal, and controlled by the third node; a fifth switch, located between the output terminal of the second current source and a fixed potential terminal, and controlled by the first node; and a sixth switch, located between the output terminal of the third current source and a fixed potential terminal, and controlled by the second node.
One advantage of the above embodiments is that the compensation capacitor in the dual-mode signal amplifying circuit can be minimized or even omitted, so that the unity gain bandwidth of the dual-mode signal amplifying circuit can be effectively increased, thereby improving the capability of the related signal receiver to resist out-of-band signal interference.
Another advantage of the foregoing embodiments is that a transconductance value (transconductance value) between the input terminal and the output terminal of the dual-mode signal amplifying circuit can be increased, so that the operation stability of the dual-mode signal amplifying circuit can be effectively improved.
Other advantages of the present invention will be explained in more detail with reference to the following description and accompanying drawings.
Drawings
Fig. 1 is a simplified functional block diagram of a dual-mode signal amplifying circuit according to an embodiment of the present invention.
Fig. 2 is a simplified functional block diagram of a dual-mode signal amplifying circuit according to another embodiment of the present invention.
Description of the reference numerals:
100. dual-mode signal amplifying circuit
101. 103 input terminal
105. 107 output terminal
111. 113, 115, 117 node
120. Bias circuit
131. 133, 135, 170 current source
141. 142, 143, 144, 145, 146, 181, 183 switches
150. Common mode feedback circuit
151. Comparator with a comparator circuit
153. 155 feedback resistance
161. 163 compensation capacitance
191. 193 capacitance
195. 197 resistance
Detailed Description
Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference numerals denote the same or similar elements or method flows.
Fig. 1 is a simplified functional block diagram of a dual-mode signal amplifying circuit 100 according to an embodiment of the present invention. The dual-mode signal amplifying circuit 100 is an amplifying circuit applied in a signal receiver, and can perform a differential mode (differential mode) operation and a common mode (common mode) operation.
As shown in fig. 1, the dual-mode signal amplifying circuit 100 includes a first input terminal 101, a second input terminal 103, a first output terminal 105, a second output terminal 107, a bias circuit 120, a first current source 131, a second current source 133, a third current source 135, a first switch 141, a second switch 142, a third switch 143, a fourth switch 144, a fifth switch 145, a sixth switch 146, a common-mode feedback circuit 150, a first compensation capacitor 161, and a second compensation capacitor 163.
The first input terminal 101 is for receiving a first input signal IN _ P. The second input terminal 103 is for receiving a second input signal IN _ N. The first output terminal 105 is for providing a first output signal OUT _ P. The second output terminal 107 is used for providing a second output signal OUT _ N. The first input signal IN _ P and the second input signal IN _ N form a pair of differential input signals, and the first output signal OUT _ P and the second output signal OUT _ N form a pair of differential output signals.
The bias circuit 120 is arranged to generate a bias signal Vbp. The first current source 131 is configured to generate a first current i1 according to the bias signal Vbp. The second current source 133 is configured to generate a second current i2 according to the bias signal Vbp. The third current source 135 is configured to generate a third current i3 according to the bias signal Vbp.
The first switch 141 is located between the output terminal of the first current source 131 and a first node 111, and is controlled by the first input terminal 101. The second switch 142 is located between the output terminal of the first current source 131 and a second node 113, and is controlled by the second input terminal 103. The third switch 143 is located between the first node 111 and a fixed potential terminal (e.g., ground) and is controlled by a third node 115. The fourth switch 144 is located between the second node 113 and a fixed potential terminal (e.g., ground) and is controlled by the third node 115. The fifth switch 145 is located between the output terminal of the second current source 133 and a fixed potential terminal (e.g., ground terminal), and is controlled by the first node 111. The sixth switch 146 is located between the output terminal of the third current source 135 and a fixed potential terminal (e.g., ground terminal), and is controlled by the second node 113.
The common mode feedback circuit 150 is coupled to the first output terminal 105 and the second output terminal 107, and configured to generate and output a feedback signal Vcm to the third node 115 according to the first output signal OUT _ P and the second output signal OUT _ N, so as to determine a dc level of a common mode voltage (common mode voltage) of the dual mode signal amplifying circuit 100.
The first compensation capacitor 161 is located between the first node 111 and the first output terminal 105, and the second compensation capacitor 163 is located between the second node 113 and the second output terminal 107. For example, in the embodiment of fig. 1, one end of the first compensation capacitor 161 is coupled to the first node 111, and the other end is coupled to the first output terminal 105 and the output terminal of the second current source 133. One end of the second compensation capacitor 163 is coupled to the second node 113, and the other end is coupled to the second output terminal 107 and the output terminal of the third current source 135.
As can also be seen from the content of fig. 1, the first switch 141 and the third switch 143 are connected in series, and the first node 111 is located between the first switch 141 and the third switch 143. The second switch 142 and the fourth switch 144 are connected in series, and the second node 113 is located between the second switch 142 and the fourth switch 144. The third switch 143 is connected in parallel with the fifth switch 145, and the first output terminal 105 is coupled between the output terminal of the second current source 133 and the fifth switch 145. The fourth switch 144 and the sixth switch 146 are connected in parallel, and the second output terminal 107 is coupled between the output terminal of the third current source 135 and the sixth switch 146.
In order to effectively increase the unit gain bandwidth of the dual-mode signal amplifying circuit 100, the first compensation capacitor 161 and the second compensation capacitor 163 can be implemented by using smaller capacitors, so as to reduce the capacitance of the two capacitors. Therefore, the ability of the signal receiver of the dual-mode signal amplifying circuit 100 to resist out-of-band signal interference can be effectively improved.
Please note that, the dual-mode signal amplifying circuit 100 in the embodiment of fig. 1 further includes a fourth current source 170, a seventh switch 181, and an eighth switch 183.
The fourth current source 170 is configured to generate a fourth current i4 according to the bias signal Vbp. The seventh switch 181 is located between the output terminal of the fourth current source 170 and the second output terminal 107, and is controlled by the first input terminal 101. The eighth switch 183 is located between the output terminal of the fourth current source 170 and the first output terminal 105, and is controlled by the second input terminal 103.
The fourth current source 170, the seventh switch 181, and the eighth switch 183 are configured to equivalently increase a transconductance value (transconductance value) between the input terminal and the output terminal of the dual-mode signal amplifying circuit 100, so that the stability of the dual-mode signal amplifying circuit 100 during the differential operation can be effectively improved.
In addition, the dual-mode signal amplifying circuit 100 in the embodiment of fig. 1 further includes a first capacitor 191 and a second capacitor 193. The first capacitor 191 is located between the first node 111 and the third node 115, and the second capacitor 193 is located between the second node 113 and the third node 115.
The first capacitor 191 and the second capacitor 193 can increase the capacitance in the signal feedback path of the dual-mode signal amplifying circuit 100, so that the stability of the dual-mode signal amplifying circuit 100 in the common mode operation can be effectively improved.
In practice, a first resistor 195 connected in series with the first capacitor 191 may be further disposed between the first node 111 and the third node 115, and a second resistor 197 connected in series with the second capacitor 193 may be further disposed between the second node 113 and the third node 115, so as to further improve the stability of the dual-mode signal amplifying circuit 100 in the common mode operation.
In practice, the current sources 131, 133, 135, 170 and the switches 141, 142, 143, 144, 145, and 146 may be implemented by appropriate field effect transistors.
The common mode feedback circuit 150 may be implemented with a suitable comparator. For example, in the embodiment of fig. 1, the common mode feedback circuit 150 includes a comparator 151, a first feedback resistor 153, and a second feedback resistor 155. The first feedback resistor 153 is coupled between the first output terminal 105 and a fourth node 117, and the second feedback resistor 155 is coupled between the second output terminal 107 and the fourth node 117. By properly selecting the resistance values of the first feedback resistor 153 and the second feedback resistor 155, a common mode voltage signal Vfb with a proper magnitude can be obtained at the fourth node 117. The comparator 151 is coupled to the third node 115 and configured to compare the common mode voltage signal Vfb with a predetermined reference signal Vref to generate the aforementioned feedback signal Vcm.
As can be seen from the foregoing description, the combination of the fourth current source 170, the seventh switch 181, and the eighth switch 183 in the dual-mode signal amplifying circuit 100 can effectively improve the stability of the dual-mode signal amplifying circuit 100 when performing the differential mode operation, and the combination of the first capacitor 191, the second capacitor 193, the first resistor 195, and the second resistor 197 in the dual-mode signal amplifying circuit 100 can effectively improve the stability of the dual-mode signal amplifying circuit 100 when performing the common mode operation.
Therefore, the first compensation capacitor 161 and the second compensation capacitor 163 of the dual-mode signal amplifying circuit 100 can be minimized during circuit design, so as to effectively increase the unity gain bandwidth of the dual-mode signal amplifying circuit 100, and further improve the capability of the related signal receiver to resist out-of-band signal interference.
In other words, the structure of the dual-mode signal amplifying circuit 100 can not only increase the unit gain bandwidth of the dual-mode signal amplifying circuit 100, but also maintain or improve the stability during the differential operation and/or the common mode operation.
Fig. 2 is a simplified functional block diagram of a dual-mode signal amplifying circuit 100 according to another embodiment of the present invention.
The embodiment of fig. 2 has many similarities with the embodiment of fig. 1 described above, but in the embodiment of fig. 2, the combination of the fourth current source 170, the seventh switch 181, and the eighth switch 183 described above in fig. 1 is omitted.
IN addition, IN the embodiment of fig. 2, the second input signal IN _ N is used as the control signal of the second current source 133, and the first input signal IN _ P is used as the control signal of the third current source 135. IN other words, IN the embodiment of fig. 2, the second current source 133 is configured to generate the second current i2 according to the second input signal IN _ N, and the third current source 135 is configured to generate the third current i3 according to the first input signal IN _ P.
After the control mechanisms of the second current source 133 and the third current source 135 are changed to the manner of fig. 2, the transconductance value between the input end and the output end of the dual-mode signal amplifying circuit 100 can be equivalently increased, so that the stability of the dual-mode signal amplifying circuit 100 in the differential operation can be effectively improved.
The foregoing descriptions regarding the connections, implementations, operation, and related advantages of other elements in fig. 1 also apply to the embodiment of fig. 2. For the sake of brevity, the description is not repeated here.
Please note that the architectures shown in FIG. 1 and FIG. 2 are only exemplary embodiments, and are not intended to limit the practical implementation of the present invention. For example, in some embodiments, the first compensation capacitor 161 and the second compensation capacitor 163 in the dual-mode signal amplifying circuit 100 may be implemented by only parasitic capacitors existing in the circuit. In this case, the dual-mode signal amplifying circuit 100 does not need to have a physical compensation capacitor.
In some embodiments where the stability requirement for performing the common mode operation is low, the first resistor 195 and the second resistor 197 may be omitted. In some embodiments, in which the stability of the common mode operation is not a concern, the first capacitor 191 and the second capacitor 193 can be omitted.
As can be seen from the foregoing description, the compensation capacitor in the dual-mode signal amplifying circuit 100 can be minimized or even omitted, so that the unit gain bandwidth of the dual-mode signal amplifying circuit 100 can be effectively increased, and the capability of the related signal receiver to resist the out-of-band signal interference can be improved.
In addition, by the operation of the fourth current source 170, the seventh switch 181 and the eighth switch 183, the stability of the dual-mode signal amplifying circuit 100 in differential operation can be effectively improved, so that the decrease of the operation performance of the related signal receiver due to the decrease of the compensation capacitance in the dual-mode signal amplifying circuit 100 can be avoided.
Certain terms are used throughout the description and claims to refer to particular elements, and those skilled in the art may refer to like elements by different names. The present specification and claims do not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Also, the term "coupled" is intended to include any direct or indirect connection. Therefore, if a first element is coupled to a second element, the first element can be directly connected to the second element through an electrical connection or a signal connection such as wireless transmission or optical transmission, or indirectly connected to the second element through another element or a connection means.
The description of "and/or" as used in this specification is inclusive of any combination of one or more of the listed items. In addition, any reference to singular is intended to include the plural unless the specification specifically states otherwise.
The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the present invention.
Claims (9)
1. A dual-mode signal amplification circuit (100) for use in a signal receiver, comprising:
a first input (101) for receiving a first input signal;
a second input terminal (103) for receiving a second input signal;
a first output terminal (105) for providing a first output signal;
a second output (107) for providing a second output signal;
a first current source (131) configured to generate a first current according to a bias signal;
a second current source (133) configured to generate a second current according to the bias signal;
a third current source (135) configured to generate a third current according to the bias signal;
a first switch (141) located between the output of the first current source (131) and a first node (111) and controlled by the first input (101);
a second switch (142) located between the output of the first current source (131) and a second node (113) and controlled by the second input (103);
a third switch (143) located between the first node (111) and a fixed potential terminal and controlled by a third node (115);
a fourth switch (144) located between the second node (113) and a fixed potential terminal and controlled by the third node (115);
a fifth switch (145) between the output terminal of the second current source (133) and a terminal of a fixed potential and controlled by the first node (111);
a sixth switch (146) between the output of the third current source (135) and a fixed potential terminal and controlled by the second node (113);
a fourth current source (170) configured to generate a fourth current according to the bias signal;
a seventh switch (181) between the output of the fourth current source (170) and the second output (107) and controlled by the first input (101); and
an eighth switch (183) is located between the output of the fourth current source (170) and the first output (105), and is controlled by the second input (103).
2. The dual-mode signal amplification circuit (100) of claim 1, further comprising:
a bias circuit (120) configured to generate the bias signal; and
a common mode feedback circuit (150), coupled to the first output terminal (105) and the second output terminal (107), configured to generate and output a feedback signal to the third node (115) according to the first output signal and the second output signal.
3. The dual-mode signal amplification circuit (100) of claim 2, further comprising:
a first capacitor (191) between the first node (111) and the third node (115); and
a second capacitor (193) between the second node (113) and the third node (115).
4. The dual-mode signal amplification circuit (100) of claim 3, further comprising:
a first resistor (195) between the first node (111) and the third node (115) and connected in series with the first capacitor (191); and
a second resistor (197) between the second node (113) and the third node (115) and in series with the second capacitor (193).
5. The dual-mode signal amplification circuit (100) of any of claims 1-4, wherein the first input signal and the second input signal form a pair of differential input signals and the first output signal and the second output signal form a pair of differential output signals.
6. A dual-mode signal amplification circuit (100) for use in a signal receiver, comprising:
a first input (101) for receiving a first input signal;
a second input terminal (103) for receiving a second input signal;
a first output terminal (105) for providing a first output signal;
a second output (107) for providing a second output signal;
a first current source (131) configured to generate a first current according to a bias signal;
a second current source (133) configured to generate a second current according to the second input signal;
a third current source (135) configured to generate a third current according to the first input signal;
a first switch (141) located between the output of the first current source (131) and a first node (111) and controlled by the first input (101);
a second switch (142) located between the output of the first current source (131) and a second node (113) and controlled by the second input (103);
a third switch (143) located between the first node (111) and a fixed potential terminal and controlled by a third node (115);
a fourth switch (144) located between the second node (113) and a fixed potential terminal and controlled by the third node (115);
a fifth switch (145) between the output terminal of the second current source (133) and a terminal of a fixed potential and controlled by the first node (111); and
a sixth switch (146) between the output terminal of the third current source (135) and a fixed potential terminal and controlled by the second node (113), the dual-mode signal amplifying circuit further comprising:
a first capacitor (191) between the first node (111) and the third node (115); and
a second capacitor (193) located between the second node (113) and the third node (115).
7. The dual-mode signal amplification circuit (100) of claim 6, further comprising:
a bias circuit (120) configured to generate the bias signal; and
a common mode feedback circuit (150), coupled to the first output terminal (105) and the second output terminal (107), configured to generate and output a feedback signal to the third node (115) according to the first output signal and the second output signal.
8. The dual-mode signal amplification circuit (100) of claim 6, further comprising:
a first resistor (195) between the first node (111) and the third node (115) and connected in series with the first capacitor (191); and
a second resistor (197) between the second node (113) and the third node (115) and in series with the second capacitor (193).
9. The dual-mode signal amplification circuit (100) of any of claims 6-8, wherein the first input signal and the second input signal form a pair of differential input signals and the first output signal and the second output signal form a pair of differential output signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711106775.7A CN109787567B (en) | 2017-11-10 | 2017-11-10 | Dual-mode signal amplifying circuit for signal receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711106775.7A CN109787567B (en) | 2017-11-10 | 2017-11-10 | Dual-mode signal amplifying circuit for signal receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109787567A CN109787567A (en) | 2019-05-21 |
| CN109787567B true CN109787567B (en) | 2022-11-11 |
Family
ID=66485418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711106775.7A Active CN109787567B (en) | 2017-11-10 | 2017-11-10 | Dual-mode signal amplifying circuit for signal receiver |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109787567B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101022266A (en) * | 2006-09-28 | 2007-08-22 | 威盛电子股份有限公司 | Power amplifier |
| CN102289237A (en) * | 2011-01-27 | 2011-12-21 | 电子科技大学 | Dual-mode on-chip power supply circuit |
| CN105391409A (en) * | 2015-11-11 | 2016-03-09 | 深圳大学 | Low-ripple switched-capacitor common-mode feedback structure |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100833624B1 (en) * | 2007-03-26 | 2008-05-30 | 삼성전자주식회사 | Fully differential ab class amplifier and ab amplifying method using single ended two stage amplifier |
| US20150061767A1 (en) * | 2013-08-28 | 2015-03-05 | Texas Instruments Incorporated | Telescopic Amplifier with Improved Common Mode Settling |
-
2017
- 2017-11-10 CN CN201711106775.7A patent/CN109787567B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101022266A (en) * | 2006-09-28 | 2007-08-22 | 威盛电子股份有限公司 | Power amplifier |
| CN102289237A (en) * | 2011-01-27 | 2011-12-21 | 电子科技大学 | Dual-mode on-chip power supply circuit |
| CN105391409A (en) * | 2015-11-11 | 2016-03-09 | 深圳大学 | Low-ripple switched-capacitor common-mode feedback structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109787567A (en) | 2019-05-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8288895B2 (en) | High-power tunable capacitor | |
| US7271663B2 (en) | Operational amplifier output stage and method | |
| CN107370465B (en) | High-precision broadband programmable gain amplifier | |
| US9263993B2 (en) | Low pass filter with common-mode noise reduction | |
| US20070096820A1 (en) | Differential amplifier and active load for the same | |
| US8310308B1 (en) | Wide bandwidth class C amplifier with common-mode feedback | |
| US10474173B2 (en) | Voltage regulator having a phase compensation circuit | |
| US9479120B2 (en) | Fully differential signal system including common mode feedback circuit | |
| CN109564249B (en) | Current sense amplifier architecture and level shifter | |
| CN108429545B (en) | Adjustable resistance type virtual resistor | |
| US9203364B2 (en) | DC offset canceller | |
| US9948244B1 (en) | Amplifier with adjustable gain | |
| US8031002B2 (en) | Buffer amplifier | |
| US9621116B2 (en) | Active load circuit and semiconductor integrated circuit | |
| CN109787567B (en) | Dual-mode signal amplifying circuit for signal receiver | |
| US9401679B1 (en) | Apparatus and method for improving power supply rejection ratio | |
| US7868688B2 (en) | Leakage independent very low bandwith current filter | |
| US9099970B2 (en) | Class AB differential line drivers | |
| US7633343B2 (en) | Fully differential amplifier | |
| US11223328B2 (en) | Dual-mode signal amplifying circuit of signal receiver | |
| US8022758B2 (en) | Impedance matching circuit and method thereof | |
| US8058931B1 (en) | Enhancing an operational amplifier's capacitive load driving capability using parallel Miller feedback | |
| US7196573B1 (en) | Systems and methods for creating complex poles | |
| CN111342818B (en) | Filter and method of operation thereof | |
| JP2010109710A (en) | Variable gain amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |