CN102281700A - Electrical structure of multilayer printed circuit board and manufacturing method thereof - Google Patents
Electrical structure of multilayer printed circuit board and manufacturing method thereof Download PDFInfo
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- CN102281700A CN102281700A CN2010102028639A CN201010202863A CN102281700A CN 102281700 A CN102281700 A CN 102281700A CN 2010102028639 A CN2010102028639 A CN 2010102028639A CN 201010202863 A CN201010202863 A CN 201010202863A CN 102281700 A CN102281700 A CN 102281700A
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Abstract
The invention provides an electrical structure of a multilayer printed circuit board and a manufacturing method thereof. The electrical structure of the multilayer printed circuit board provided by the invention comprises a circuit base board, a dielectric layer arranged on the circuit base board, a line layer and a grounding layer, wherein the line layer and the grounding layer are mutually in electrical insulation, are respectively arranged on the circuit base board and are respectively in contact with the dielectric layer; the line layer and the grounding layer are arranged on the same reinforcing layer; the thickness of the grounding layer is at least more than 1.5 times of the thickness of the line layer; the grounding layer surrounds the line layer and shields the line layer through metal; and the top surface of the grounding layer is higher than the top surface of the dielectric layer. In the invention, the area and layer number of the electrical structure of the multilayer printed circuit board can be greatly saved; the separation of a crosstalk phenomenon of signals is maintained; the cost of a process can be greatly lowered; an open loop with green patient, the aperture of a blind hole and the thickness of insulating layers such as a soldering-resistant green patient layer/insulating film and the like are controlled to be more uniform; the dimension of a bump for tin soldering in advance is further controlled; and the qualification rate of the process is improved.
Description
Technical field
The present invention relates to a kind of multilayer board electrical structure, relate in particular to a kind of configuration of line layer and ground plane of printed circuit board (PCB).
Background technology
In known printed circuit board arrangement,, must use large-area ground connection copper layer with the metallic shield holding wire in the upper strata or the lower floor of holding wire in order to reduce signal noise interference signal line.Fig. 1 is the profile of known printed circuit board arrangement, the configuration relation of its display signal line and ground connection copper layer.As shown in Figure 1, holding wire 104 must meet the alternately design that increases layer up and down with ground connection copper layer 102.Fig. 2 is the schematic diagram that known printed circuit board arrangement difference increases layer 150a～150c, and it shows that varying level increases the configuration relation in the holding wire district and the ground connection copper floor district of floor.For instance, as shown in Figure 2, the holding wire district 104b that increases floor 150b must vertical folder be located in difference and increases between the ground connection copper floor district 102a and 102c of floor 150a and 150c.Perhaps, increase floor 150b and be necessary for ground connection copper floor district 102b corresponding to the zone of the holding wire district 104a that increases floor 150a; Perhaps, increase floor 150b and be necessary for ground connection copper floor district 102b, to form the structure of (circuit-ground connection-circuit) or (ground connection-circuit-ground connection) three-dimensional three-layer type of this kind corresponding to the zone of the holding wire district 104c that increases floor 150c.In any case the design of this kind structure has the restriction on size and the steric hindrance.The function that faces the future increases, and descends but take into account cost again, and the three-dimensional three layers structure of this kind is not inconsistent benefit.
In addition, when increasing layer plating formation holding wire and ground connection copper layer, ground connection copper face and line areas are because of the difference of area, cause the electric current distribution inequality, the thick high low head of the copper excessive phenomenon that makes a variation can take place, cause follow-uply when insulating barrier is coated with, the excessive anomalies of difference can take place in two kinds of different local thickness/open loop size.
In this technical field, a kind of printed circuit board (PCB) electrical structure of needs is arranged, to improve above-mentioned shortcoming.
Summary of the invention
In view of this, in order to solve prior art problems, one embodiment of the invention provides a kind of multilayer board electrical structure, and above-mentioned multilayer board electrical structure comprises a circuit substrate; One dielectric layer is arranged on the foregoing circuit substrate; A line layer that is electrically insulated each other and a ground plane, be arranged at respectively on the foregoing circuit substrate, and contact with above-mentioned dielectric layer respectively, wherein above-mentioned line layer and above-mentioned ground plane are arranged in the same layer that increases, and the thickness of above-mentioned ground plane is at least more than 1.5 times of above-mentioned line layer thickness, with the above-mentioned line layer of metallic shield, wherein the end face of above-mentioned ground plane is higher than the end face of above-mentioned dielectric layer to above-mentioned ground plane around above-mentioned line layer.
Another embodiment of the present invention provides a kind of manufacture method of multilayer board electrical structure, and comprising provides a circuit substrate; On the foregoing circuit substrate, form a dielectric layer; On the foregoing circuit substrate, form a line layer and a ground plane that is electrically insulated each other respectively, and contact with above-mentioned dielectric layer respectively, wherein above-mentioned line layer and above-mentioned ground plane are arranged in the same layer that increases, and the thickness of above-mentioned ground plane is at least more than 1.5 times of above-mentioned line layer thickness, with the above-mentioned line layer of metallic shield, wherein the end face of above-mentioned ground plane is higher than the end face of above-mentioned dielectric layer to above-mentioned ground plane around above-mentioned line layer.
The present invention can greatly save the area and the number of plies of multilayer board electrical structure, the obstruct of keeping the cross-talk phenomenon of signal also can greatly reduce the cost of technology, controls green lacquer open loop and blind hole aperture and resists further pre-solder bump size and the lifting technology qualification rate controlled of homogeneous such as the thickness of insulating layer that weld green enamelled coating/dielectric film.
Description of drawings
Fig. 1 is the profile of known multilayer board electrical structure, the configuration relation of its display signal line and ground connection copper layer.
Fig. 2 is the schematic diagram that known multilayer board electrical structure varying level increases layer, and it shows that varying level increases the configuration relation in the holding wire district and the ground connection copper floor district of floor.
Fig. 3～Figure 13 is the process section of the multilayer board electrical structure of one embodiment of the invention.
Figure 14～Figure 23 is the process section of the multilayer board electrical structure of another embodiment of the present invention.
Figure 24～Figure 30 is the present invention's process section of the multilayer board electrical structure of another embodiment again.
Wherein, description of reference numerals is as follows:
104～holding wire;
102～ground connection copper layer;
150a～150c～increase layer;
104a～104c～holding wire district;
102a～102c～ground connection copper floor district;
200～circuit substrate;
202～via;
203～grout resin;
204～line layer;
204a, 314a～first bottom ground plane;
214a, 414a, 514a～first ground plane;
214b, 414b, 514b～second ground plane;
214c, 414c, 514c～the 3rd ground plane;
222a～second bottom the ground plane;
204b, 304b, 404b～first line layer;
222b, 322b, 422b～second line layer;
232b, 332b, 432b～tertiary circuit layer;
204c, 222c, 232c, 522c, 532c, 542c～conductive pad;
207～line construction;
206,208,220,224,412,512～patterning photoresist layer;
210,226,236,436,508a, 508c～opening;
212,228,312～metal level;
216,230,306,416,430,516,530～dielectric layer;
250～line construction;
450,550～build-up circuit structure;
201,231,304c, 322c, 332c, 404c, 422c, 432c～conductive blind hole;
234,434,534～insulating barrier;
238,438,538～pre-solder bump;
240,440,540～zone;
308,308a～308c～blind hole;
310～crystal seed layer;
T
1～T
6～thickness;
500a～500c～multilayer board electrical structure.
Embodiment
Below describe and be accompanied by the example of description of drawings in detail with each embodiment, as reference frame of the present invention.In accompanying drawing or specification description, similar or identical part is all used identical mark.And in the accompanying drawings, the shape of embodiment or thickness can enlarge, and to simplify or convenient the sign.In addition, the part of each element will be it should be noted that to describe explanation respectively in the accompanying drawing, not shown or describe element is the form known to those of ordinary skills, in addition, only for disclosing the ad hoc fashion that the present invention uses, it is not in order to limit the present invention to certain embodiments.
Fig. 3～Figure 13 is the process section of the multilayer board electrical structure 500a of one embodiment of the invention.Figure 14～Figure 23 is the process section of the multilayer board electrical structure 500b of another embodiment of the present invention.Figure 24～Figure 30 is the present invention's process section of the multilayer board electrical structure 500c of another embodiment again.The multilayer board electrical structure of the embodiment of the invention is arranged in the same layer that increases with line layer with in order to the ground plane setting of the above-mentioned line layer of metallic shield.The multilayer board electrical structure of the embodiment of the invention can reduce to known three-dimensional three-layer type signal-ground connection-signal structure in promptly having the structural design of signal-ground connection-signal with one deck, still can keep the obstruct of the cross-talk phenomenon of signal on function.
Please refer to Fig. 3, at first, provide a circuit substrate 200.In embodiments of the present invention, circuit substrate 200 can be the circuit board of finishing line construction.One line construction 207 covers the part surface of circuit substrate 200, and runs through circuit substrate 200 by through hole, and forms grout resin 203 in through hole.In an embodiment of the present invention, line construction 207 can comprise the first bottom ground plane 204a, the first line layer 204b and the conductive pad 204c of the part surface that covers circuit substrate 200.As shown in Figure 3, the bottom surface of the first bottom ground plane 204a, the first line layer 204b and conductive pad 204c is in alignment with each other, and the first bottom ground plane 204a and the first line layer 204b are electrically insulated each other.The generation type of the first bottom ground plane 204a, the first line layer 204b and conductive pad 204c can comprise the modes such as physical vapor deposition (PVD) that can utilize coating (coating), chemical vapor deposition (CVD), for example sputter (sputtering), compliance forms a crystal seed layer (seed layer) (figure does not show) on circuit substrate 200, and covers the inwall of through hole.Above-mentioned crystal seed layer (seed layer) is a skim, and its material can comprise nickel, gold, tin, lead, copper, aluminium, silver, chromium, tungsten, silicon or its combination or above-mentioned alloy.Above-mentioned crystal seed layer (seed layer) is convenient to so as to line construction 207 nucleation and the growth thereon that improves and the later use plating mode forms.Afterwards, utilize image transfer again, promptly via the step that covers photoresist, exposure, development (developing), on the surface of circuit substrate 200, form patterning photoresist layer 206, utilize the mode of electroplating again, on the circuit substrate 200 that is not patterned 206 covering of photoresist layer, form the first bottom ground plane 204a, the first line layer 204b and conductive pad 204c simultaneously.In an embodiment of the present invention, the material of the first bottom ground plane 204a, the first line layer 204b and conductive pad 204c can comprise nickel, gold, tin, lead, copper, aluminium, silver, chromium, tungsten, silicon or its combination or above-mentioned alloy.In another embodiment of the present invention, the first bottom ground plane 204a, the first line layer 204b and conductive pad 204c also can chemical deposition or mode such as electroless plating form, then need not be pre-formed crystal seed layer this moment.
Then, please refer to Fig. 4, can utilize the attaching mode, cover a photoresist layer comprehensively.(developing) step of exposing, develop forms patterning photoresist layer 208 on line construction 207.As shown in Figure 4, patterning photoresist layer 208 has a plurality of openings 210 that expose the first bottom ground plane 204a.
Then, please refer to Fig. 5, can utilize the plating (known technology that forms plating of crystal seed layer, demonstration of event figure), modes such as chemical deposition or electroless plating, go up formation metal level 212 in the first bottom ground plane 204a that is not patterned 208 covering of photoresist layer, wherein the material of metal level 212 can be identical with conductive pad 204c with the first bottom ground plane 204a, the first line layer 204b.As shown in Figure 5, the first bottom ground plane 204a and the metal level on it 212 that are positioned at the bottom form the first thicker ground plane 214a of thickness, in an embodiment of the present invention, the thickness of the first ground plane 214a is at least more than 1.5 times of the first line layer 204b thickness, the first ground plane 214a centers on and the above-mentioned first line layer 204b of metallic shield, thereby first ground plane 214a can't be electrically connected to any element, for example can be suspension joint (floating) or ground connection (ground).
Then, please refer to Fig. 6, carry out striping (striping) step, remove patterning photoresist layer 206 and 208.At this moment, the first ground plane 214a, the first line layer 204b and conductive pad 204c form a line construction 250.Then, can go up the dielectric layer 216 of comprehensive formation thickness in the first ground plane 214a, the first line layer 204b and conductive pad 204c, thereby the end face of dielectric layer 216 can be a plane substantially much larger than the first ground plane 214a, the first line layer 204b and conductive pad 204c.As shown in Figure 6, the first ground plane 214a, the first line layer 204b and the available each other dielectric layer 216 of conductive pad 204c are electrically isolated, and dielectric layer 216 can be electrically insulated from each other in order to will be positioned at line layer and the ground plane that difference increases layer.In an embodiment of the present invention, the material of dielectric layer 216 can comprise epoxy resin (epoxyresin), two Maleimide-triazine resin (bismaleimide triacine, BT), pi (polyimide), ABF film (ajinomoto build-up film), polyphenylene oxide (poly phenylene oxide, PPE) or polytetrafluoroethylene (polytetrafluorethylene, PTFE).
Afterwards, please refer to Fig. 7, can utilize laser drill (laser drilling) technology, in dielectric layer 216, form a plurality of blind holes, to reserve the position of follow-up formation conductive blind hole 201.Then, refer again to Fig. 7, can repeat the technology of Fig. 3 again, utilize image transfer, promptly via covering photoresist, the step of exposure and develop (developing), on the surface of dielectric layer 216, form patterning photoresist layer 220, utilize again and electroplate (the known technology that forms plating of crystal seed layer, so figure does not show), mode such as chemical deposition or electroless plating, on the dielectric layer 216 that is not patterned 220 covering of photoresist layer, form the second bottom ground plane 222a simultaneously, the second line layer 222b, conductive blind hole 201 and conductive pad 222c, wherein conductive blind hole 201 passes dielectric layer 216 and is electrically connected to line layer 204.In addition, conductive pad 222c is positioned on the conductive blind hole 201, and is electrically connected to conductive blind hole 201.
Then, please refer to Fig. 8, can repeat the technology of Fig. 4 again, form patterning photoresist layer 224 on patterning photoresist layer 220, it has a plurality of openings 226 that expose the second bottom ground plane 222a.
Then, please refer to Fig. 9, can repeat the technology of Fig. 5 again, go up in the second bottom ground plane 222a that is not patterned 224 covering of photoresist layer and form metal level 228, wherein the material of metal level 228 can be identical with the second line layer 222b, conductive pad 222c and the second bottom ground plane 222a.As shown in Figure 9, the second bottom ground plane 222a and the 228 common second thicker ground plane 214b of thickness that form of the metal level on it.Through after the above-mentioned technology, formation is positioned at another build-up circuit structure that increases layer on line construction 250, and it comprises the second line layer 222b, conductive blind hole 201, conductive pad 222c and the second ground plane 214b.Be similar to the first ground plane 214a, the thickness of the second ground plane 214b is at least more than 1.5 times of the second line layer 222b thickness, the second ground plane 214b centers on and the above-mentioned second line layer 222b of metallic shield, thereby second ground plane 214b can't be electrically connected to any element, for example can be suspension joint (floating) or ground connection (ground).
Afterwards, please refer to Figure 10, carry out striping (striping) step, remove patterning photoresist layer 220 and 224.Then, can repeat the technology of Fig. 6～Fig. 9 again, cover the second line layer 222b to form, the dielectric layer 230 of the conductive pad 222c and the second ground plane 214b, and formation is positioned at the build-up circuit structure that another increases layer on dielectric layer 230, it comprises the 3rd ground plane 214c, tertiary circuit layer 232b, conductive blind hole 231, conductive pad 232c and the 3rd ground plane 214c, wherein the thickness of the 3rd ground plane 214c is at least more than 1.5 times of tertiary circuit layer 232b thickness, and center on and the above-mentioned tertiary circuit layer of metallic shield 232b, thereby the 3rd ground plane 214c can't be electrically connected to any element, for example can be suspension joint (floating) or ground connection (ground).The number of above-mentioned build-up circuit structure is also unrestricted.
Then, please refer to Figure 11, can utilize modes such as coating, attaching or pressing, on the build-up circuit structure, form insulating barrier 234, and can utilize open loop technologies such as laser drill (laser drilling), plasma etching or image transfer, selectivity forms a plurality of openings 236 in insulating barrier 234, and exposes partially conductive pad 232c.In embodiments of the present invention; insulating barrier 234 can comprise for example anti-welding material of green lacquer; or can be and comprise pi (polyimide), ABF film (ajinomoto build-up film) or polypropylene (polypropylene; PP) insulating material, it can protect the conductive pad under it and the build-up circuit structure is not oxidized or short circuit each other.In addition, the opening 236 that passes insulating barrier 234 can provide the formation position of follow-up pre-solder bump.
Then, please refer to Figure 12, can utilize printing, deposition or Patternized technique, in opening 236, form pre-solder bump 238, so that pre-solder bump 238 is electrically connected to conductive pad 232c.As shown in figure 12, the circuit substrate surface of close pre-solder bump 238 is a wafer side face, and another apparent surface is the support plate side surface.In embodiments of the present invention, the material of pre-solder bump 238 can comprise nickel, gold, tin, lead, copper, aluminium, silver, chromium, tungsten, silicon or its combination or above-mentioned alloy.After above-mentioned technology, form the multilayer board electrical structure 500a of the embodiment of the invention.
Figure 13 is the enlarged drawing in the zone 240 of Figure 12, and it shows the position relation of the second line layer 222b and the second ground plane 214b.Because the second line layer 222b and the second ground plane 214b all are formed on the dielectric layer 216, so the bottom surface of the second line layer 222b and the second ground plane 214b is in alignment with each other and is electrically insulated each other, and the thickness T 2 of the second ground plane 214b that forms via twice image transfer is at least more than 1.5 times of the second line layer 222b thickness T 1, the second ground plane 214b around and the above-mentioned second line layer 222b of metallic shield.In addition, the end face of dielectric layer 216 is aligned in the bottom surface of the second line layer 222b and the second ground plane 214b.
The multilayer board electrical structure 500a of the embodiment of the invention has the following advantages: in embodiment of the invention multilayer board electrical structure, appoint not need to press from both sides again between two-layer vertical internal layer adjacent line layer or the build-up circuit layer and establish from level to level indirectly the stratum and come noise insulation, therefore be positioned at line layer directly over or under adjacent increasing on layer position all the All other routes layer can be set.For instance, a certain layer line layer and directly over it or under adjacent line layer can only separate with one dielectric layer, thereby can greatly save the area and the number of plies of multilayer board electrical structure.Original three-dimensional three layers structure can be reduced in the same structural design that promptly has signal-ground connection-signal in the layer that increases, on function, still can keep the obstruct of the cross-talk phenomenon of signal, and can greatly reduce the cost of technology.In embodiment of the invention multilayer board electrical structure, can be at an area that increases mean allocation line areas and ground plane district in the floor, thereby can improve the problem of the plating partition effect inequality of known technology, can effectively the metal layer thickness in line areas and ground plane district be kept lower thickness.Thickness of insulating layer such as green lacquer open loop of the method may command and blind hole aperture and the green enamelled coating/dielectric film of anti-weldering are homogeneous more, further controls pre-solder bump size and promotes the technology qualification rate.
Figure 14～Figure 23 is the process section of the multilayer board electrical structure 500b of another embodiment of the present invention, it forms after the dielectric layer earlier, utilize the laser drill step again, in dielectric layer, form the blind hole of different depth, attach patterning photoresist layer afterwards to strengthen the degree of depth of above-mentioned blind hole, utilize plating mode to form thicker line layer and the ground plane of gross thickness then.Please refer to Figure 14, at first, provide a circuit substrate 200.Then, form via 202, grout resin 203 that fills up through hole that runs through circuit substrate 200 and the line layer 204 that covers the part surface of circuit substrate 200.Then, can utilize the pressing mode, comprehensive formation one dielectric layer 306 on circuit substrate 200, and cover via 202, the grout resin 203 that fills up through hole and line layer 204.
Then, please refer to Figure 15, can utilize laser drill (laser drilling) technology, in dielectric layer 306, once form a plurality of blind holes 308 of different depth, it comprises in order to the blind hole 308a that reserves follow-up formation ground plane position, in order to the blind hole 308b that reserves follow-up formation line layer position with in order to reserve the blind hole 308c of follow-up formation conductive blind hole position.As shown in figure 15, must be in order to the degree of depth of the blind hole 308a that reserves follow-up formation ground plane position greater than the degree of depth of blind hole 308b and 308c.
Then, please refer to Figure 16, can utilize the modes such as physical vapor deposition (PVD) of coating (coating), chemical vapor deposition (CVD), for example sputter (sputtering), compliance forms a crystal seed layer (seed layer) 310 on dielectric layer 306, and covers the inwall of blind hole 308.In an embodiment of the present invention, crystal seed layer (seed layer) 310 is a skim, and its material can comprise nickel, gold, tin, lead, copper, aluminium, silver, chromium, tungsten, silicon or its combination or above-mentioned alloy.Above-mentioned crystal seed layer (seed layer) 310 is convenient to so as to line layer, ground plane or conductive pad nucleation and the growth thereon that improves and the later use plating mode forms.
Please refer to Figure 17, afterwards, can utilize the attaching mode, cover a photoresist layer comprehensively.(developing) step of exposing, develop is to form patterning photoresist layer 412 on dielectric layer 306 and crystal seed layer (seed layer) 310.As shown in figure 17, patterning photoresist layer 412 has a plurality of openings (the visual contraposition situation of the top opening correction openings of sizes of blind hole 308c also can equally be left the opening big than blind hole 308c with Figure 26) that expose and be communicated to blind hole 308a～308c.
Afterwards, please refer to Figure 18, can utilize plating mode, in the above-mentioned opening of patterning photoresist layer 412, form a metal material, in blind hole 308a, to form the first ground plane 414a simultaneously, in blind hole 308b, form the first line layer 404b, and in blind hole 308c, form conductive blind hole 404c.As shown in figure 18, the end face of the first ground plane 414a, the first line layer 404b and conductive blind hole 404c is aligned in the end face of patterning photoresist layer 412 substantially, patterning photoresist layer 412 is in order to increasing the gross thickness of the follow-up formation first ground plane 414a and the first line layer 404b, and can arrange in pairs or groups its down dielectric layer form conductive blind hole 404c.
Then, please refer to Figure 19, can carry out striping (striping) step, remove patterning photoresist layer 412.Afterwards, can carry out etching step, remove the crystal seed layer (seedlayer) 310 on dielectric layer 306 end faces, to avoid the first ground plane 414a, the first line layer 404b and conductive blind hole 404c to be electrically connected to each other and to cause short circuit.At this moment, dielectric layer 306, the first ground plane 414a, the first line layer 404b and conductive blind hole 404c form a build-up circuit structure 450, wherein the thickness of the first ground plane 414a is at least more than 1.5 times of the first line layer 404b thickness, and center on and the above-mentioned first line layer 404b of metallic shield, thereby first ground plane 414a can't be electrically connected to any element, for example can be suspension joint (floating) or ground connection (ground).In another embodiment of the present invention, the build-up circuit structure also can chemical deposition or mode such as electroless plating form, then need not be pre-formed crystal seed layer this moment.
Afterwards, please refer to Figure 20, can repeat the technology of Figure 14～Figure 19 again, on build-up circuit structure 450, to form the build-up circuit structure of several layers of vertical stacking, the second ground plane 414b, the second line layer 422b and the conductive blind hole 422c that in dielectric layer 416, forms for example, and be formed at the 3rd ground plane 414c, tertiary circuit layer 432b and conductive blind hole 432c in the dielectric layer 430.
Then, please refer to Figure 21, can repeat the technology of Figure 11 again, modes such as available coating, attaching or pressing form insulating barrier 434 on the build-up circuit structure, and selectivity form a plurality of openings 436 in insulating barrier 434, and expose partially conductive blind hole 432c.In embodiments of the present invention, insulating barrier 434 can comprise identical material with insulating barrier 234 shown in Figure 11.
Then, please refer to Figure 22, can repeat the technology of Figure 12 again, can utilize printing, deposition or Patternized technique, in opening 436, form pre-solder bump 438, so that pre-solder bump 438 is electrically connected to conductive blind hole 432c.In embodiments of the present invention, pre-solder bump 438 can comprise identical material with pre-solder bump 238 shown in Figure 12.Through after the above-mentioned technology, form the multilayer board electrical structure 500b of the embodiment of the invention.
Figure 23 is the enlarged drawing in the zone 440 of Figure 22, and it shows the position relation of the first line layer 404b, the first ground plane 414a and dielectric layer 306.Owing to carry out laser drill again and attach patterning photoresist layer after forming dielectric layer 306 earlier, utilize plating mode to form the thicker first line layer 404b and the first ground plane 414a of gross thickness then, so the end face of the first line layer 404b and the first ground plane 414a is in alignment with each other and is electrically insulated each other, and the thickness T of the first ground plane 414a
4Be at least the first line layer 404b thickness T
3More than 1.5 times, the first ground plane 414a around and the above-mentioned first line layer 404b of metallic shield, thereby the first ground plane 414a can't be electrically connected to any element, for example can be suspension joint (floating) or ground connection (ground).In addition, the end face of dielectric layer 306 is between the end face and bottom surface of the first line layer 404b and the first ground plane 414a.
The multilayer board electrical structure 500b of the embodiment of the invention is except that the advantage with multilayer board electrical structure 500a, it utilizes the laser drill step image transfer of arranging in pairs or groups one, with the blind hole that in dielectric layer, forms different depth and the degree of depth that strengthens above-mentioned blind hole, thereby can utilize modes such as plating, chemical deposition or electroless plating to form thicker line layer of gross thickness and ground plane.
Figure 24～Figure 30 is the present invention's process section of the multilayer board electrical structure 500c of another embodiment again, it forms after the dielectric layer earlier, utilize the laser drill step again, in dielectric layer, form the blind hole of different depth, form the patterning photoresist layer that exposes ground plane afterwards, utilize plating mode to form then and have the ground plane that strengthens thickness.Each element in the above-mentioned accompanying drawing if any with Figure 14～same or analogous part shown in Figure 16, then can not do repeat specification at this with reference to the relevant narration of front.
Please refer to Figure 24, can utilize plating mode, comprehensive formation one metal level 312, and insert blind hole 308.As shown in figure 24, the thickness of metal level 312 is greater than the degree of depth of blind hole 308, so that the end face of metal level 312 is kept a plane substantially.In an embodiment of the present invention, the material of metal level 312 can comprise nickel, gold, tin, lead, copper, aluminium, silver, chromium, tungsten, silicon or its combination or above-mentioned alloy.
Then, please refer to Figure 25, can utilize and grind or etching mode, remove the metal level 312 on outer crystal seed layer 310 end faces of blind hole, in blind hole 308a, to form the first bottom ground plane 314a simultaneously, in blind hole 308b, form the first line layer 304b, and in blind hole 308c, form conductive blind hole 304c.
Afterwards, please refer to Figure 26, after forming the first bottom ground plane 314a, the first line layer 304b and conductive blind hole 304c, can utilize the attaching mode, cover a photoresist layer comprehensively.(developing) step of exposing, develop forms patterning photoresist layer 512 on dielectric layer 306.As shown in figure 26, patterning photoresist layer 512 has a plurality of opening 508a of exposing and being communicated to the first bottom ground plane 314a and exposure and is communicated to a plurality of opening 508c of conductive blind hole 304c (the visual contraposition situation of the opening 508c correction openings of sizes of blind hole 304c top also can equally be left opening with the identical size of blind hole 304c with Figure 17).
Afterwards, please refer to Figure 27, can utilize plating mode, in opening 508a and 508c, form metal level, and cover first bottom ground plane 314a and the conductive blind hole 304c respectively.Through after the above-mentioned technology, in opening 508a, utilize above-mentioned metal level to increase by the gross thickness of the first bottom ground plane 314a to form the first ground plane 514a, and in opening 508c, utilizing above-mentioned metal level to form conductive pad 522c simultaneously, it is electrically connected to the conductive blind hole 304c under it.Then, can carry out striping (striping) step, remove patterning photoresist layer 512.Afterwards, can carry out etching step, remove the crystal seed layer (seed layer) 310 on outer dielectric layer 306 end faces of blind hole, to avoid the first ground plane 514a, the first line layer 304b and conductive pad 522c/ conductive blind hole 304c to be electrically connected to each other and to cause short circuit.At this moment, dielectric layer 306, the first ground plane 514a, the first line layer 304b, conductive blind hole 304c and conductive pad 522c form a build-up circuit structure 550, wherein the thickness of the first ground plane 514a is at least more than 1.5 times of the first line layer 304b thickness, and center on and the above-mentioned first line layer 304b of metallic shield, thereby first ground plane 514a can't be electrically connected to any element, for example can be suspension joint (floating) or ground connection (ground).
Afterwards, please refer to Figure 28, can repeat the technology of Figure 14～Figure 16, Figure 24～Figure 27 again, on build-up circuit structure 550, to form the build-up circuit structure of several layers of vertical stacking, the second ground plane 514b, the second line layer 322b, conductive blind hole 322c and the conductive pad 532c that in dielectric layer 516, forms for example, and be formed at the 3rd ground plane 514c, tertiary circuit layer 332b, conductive blind hole 332c and conductive pad 542c in the dielectric layer 530.
Then, please refer to Figure 29, can repeat the technology of Figure 11 again, utilize modes such as coating, attaching or pressing, on the build-up circuit structure, form insulating barrier 534, and selectivity forms a plurality of openings that expose partially conductive pad 542c in insulating barrier 534.In embodiments of the present invention, insulating barrier 434 can comprise identical material with insulating barrier 234 shown in Figure 11.Then, can repeat the technology of Figure 12 again, can utilize printing, deposition or Patternized technique, in opening, form pre-solder bump 538, so that pre-solder bump 538 is electrically connected to conductive pad 542c.In embodiments of the present invention, pre-solder bump 538 can comprise identical material with pre-solder bump 238 shown in Figure 12.Through after the above-mentioned technology, form the multilayer board electrical structure 500c of the embodiment of the invention.
Figure 30 is the enlarged drawing in the zone 540 of Figure 29, the position relation of the first line layer 304b, the first ground plane 514a of the multilayer board electrical structure 500c of its demonstration embodiment of the invention and dielectric layer 306.Owing to form after the dielectric layer 306 earlier, utilize the laser drill step again, in dielectric layer 306, form the blind hole of different depth, attach the patterning photoresist layer 512 that exposes the first bottom ground plane 314a afterwards, utilize plating mode to form the first ground plane 514a that strengthens thickness then.So, be positioned at the same end face of the first ground plane 514a that increases layer and be higher than the end face of the first line layer 304b and be electrically insulated each other, and the thickness T of the first ground plane 514a
6Be at least the first line layer 304b thickness T
5More than 1.5 times, the first ground plane 514a around and the above-mentioned build-up circuit layer of metallic shield 304b, thereby the first ground plane 514a can't be electrically connected to any element, for example can be suspension joint (floating) or ground connection (ground).In addition, the end face of dielectric layer 306 is aligned in the first line layer 304b, and between the end face and bottom surface of the first ground plane 514a.
The multilayer board electrical structure 500c of the embodiment of the invention is except that the advantage with multilayer board electrical structure 500a, it utilizes the laser drill step, in dielectric layer, form the blind hole of different depth, attach the patterning photoresist layer that exposes ground plane and conductive blind hole afterwards, utilize plating mode to form the ground plane that strengthens thickness then, and form conductive pad simultaneously, when the build-up circuit layer was the holding wire of fan-out (fan-out) wiring, ground plane also can provide better metallic shield effect to the build-up circuit layer.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; any those of ordinary skills; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the scope that claim defined.
Claims (12)
1. multilayer board electrical structure comprises:
One circuit substrate;
One dielectric layer is arranged on this circuit substrate; And
A line layer that is electrically insulated each other and a ground plane, be arranged at respectively on this circuit substrate, and contact with this dielectric layer respectively, wherein this line layer and this ground plane are arranged in the same layer that increases, and the thickness of this ground plane is at least more than 1.5 times of this line layer thickness, with this line layer of metallic shield, wherein the end face of this ground plane is higher than the end face of this dielectric layer to this ground plane around this line layer.
2. multilayer board electrical structure as claimed in claim 1 also comprises a pre-solder bump, is electrically connected to this line layer, and is not electrically connected to this ground plane.
3. multilayer board electrical structure as claimed in claim 1, wherein the end face of this dielectric layer is aligned in the bottom surface of this line layer and this ground plane.
4. multilayer board electrical structure as claimed in claim 1, wherein this line layer or this ground plane also pass this dielectric layer of part respectively.
5. multilayer board electrical structure as claimed in claim 4, wherein the bottom surface of this ground plane is lower than the bottom surface of this line layer, and the end face of this ground plane is higher than the end face of this line layer.
6. multilayer board electrical structure as claimed in claim 4, wherein the bottom surface of this ground plane is lower than the bottom surface of this line layer, and the end face of this ground plane is aligned in the end face of this line layer.
7. multilayer board electrical structure as claimed in claim 4, wherein the end face of this dielectric layer is between the end face and bottom surface of this line layer and this ground plane.
8. multilayer board electrical structure as claimed in claim 4, wherein the end face of this dielectric layer is aligned in the end face of this line layer.
9. the manufacture method of a multilayer board electrical structure comprises the following steps:
One circuit substrate is provided;
On this circuit substrate, form a dielectric layer; And
On this circuit substrate, form a line layer and a ground plane that is electrically insulated each other respectively, and contact with this dielectric layer respectively, wherein this line layer and this ground plane are arranged in the same layer that increases, and the thickness of this ground plane is at least more than 1.5 times of this line layer thickness, with this line layer of metallic shield, wherein the end face of this ground plane is higher than the end face of this dielectric layer to this ground plane around this line layer.
10. the manufacture method of multilayer board electrical structure as claimed in claim 9 forms this line layer be electrically insulated each other and the step of this ground plane respectively and also comprises on this circuit substrate:
On this dielectric layer, form one first patterning photoresist layer;
On this circuit substrate that is not covered, form this line layer and a bottom ground plane simultaneously by this first patterning photoresist layer;
Cover one second patterning photoresist layer, it has an opening that exposes this bottom ground plane;
On this bottom ground plane that is not covered, form a metal level, so that this bottom ground plane and this metal level on it form this ground plane by this second patterning photoresist layer; And
Remove this first and second patternings photoresist layer.
11. the manufacture method of multilayer board electrical structure as claimed in claim 9 forms this line layer be electrically insulated each other and the step of this ground plane respectively and also comprises on this circuit substrate:
Form one first blind hole and one second blind hole in this dielectric layer, wherein the degree of depth of this first blind hole is greater than the degree of depth of this second blind hole;
Compliance forms a crystal seed layer on this dielectric layer, and covers the inwall of this first blind hole and this second blind hole;
Form a patterning photoresist layer on this crystal seed layer, it has a plurality of openings that expose and be communicated to this first blind hole and this second blind hole;
In described a plurality of openings of this patterning photoresist layer, form a metal material, in first blind hole, to form this ground plane, and form this line layer in this second blind hole, wherein the end face of this ground plane and this line layer is aligned in an end face of this patterning photoresist layer substantially; And
Remove this unnecessary crystal seed layer on the end face of patterning photoresist layer and this dielectric layer.
12. the manufacture method of multilayer board electrical structure as claimed in claim 9 forms this line layer be electrically insulated each other and the step of this ground plane respectively and also comprises on this circuit substrate:
Form one first blind hole and one second blind hole in this dielectric layer, wherein the degree of depth of this first blind hole is greater than the degree of depth of this second blind hole;
Compliance forms a crystal seed layer on this dielectric layer, and covers the inwall of this first blind hole and this second blind hole;
Comprehensive formation one the first metal layer, and insert this first blind hole and this second blind hole, wherein this metal layer thickness is greater than the degree of depth of this first blind hole and this second blind hole;
Remove this first metal layer on this outer crystal seed layer end face of this first blind hole and this second blind hole;
Form a patterning photoresist layer on this dielectric layer, it has an opening that exposes and be communicated to this first blind hole;
In this opening, form one second metal level, and cover this first metal layer in this first blind hole, so that this first metal layer in this first blind hole and second metal level on it form this ground plane; And
Remove this crystal seed layer on the end face of this outer dielectric layer of this patterning photoresist layer and this first blind hole and this second blind hole, in this second blind hole, to form this line layer.
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| CN 201010202863 CN102281700B (en) | 2010-06-10 | 2010-06-10 | Electrical structure of multilayer printed circuit board and manufacturing method thereof |
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| CN 201010202863 CN102281700B (en) | 2010-06-10 | 2010-06-10 | Electrical structure of multilayer printed circuit board and manufacturing method thereof |
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| WO2014015832A1 (en) * | 2012-07-26 | 2014-01-30 | Huawei Technologies Co., Ltd. | Device and Method for Printed Circuit Board with Embedded Cable |
| CN104968138A (en) * | 2015-06-02 | 2015-10-07 | 广东欧珀移动通信有限公司 | Printed circuit board |
| CN106304663A (en) * | 2015-06-26 | 2017-01-04 | 健鼎（无锡）电子有限公司 | Patterned lines line structure and preparation method thereof |
| CN107305848A (en) * | 2016-04-20 | 2017-10-31 | 碁鼎科技秦皇岛有限公司 | Package substrate, encapsulating structure and preparation method thereof |
| CN107404802A (en) * | 2017-08-21 | 2017-11-28 | 广东欧珀移动通信有限公司 | Printed circuit board, the preparation method of printed circuit board and electronic equipment |
| CN108430170A (en) * | 2018-01-29 | 2018-08-21 | 昆山群安电子贸易有限公司 | A kind of production method of circuit board substrate |
| CN111050466A (en) * | 2019-12-31 | 2020-04-21 | 安捷利（番禺）电子实业有限公司 | PCB with low insertion loss and high peeling strength and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2014015832A1 (en) * | 2012-07-26 | 2014-01-30 | Huawei Technologies Co., Ltd. | Device and Method for Printed Circuit Board with Embedded Cable |
| CN104968138A (en) * | 2015-06-02 | 2015-10-07 | 广东欧珀移动通信有限公司 | Printed circuit board |
| CN106304663B (en) * | 2015-06-26 | 2019-03-15 | 健鼎（无锡）电子有限公司 | Patterned lines line structure and preparation method thereof |
| CN106304663A (en) * | 2015-06-26 | 2017-01-04 | 健鼎（无锡）电子有限公司 | Patterned lines line structure and preparation method thereof |
| CN107305848A (en) * | 2016-04-20 | 2017-10-31 | 碁鼎科技秦皇岛有限公司 | Package substrate, encapsulating structure and preparation method thereof |
| CN107305848B (en) * | 2016-04-20 | 2019-08-20 | 碁鼎科技秦皇岛有限公司 | Package substrate, encapsulating structure and preparation method thereof |
| CN107404802A (en) * | 2017-08-21 | 2017-11-28 | 广东欧珀移动通信有限公司 | Printed circuit board, the preparation method of printed circuit board and electronic equipment |
| CN108430170A (en) * | 2018-01-29 | 2018-08-21 | 昆山群安电子贸易有限公司 | A kind of production method of circuit board substrate |
| CN111050466A (en) * | 2019-12-31 | 2020-04-21 | 安捷利（番禺）电子实业有限公司 | PCB with low insertion loss and high peeling strength and manufacturing method thereof |
| CN111211111A (en) * | 2020-01-08 | 2020-05-29 | 上海燧原智能科技有限公司 | Interconnector and packaging structure |
| CN111211111B (en) * | 2020-01-08 | 2020-11-20 | 上海燧原智能科技有限公司 | Interconnector and packaging structure |
| CN113709963A (en) * | 2021-07-23 | 2021-11-26 | 苏州浪潮智能科技有限公司 | PCB and manufacturing method and equipment thereof |
| CN114040565A (en) * | 2021-11-15 | 2022-02-11 | 广东世运电路科技股份有限公司 | PCB processing method, PCB processing equipment and computer readable storage medium |
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