TWI403223B - Multi layer printed circuit board electronic structure and method for fabricating the same - Google Patents

Description

Multilayer printed circuit board electrical structure and manufacturing method thereof

The present invention relates to an electrical structure of a multilayer printed circuit board, and more particularly to a configuration of a circuit layer and a ground plane of a printed circuit board.

In the conventional printed circuit board structure, in order to reduce the signal noise interference signal line, it is necessary to use a large-area grounding copper layer to shield the signal line with metal in the upper or lower layer of the signal line. Figure 1 is a cross-sectional view showing the structure of a conventional printed circuit board showing the arrangement relationship between the signal line and the ground copper layer. As shown in FIG. 1, the signal line 104 and the grounded copper layer 102 must conform to the alternate design of the upper and lower layers. Fig. 2 is a schematic view showing the different build-up layers 150a-150c of the conventional printed circuit board structure, showing the arrangement relationship of the signal line regions and the grounded copper layer regions of different horizontally layered layers. For example, as shown in FIG. 2, the signal line region 104b of the build-up layer 150b must be vertically sandwiched between the ground copper layer regions 102a and 102c located in the different build-up layers 150a and 150c. Alternatively, the region of the enhancement layer 150b corresponding to the signal line region 104a of the enhancement layer 150a must be the ground copper layer region 102b; or the region of the enhancement layer 150b corresponding to the signal line region 104c of the enhancement layer 150c must be the ground copper layer region 102b, To form (line-ground-line) or (ground-line-ground) such a three-dimensional three-layer structure. No matter how the structure is designed, there are restrictions on size and steric obstacles. In the face of the increase in future functions, but also to take into account the cost reduction, this three-dimensional three-tier structure is not effective.

In addition, when the signal line and the grounding copper layer are formed by the layer plating, the difference in the area between the grounded copper surface and the line region results in uneven current density distribution, which may cause excessive variation of the copper thickness difference, resulting in subsequent coating on the insulating layer. At the same time, the thickness/open loop size in two different places may be abnormally different.

There is a need in the art for a printed circuit board electrical structure to address the above disadvantages.

In view of the above, an embodiment of the present invention provides a multilayer printed circuit board electrical structure, the multilayer printed circuit board electrical structure includes a circuit substrate; a dielectric layer disposed on the circuit substrate; electrically insulated from each other a circuit layer and a ground layer respectively disposed on the circuit substrate and respectively in contact with the dielectric layer, wherein the circuit layer and the ground layer are located in the same build-up layer, and the ground layer has a thickness of at least the circuit layer More than 1.5 times the thickness, the ground layer surrounds the circuit layer with metal around the circuit layer, wherein a top surface of the ground layer is higher than a top surface of the dielectric layer.

Another embodiment of the present invention provides a method for fabricating an electrical structure of a multilayer printed circuit board, comprising: providing a circuit substrate; forming a dielectric layer on the circuit substrate; and forming one electrically insulated from each other on the circuit substrate a circuit layer and a ground layer respectively in contact with the dielectric layer, wherein the circuit layer and the ground layer are located in the same build-up layer, and the ground layer has a thickness of at least 1.5 times the thickness of the circuit layer, and the ground layer The circuit layer is shielded by metal around the circuit layer, wherein a top surface of the ground layer is higher than a top surface of the dielectric layer.

The following is a detailed description of the embodiments and examples accompanying the drawings, which are the basis of the present invention. In the drawings or the description of the specification, the same drawing numbers are used for similar or identical parts. In the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. In addition, the components of the drawings will be described separately, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art, and in particular, The examples are merely illustrative of specific ways of using the invention and are not intended to limit the invention.

3 to 13 are cross-sectional views showing the process of the multilayer printed circuit board electrical structure 500a according to an embodiment of the present invention. 14 to 23 are cross-sectional views showing the process of the multilayer printed circuit board electrical structure 500b according to another embodiment of the present invention. 24 to 30 are cross-sectional views showing the process of the multilayer printed circuit board electrical structure 500c according to still another embodiment of the present invention. The multilayer printed circuit board electrical structure of the embodiment of the present invention places the circuit layer and the ground layer for shielding the circuit layer from the metal in the same build-up layer. The electrical structure of the multilayer printed circuit board of the embodiment of the invention can reduce the conventional three-layer three-layer signal-grounding-signal structure to the same layer, that is, the signal-grounding-signal structure design, and can still maintain the signal in function. The barrier of the crosstalk phenomenon.

Referring to FIG. 3, first, a circuit substrate 200 is provided. In the embodiment of the present invention, the circuit substrate 200 may be a circuit board that has completed the circuit structure. A wiring structure 207 covers a part of the surface of the circuit substrate 200, and penetrates the circuit substrate 200 through the through holes, and forms the filling resin 203 in the through holes. In an embodiment of the invention, the wiring structure 207 may include a first lower ground layer 204a, a first wiring layer 204b, and a conductive pad 204c that cover a portion of the surface of the circuit substrate 200. As shown in FIG. 3, the bottom surfaces of the first lower ground layer 204a, the first wiring layer 204b, and the conductive pads 204c are aligned with each other, and the first lower ground layer 204a and the first wiring layer 204b are electrically insulated from each other. The formation of the first lower ground layer 204a, the first wiring layer 204b, and the conductive pad 204c may include physical vapor deposition (coating), chemical vapor deposition (CVD), such as sputtering. In a manner such as PVD), a seed layer (not shown) is formed on the circuit substrate 200 in compliance with the inner wall of the through hole. The seed layer is a thin layer and may be made of nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, rhenium or a combination thereof or an alloy thereof. The above seed layer is convenient for improving the nucleation and growth of the line structure 207 formed by subsequent electroplating. Thereafter, the image transfer process is further utilized, that is, a patterned photoresist layer 206 is formed on the surface of the circuit substrate 200 via a step of covering photoresist, exposure, and development, and then patterned by using the plating method. A first lower ground layer 204a, a first wiring layer 204b, and a conductive pad 204c are simultaneously formed on the circuit substrate 200 covered by the resist layer 206. In an embodiment of the present invention, the material of the first lower ground layer 204a, the first circuit layer 204b, and the conductive pad 204c may include nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, tantalum or Combination or alloy as described above. In another embodiment of the present invention, the first lower ground layer 204a, the first wiring layer 204b, and the conductive pad 204c may also be formed by chemical deposition or electroless plating. In this case, it is not necessary to form a seed layer in advance.

Next, please refer to Figure 4, which can be used to cover a photoresist layer in a comprehensive manner. The exposure and development steps are further performed to form a patterned photoresist layer 208 on the line structure 207. As shown in FIG. 4, the patterned photoresist layer 208 has a plurality of openings 210 exposing the first lower ground layer 204a.

Then, please refer to FIG. 5, which can be covered by the patterned photoresist layer 208 by means of electroplating (the seed layer is formed by electroplating, so the figure is not shown), chemical deposition or electroless plating. A metal layer 212 is formed on the first lower ground layer 204a, wherein the metal layer 212 is made of the same material as the first lower ground layer 204a, the first wiring layer 204b, and the conductive pad 204c. As shown in FIG. 5, the lower first ground layer 204a and the metal layer 212 thereon form a thicker first ground layer 214a. In an embodiment of the invention, the first ground layer 214a The first ground layer 214a surrounds and metal shields the first circuit layer 204b, and the first ground layer 214a is not electrically connected to any component, for example, Floating or ground.

Next, referring to FIG. 6, a stripping step is performed to remove the patterned photoresist layers 206 and 208. At this time, the first ground layer 214a, the first wiring layer 204b, and the conductive pad 204c form a wiring structure 250. Then, a dielectric layer 216 having a thickness much larger than that of the first ground layer 214a, the first wiring layer 204b, and the conductive pad 204c can be formed on the first ground layer 214a, the first wiring layer 204b, and the conductive pad 204c. The top surface of the electrical layer 216 can be substantially a flat surface. As shown in FIG. 6, the first ground layer 214a, the first circuit layer 204b, and the conductive pads 204c may be electrically isolated from each other by a dielectric layer 216, and the dielectric layer 216 may be used to connect the circuit layers of different build-up layers and The ground planes are electrically isolated from one another. In an embodiment of the invention, the material of the dielectric layer 216 may include epoxy resin, bismaleimide triacine (BT), polyimide (polyimide). , ABFomoto build-up film, polyphenylene oxide (PPE) or polytetrafluorethylene (PTFE).

Thereafter, referring to FIG. 7, a plurality of blind holes may be formed in the dielectric layer 216 by a laser drilling process to reserve a position where the conductive blind holes 201 are subsequently formed. Next, referring to FIG. 7, the process of FIG. 3 can be repeated, and the image transfer process is performed, that is, the pattern is formed on the surface of the dielectric layer 216 by the steps of covering photoresist, exposure, and developing. The photoresist layer 220 is further coated with a dielectric layer not covered by the patterned photoresist layer 220 by means of electroplating (the seed layer is formed by electroplating, so the figure is not shown), chemical deposition or electroless plating. A second lower ground layer 222a, a second wiring layer 222b, a conductive via 201 and a conductive pad 222c are formed on the 216, wherein the conductive via 201 is electrically connected to the circuit layer 204 through the dielectric layer 216. In addition, the conductive pad 222c is located on the conductive blind hole 201 and electrically connected to the conductive blind hole 201.

Then, referring to FIG. 8, the process of FIG. 4 can be repeated to form a patterned photoresist layer 224 on the patterned photoresist layer 220 having a plurality of openings 226 exposing the second lower ground layer 222a.

Next, referring to FIG. 9, the process of FIG. 5 can be repeated to form a metal layer 228 on the second lower ground layer 222a not covered by the patterned photoresist layer 224, wherein the material of the metal layer 228 can be The two wiring layers 222b, the conductive pads 222c, and the second lower ground layer 222a are the same. As shown in FIG. 9, the second lower ground layer 222a and the metal layer 228 thereon are collectively formed to form a second ground layer 214b having a relatively thick thickness. After the above process, a build-up line structure in another build-up layer is formed on the line structure 250, which includes a second line layer 222b, a conductive blind via 201, a conductive pad 222c, and a second ground layer 214b. Similar to the first ground layer 214a, the thickness of the second ground layer 214b is at least 1.5 times the thickness of the second circuit layer 222b, and the second ground layer 214b surrounds and metal shields the second circuit layer 222b, and thus the second ground layer 214b is not electrically connected to any component, such as floating or ground.

Thereafter, referring to FIG. 10, a stripping step is performed to remove the patterned photoresist layers 220 and 224. Then, the process of FIGS. 6-9 can be repeated to form a dielectric layer 230 covering the second circuit layer 222b, the conductive pad 222c and the second ground layer 214b, and formed on the dielectric layer 230 at another increase. The layered wiring structure includes a third ground layer 214c, a third circuit layer 232b, a conductive blind via 231, a conductive pad 232c, and a third ground layer 214c, wherein the third ground layer 214c has a thickness of at least a third circuit layer The thickness of 232b is more than 1.5 times, and the third circuit layer 232b is shielded around the metal, so that the third ground layer 214c is not electrically connected to any component, for example, may be floating or ground. The number of the above-mentioned build-up line structures is not limited.

Then, referring to Fig. 11, the insulating layer 234 can be formed on the build-up line structure by coating, attaching or pressing, and laser drilling, plasma etching or image transfer can be utilized. During the open-loop process, a plurality of openings 236 are selectively formed in the insulating layer 234, and a portion of the conductive pads 232c are exposed. In the embodiment of the present invention, the insulating layer 234 may include a solder resist material such as green lacquer, or may include polyimide, ABF film (ajinomoto build-up film) or polypropylene (PP). An insulating material that protects the underlying conductive pads and build-up wiring structures from oxidation or short-circuiting with each other. Additionally, opening 236 through insulating layer 234 can provide a location for subsequent pre-solder bumps.

Next, referring to FIG. 12, a pre-solder bump 238 may be formed in the opening 236 by a printing, deposition or patterning process to electrically connect the pre-solder bump 238 to the conductive pad 232c. As shown in Fig. 12, the surface of the circuit substrate adjacent to the pre-solder bump 238 is the wafer side surface, and the other opposite surface is the carrier side surface. In the embodiment of the present invention, the material of the pre-solder bump 238 may include nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, tantalum or a combination thereof or the above alloy. After the above process, the multilayer printed circuit board electrical structure 500a of the embodiment of the present invention is formed.

Fig. 13 is an enlarged view of a region 240 of Fig. 12 showing the positional relationship of the second wiring layer 222b and the second ground layer 214b. Since the second circuit layer 222b and the second ground layer 214b are both formed on the dielectric layer 216, the bottom surfaces of the second circuit layer 222b and the second ground layer 214b are aligned with each other and electrically insulated from each other, and are processed through two image transfer processes. The thickness T _{2 of the} formed second ground layer 214b is at least 1.5 times the thickness T ₁ of the second wiring layer 222b, and the second ground layer 214b surrounds and metal shields the second wiring layer 222b. In addition, the top surface of the dielectric layer 216 is aligned with the bottom surfaces of the second wiring layer 222b and the second ground layer 214b.

The multilayer printed circuit board electrical structure 500a of the embodiment of the present invention has the following advantages: in the electrical structure of the multilayer printed circuit board of the embodiment of the present invention, between any two vertically adjacent inner wiring layers or layered wiring layers A layer of indirect ground layer is required to isolate the noise, so that other circuit layers can be disposed at adjacent build-up positions directly above or below the circuit layer. For example, a certain circuit layer may be separated by a dielectric layer directly adjacent to or directly below the wiring layer, thereby greatly reducing the area and number of layers of the multilayer printed circuit board electrical structure. The original three-layer three-layer structure can be reduced to the same layer, that is, the signal-grounding-signal structure design can maintain the crosstalk of the signal in function, and can greatly reduce the cost of the process. In the electrical structure of the multilayer printed circuit board according to the embodiment of the present invention, the area of the line region and the ground layer region can be equally distributed in a build-up layer, thereby improving the problem of uneven plating effect of the prior art, and effectively The thickness of the metal layer in the line region and the ground layer region is maintained at a low thickness. The method can control the green paint open loop and blind hole aperture and the thickness of the insulating layer such as the anti-weld green paint layer/insulation film to further control the size of the pre-solder bump and improve the process yield.

14 to 23 are process cross-sectional views showing a multilayer printed circuit board electrical structure 500b according to another embodiment of the present invention, which is formed by first forming a dielectric layer and then using a laser drilling step to form a different layer in the dielectric layer. A deep blind hole is then attached with a patterned photoresist layer to increase the depth of the blind via, and then a plating layer and a ground layer having a relatively thick total thickness are formed by electroplating. Referring to FIG. 14, first, a circuit substrate 200 is provided. Next, a via hole 202 penetrating the circuit substrate 200, a via resin 203 filling the via hole, and a wiring layer 204 covering a part of the surface of the circuit substrate 200 are formed. Then, a dielectric layer 306 is formed on the circuit substrate 200 by a pressing method, and the via hole 202, the via resin 203 filling the via hole, and the wiring layer 204 are covered.

Next, referring to FIG. 15, a plurality of blind holes 308 of different depths may be formed in the dielectric layer 306 at one time by using a laser drilling process, which includes a blind to reserve the position of the ground layer. The hole 308a is configured to reserve a blind hole 308b for subsequently forming a position of the circuit layer, and a blind hole 308c for reserving a position for forming a conductive blind hole. As shown in Fig. 15, the depth of the blind hole 308a for reserving the position at which the ground layer is subsequently formed must be greater than the depth of the blind holes 308b and 308c.

Then, referring to FIG. 16, the compliance may be formed on the dielectric layer 306 by means of coating, chemical vapor deposition (CVD), physical vapor deposition (PVD) such as sputtering, and the like. A seed layer 310 covers the inner wall of the blind via 308. In an embodiment of the invention, the seed layer 310 is a thin layer, and the material thereof may include nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, rhenium or a combination thereof or the above. alloy. The above seed layer 310 is convenient for improving the nucleation and growth of the circuit layer, the ground layer or the conductive pad formed by the subsequent plating method.

Please refer to Figure 17, after which you can use a splicing method to completely cover a photoresist layer. An exposure and development step is then performed to form a patterned photoresist layer 412 on the dielectric layer 306 and the seed layer 310. As shown in FIG. 17, the patterned photoresist layer 412 has a plurality of openings that are exposed and communicated to the blind vias 308a-308c (the upper opening of the blind via 308c can be visually aligned to correct the opening size, and can also be opened as shown in FIG. Out of the larger opening of the blind hole 308c).

Thereafter, referring to FIG. 18, a metal material may be formed in the opening of the patterned photoresist layer 412 by electroplating to simultaneously form the first ground layer 414a in the blind via 308a and form the first via the blind via 308b. A wiring layer 404b is formed, and a conductive blind via 404c is formed in the blind via 308c. As shown in FIG. 18, the top surfaces of the first ground layer 414a, the first wiring layer 404b, and the conductive blind vias 404c are substantially aligned with the top surface of the patterned photoresist layer 412, and the patterned photoresist layer 412 is used to increase The total thickness of the first ground layer 414a and the first wiring layer 404b is subsequently formed, and the conductive via hole 404c may be formed with the lower dielectric layer.

Next, referring to FIG. 19, a stripping step may be performed to remove the patterned photoresist layer 412. Thereafter, an etching step may be performed to remove the seed layer 310 on the top surface of the dielectric layer 306 to prevent the first ground layer 414a, the first wiring layer 404b, and the conductive via 404c from being electrically connected to each other. Short circuit. At this time, the dielectric layer 306, the first ground layer 414a, the first wiring layer 404b, and the conductive via 404c form a build-up wiring structure 450, wherein the first ground layer 414a has a thickness at least the thickness of the first wiring layer 404b. 1.5 times or more, and the first circuit layer 404b is shielded around the metal, and thus the first ground layer 414a is not electrically connected to any component, for example, may be floating or ground. In another embodiment of the present invention, the build-up line structure can also be formed by chemical deposition or electroless plating, in which case it is not necessary to form a seed layer in advance.

Thereafter, referring to FIG. 20, the process of FIGS. 14-19 can be repeated to form a plurality of vertically stacked build-up line structures on the build-up line structure 450, such as a second formed in the dielectric layer 416. The ground layer 414b, the second wiring layer 422b, and the conductive blind via 422c, and the third ground layer 414c, the third wiring layer 432b, and the conductive blind via 432c formed in the dielectric layer 430.

Then, referring to FIG. 21, the process of FIG. 11 can be repeated, and the insulating layer 434 can be formed on the build-up line structure by coating, attaching or pressing, and selectively formed in the insulating layer 434. A plurality of openings 436 are exposed and a portion of the conductive blind vias 432c are exposed. In the embodiment of the present invention, the insulating layer 434 may include the same material as the insulating layer 234 shown in FIG.

Next, referring to FIG. 22, the process of FIG. 12 can be repeated, and a pre-solder bump 438 can be formed in the opening 436 by a printing, deposition or patterning process to electrically connect the pre-solder bump 438 to Conductive blind hole 432c. In the embodiment of the present invention, the pre-solder bump 438 may comprise the same material as the pre-solder bump 238 shown in FIG. After the above process, the multilayer printed circuit board electrical structure 500b of the embodiment of the present invention is formed.

Fig. 23 is an enlarged view of a region 440 of Fig. 22 showing the positional relationship of the first wiring layer 404b, the first ground layer 414a, and the dielectric layer 306. The first circuit layer is formed by first forming the dielectric layer 306 and then performing laser drilling and attaching the patterned photoresist layer, and then forming the first wiring layer 404b and the first ground layer 414a having a thick total thickness by electroplating. The top surfaces of the 404b and the first ground layer 414a are aligned with each other and electrically insulated from each other, and the thickness T _{4 of the} first ground layer 414a is at least 1.5 times the thickness T ₃ of the first circuit layer 404b, and the first ground layer 414a is surrounded. And the metal shields the first circuit layer 404b, and thus the first ground layer 414a is not electrically connected to any component, for example, may be floating or ground. In addition, the top surface of the dielectric layer 306 is interposed between the top surface and the bottom surface of the first wiring layer 404b and the first ground layer 414a.

In addition to the advantages of the multilayer printed circuit board electrical structure 500a, the multilayer printed circuit board electrical structure 500b of the embodiment of the present invention utilizes a laser drilling step with an image transfer process to form different layers in the dielectric layer. The depth of the blind hole increases the depth of the blind hole, so that the circuit layer and the ground layer having a relatively thick total thickness can be formed by electroplating, chemical deposition or electroless plating.

24 to 30 are cross-sectional views showing a process of the multilayer printed circuit board electrical structure 500c according to still another embodiment of the present invention, which is formed by forming a dielectric layer and then using a laser drilling step to form a dielectric layer. Blind holes of different depths are then formed with a patterned photoresist layer exposing the ground layer, and then a grounding layer having an increased thickness is formed by electroplating. If the components in the above drawings have the same or similar parts as those shown in Figures 14 to 16, reference may be made to the related description above, and the description thereof will not be repeated.

Referring to FIG. 24, a metal layer 312 can be formed by electroplating and filled into the blind vias 308. As shown in Fig. 24, the thickness of the metal layer 312 is greater than the depth of the blind via 308 such that the top surface of the metal layer 312 substantially maintains a plane. In an embodiment of the invention, the material of the metal layer 312 may include nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, rhenium or a combination thereof or an alloy thereof.

Next, referring to FIG. 25, the metal layer 312 on the top surface of the seed layer 310 outside the blind via can be removed by grinding or etching to form the first lower ground layer 314a in the blind via 308a. A first wiring layer 304b is formed in the blind via 308b, and a conductive blind via 304c is formed in the blind via 308c.

Thereafter, referring to FIG. 26, after the first lower ground layer 314a, the first wiring layer 304b, and the conductive blind via 304c are formed, a photoresist layer may be entirely covered by attaching. The exposure and development steps are further performed to form a patterned photoresist layer 512 on the dielectric layer 306. As shown in FIG. 26, the patterned photoresist layer 512 has a plurality of openings 508a exposed and connected to the first lower ground layer 314a and a plurality of openings 508c exposed to the conductive vias 304c (above the blind vias 304c) The opening 508c can correct the opening size according to the alignment condition, and can also open the opening of the same size as the blind hole 304c as in the 17th figure.

Thereafter, referring to FIG. 27, a metal layer may be formed in the openings 508a and 508c by electroplating, and cover the first lower ground layer 314a and the conductive blind via 304c, respectively. After the above process, the total thickness of the first lower ground layer 314a is increased in the opening 508a by using the metal layer to form the first ground layer 514a, and at the same time, the conductive pad 522c is formed in the opening 508c by using the above metal layer, and the electrical property thereof is formed. Connected to the conductive blind via 304c underneath. Next, a stripping step can be performed to remove the patterned photoresist layer 512. Thereafter, an etching step may be performed to remove a seed layer 310 on the top surface of the dielectric layer 306 outside the blind via to avoid the first ground layer 514a, the first wiring layer 304b, and the conductive pad 522c/conductive blind. The holes 304c are electrically connected to each other to cause a short circuit. At this time, the dielectric layer 306, the first ground layer 514a, the first circuit layer 304b, the conductive via 304c, and the conductive pad 522c form a build-up line structure 550, wherein the first ground layer 514a has a thickness of at least the first line. The layer 304b is more than 1.5 times thicker and the first wiring layer 304b is shielded around the metal, and thus the first ground layer 514a is not electrically connected to any component, such as floating or ground.

Thereafter, referring to FIG. 28, the processes of FIGS. 14-16 and 24-27 can be repeated to form a plurality of vertically stacked build-up line structures on the build-up line structure 550, for example, in the dielectric layer 516. The formed second ground layer 514b, the second wiring layer 322b, the conductive blind via 322c and the conductive pad 532c, and the third ground layer 514c, the third wiring layer 332b, the conductive blind via 332c and the conductive layer formed in the dielectric layer 530 Pad 542c.

Then, referring to FIG. 29, the process of FIG. 11 can be repeated, and the insulating layer 534 is formed on the build-up line structure by coating, attaching or pressing, and selectively formed in the insulating layer 534. A plurality of openings of a portion of the conductive pads 542c are exposed. In the embodiment of the present invention, the insulating layer 434 may include the same material as the insulating layer 234 shown in FIG. Then, the process of FIG. 12 can be repeated, and a pre-solder bump 538 can be formed in the opening by a printing, deposition or patterning process to electrically connect the pre-solder bump 538 to the conductive pad 542c. In the embodiment of the present invention, the pre-solder bump 538 may comprise the same material as the pre-solder bump 238 shown in FIG. After the above process, the multilayer printed circuit board electrical structure 500c of the embodiment of the present invention is formed.

Figure 30 is an enlarged view of a region 540 of Figure 29 showing the positional relationship of the first wiring layer 304b, the first ground layer 514a, and the dielectric layer 306 of the multilayer printed circuit board electrical structure 500c of the embodiment of the present invention. After the dielectric layer 306 is formed first, the blind holes of different depths are formed in the dielectric layer 306 by using the laser drilling step, and then the patterned photoresist layer 512 exposing the first lower ground layer 314a is attached. A first ground layer 514a of increased thickness is then formed by electroplating. Therefore, the top surface of the first ground layer 514a of the same build-up layer is higher than the top surface of the first circuit layer 304b and electrically insulated from each other, and the thickness T _{6 of the} first ground layer 514a is at least the thickness T of the first circuit layer 304b. 1.5 times or more of ₅ , the first ground layer 514a surrounds and metal shields the above-mentioned build-up wiring layer 304b, and thus the first ground layer 514a is not electrically connected to any component, for example, may be floating or grounded ( Ground). In addition, the top surface of the dielectric layer 306 is aligned with the first wiring layer 304b and between the top surface and the bottom surface of the first ground layer 514a.

In addition to the advantages of the multilayer printed circuit board electrical structure 500a, the multilayer printed circuit board electrical structure 500c of the embodiment of the present invention utilizes a laser drilling step to form blind holes of different depths in the dielectric layer, and then pastes A patterned photoresist layer exposing the ground layer and the conductive blind via is formed, and then a grounding layer having an increased thickness is formed by electroplating, and a conductive pad is formed at the same time, and the signal of the fan-out wiring is formed when the layer is formed. The ground plane also provides better metal shielding for the build-up wiring layer.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope is defined as defined in the scope of the patent application.

104. . . Signal line

102. . . Grounded copper layer

150a~150c. . . Addition

104a~104c. . . Signal line area

102a~102c. . . Ground copper layer

200. . . Circuit substrate

202. . . Via

203. . . Perforated resin

204. . . Circuit layer

204a, 314a. . . First lower ground plane

214a, 414a, 514a. . . First ground plane

214b, 414b, 514b‧‧‧ second ground plane

214c, 414c, 514c‧‧‧ third ground plane

222a‧‧‧Second lower ground plane

204b, 304b, 404b‧‧‧ first line layer

222b, 322b, 422b‧‧‧ second circuit layer

232b, 332b, 432b‧‧‧ third circuit layer

204c, 222c, 232c, 522c, 532c, 542c‧‧‧ conductive pads

207‧‧‧Line structure

206, 208, 220, 224, 412, 512‧‧‧ patterned photoresist layer

210, 226, 236, 436, 508a, 508c‧‧

212, 228, 312‧‧‧ metal layers

216, 230, 306, 416, 430, 516, 530‧‧ dielectric layers

250‧‧‧Line structure

450, 550‧‧‧Additional line structure

201, 231, 304c, 322c, 332c, 404c, 422c, 432c‧‧‧ conductive blind holes

234, 434, 534‧‧ ‧ insulation

238, 438, 538‧‧‧Pre-solder bumps

240, 440, 540‧‧‧ areas

308, 308a~308c‧‧‧ blind holes

310‧‧‧ seed layer

T ₁ ~T ₆ ‧‧‧thickness

500a~500c‧‧‧Multilayer printed circuit board electrical structure

1 is a cross-sectional view showing an electrical structure of a conventional multilayer printed circuit board showing the arrangement relationship between a signal line and a grounded copper layer.

FIG. 2 is a schematic diagram showing the different levels of electrical layers of the conventional multilayer printed circuit board, showing the arrangement relationship of the signal line regions and the grounded copper layer regions of different horizontally layered layers.

3 to 13 are cross-sectional views showing the process of the electrical structure of the multilayer printed circuit board according to an embodiment of the present invention.

14 to 23 are cross-sectional views showing processes of an electrical structure of a multilayer printed circuit board according to another embodiment of the present invention.

24 to 30 are cross-sectional views showing processes of an electrical structure of a multilayer printed circuit board according to still another embodiment of the present invention.

200. . . Circuit substrate

201, 231. . . Conductive blind hole

202. . . Via

203. . . Perforated resin

214a. . . First ground plane

214b. . . Second ground plane

214c. . . Third ground plane

204b. . . First circuit layer

222b. . . Second circuit layer

232b. . . Third circuit layer

204c, 222c, 232c. . . Conductive pad

216, 230. . . Dielectric layer

234. . . Insulation

238. . . Pre-solder bump

240. . . region

500a. . . Multilayer printed circuit board electrical structure

Claims (9)

An electrical structure of a multilayer printed circuit board, comprising: a circuit substrate; a dielectric layer disposed on the circuit substrate; and a circuit layer and a ground layer electrically insulated from each other, respectively disposed on the circuit substrate, and Contacting the dielectric layer respectively, wherein the circuit layer and the ground layer are in the same build-up layer, and the ground layer has a thickness at least 1.5 times the thickness of the circuit layer, and the ground layer is metal-shielded around the circuit layer The circuit layer, wherein a top surface of the ground layer is higher than a top surface of the dielectric layer, and wherein a bottom surface of the ground layer is lower than a bottom surface of the circuit layer. The multilayer printed circuit board electrical structure of claim 1, further comprising a pre-solder bump electrically connected to the circuit layer and not electrically connected to the ground layer. The multilayer printed circuit board electrical structure of claim 1, wherein the circuit layer or the ground layer further passes through a portion of the dielectric layer. The multilayer printed circuit board electrical structure of claim 3, wherein a top surface of the dielectric layer is interposed between the circuit layer and a top surface and a bottom surface of the ground layer. The multilayer printed circuit board electrical structure of claim 3, wherein a top surface of the dielectric layer is aligned with a top surface of the circuit layer. A method for manufacturing a multilayer printed circuit board electrical structure, comprising the steps of: providing a circuit substrate; forming a dielectric layer on the circuit substrate; and forming a circuit layer electrically insulated from each other on the circuit substrate a ground layer, respectively, in contact with the dielectric layer, wherein the circuit layer and the ground layer are in the same build-up layer, and the ground layer has a thickness at least 1.5 times the thickness of the circuit layer, and the ground layer surrounds the ground layer The circuit layer shields the circuit layer with metal, wherein a top surface of the ground layer is higher than a top surface of the dielectric layer, and wherein a bottom surface of the ground layer is lower than a bottom surface of the circuit layer. The method for manufacturing a multilayer printed circuit board electrical structure according to claim 6, wherein the step of forming the circuit layer and the ground layer electrically insulated from each other on the circuit substrate further comprises: the dielectric layer Forming a first patterned photoresist layer thereon; forming the circuit layer and the lower ground layer simultaneously on the circuit substrate not covered by the first patterned photoresist layer; covering a second patterned photoresist layer, Having an opening exposing the lower ground layer; forming a metal layer on the lower ground layer not covered by the second patterned photoresist layer, such that the lower ground layer and the metal layer thereon form the ground layer And removing the first and second patterned photoresist layers. The method for manufacturing a multilayer printed circuit board electrical structure according to claim 6, wherein the step of forming the circuit layer and the ground layer electrically insulated from each other on the circuit substrate further comprises: the dielectric layer Forming a first blind via and a second blind via, wherein the first blind via has a depth greater than a depth of the second blind via; conforming to forming a seed layer on the dielectric layer and covering the first a blind hole and an inner wall of the second blind hole; forming a patterned photoresist layer on the seed layer, which has an exposed and connected a plurality of openings to the first blind via and the second blind via; forming a metal material in the openings of the patterned photoresist layer to form the ground layer in the first blind via, and a second blind via is formed in the circuit layer, wherein a top surface of the ground layer and the wiring layer is substantially aligned with a top surface of the patterned photoresist layer; and a patterned photoresist layer and a dielectric layer are removed The extra seed layer on the top surface. The method for manufacturing a multilayer printed circuit board electrical structure according to claim 6, wherein the step of forming the circuit layer and the ground layer electrically insulated from each other on the circuit substrate further comprises: the dielectric layer Forming a first blind via and a second blind via, wherein the first blind via has a depth greater than a depth of the second blind via; conforming to forming a seed layer on the dielectric layer and covering the first a blind hole and an inner wall of the second blind hole; integrally forming a first metal layer and filling the first blind hole and the second blind hole, wherein a thickness of the metal layer is greater than the first blind hole and the Depth of the second blind hole; removing the first metal layer on the top surface of the seed layer outside the first blind hole and the second blind hole; forming a patterned photoresist layer on the dielectric layer, An opening that is exposed and communicated to the first blind hole; a second metal layer is formed in the opening, and covers the first metal layer in the first blind hole to make the first blind hole Forming the ground layer with the first metal layer and a second metal layer thereon; and removing the patterned photoresist layer and the first Blind hole and the second blind hole The seed layer on the top surface of the dielectric layer forms the wiring layer in the second blind via.