200840447 22355tw£doc/e 九、發明說明： 【發明所屬之技術領域】 本發明疋有關於一種線路板之線路結 . 構及其線路（trace)製程，且特別是有關於一種在同一線 . 路層中具有多條不同厚度之線路結構及其線路製程。 【先前技術】 現代的社會大眾已普遍地使用訴求短、小、輕、薄的 _ 手機（cellular Phone)、筆記型電腦（noteb〇〇k PC)以及 個人數位助理機（personal digitai assistant，pda)等可攜 式電子產品。在這些電子產品的必要零件中，除了晶片 (chip )與被動元件（passive c〇mp〇nent)等電子元件之外， 承載與配置這些晶片與被動元件的線路板也是十分重要的 零件。 圖1是習知一種線路板之剖面示意圖。圖1所示的線 路板ίου是目前一般常見的四層線路板（four_layers wijing board)，其由二訊號層110a與11〇b、接地層12〇、電源 響 層13〇以及二層介電層140a、140b、140c組成的基本疊板 結構。訊號層ll〇a、ll〇b已佈局好多條訊號線路η〕，而 電子元件10組裝在訊號層ll〇a上，並與訊號線路112電 性連接。此外，電源層130可對外連接電源，以驅動裝設於 線路板100上的電子元件1〇,並使電子元件1〇的輸入/輸出訊 號可經由訊號線路112傳遞而運作。接地層120配置於訊號 層110a與電源層130之間，且訊號層11〇&與11〇b、接地 層120以及電源層130分別以介電層14〇a、14〇b、M〇c 5 200840447 22355tw£doc/e 相隔於其中，以作為絕緣之用。 為了讀保訊號傳遞的正確性與釋定性、， 訊號線路112能共同對應向—表、、: ，並使同一層的 平面），來作為輪入或輪^源平面或接地 地層12〇與電源層⑽皆製成之電麵考準位，接 在訊號層llGa的下方=面積的導電平面，並配置[Technical Field] The present invention relates to a circuit board wiring structure and a trace process thereof, and particularly relates to a line in the same line. The layer has a plurality of line structures of different thicknesses and a line process thereof. [Prior Art] The modern society has generally used short, small, light, and thin cellular phones, notebook computers (noteb〇〇k PC), and personal digitai assistants (pda). And other portable electronic products. In the necessary parts of these electronic products, in addition to electronic components such as chips and passive components, circuit boards carrying and arranging these wafers and passive components are also very important parts. 1 is a schematic cross-sectional view of a conventional circuit board. The circuit board shown in FIG. 1 is a commonly used four-layer board (four_layers wijing board), which is composed of two signal layers 110a and 11〇b, a ground layer 12〇, a power layer 13 〇, and a second dielectric layer. The basic stack structure consisting of 140a, 140b, 140c. The signal layers 11a, 11b have been arranged with a plurality of signal lines η], and the electronic component 10 is assembled on the signal layer 11a and electrically connected to the signal line 112. In addition, the power layer 130 can be externally connected to the power source to drive the electronic components mounted on the circuit board 100, and the input/output signals of the electronic components 1 can be transmitted via the signal line 112. The ground layer 120 is disposed between the signal layer 110a and the power layer 130, and the signal layers 11 amp & 11 〇 b, the ground layer 120 and the power layer 130 are respectively dielectric layers 14 〇 a, 14 〇 b, M 〇 c 5 200840447 22355tw£doc/e is separated from it for insulation purposes. In order to read the correctness and release of the signal transmission, the signal line 112 can collectively correspond to the direction, the table, and the plane of the same layer, as the wheel or wheel source plane or the ground layer 12 〇 and the power source. The electrical plane of the layer (10) is measured, connected to the conductive plane below the signal layer llGa = area, and configured
的接地層120、電源声 "口貝然而，大面積 板100的層數及厚度θ，無 1路=計上會增加線路 積集度線路板的需求。^付D日益普及的薄化、高 及，不同訊號源：同—卢隨/严頻電咖^ 遞訊號時，受到雜訊耦合曰的5影:“丄〇:匕11〇b)傳 情況更為嚴重。因此，^ a產生电磁波干擾的 σ$ 避免訊號傳遞時失真，並提 子元件崎作正常，實關不容緩 【發明内容】 路制^月之目的是提供H路板之祕結構及其線 改魏號線_的電子訊號互相干擾之缺點， 進而提升訊號傳遞的品質。 --綠"明提出—種線路板之線路結構，其包括介電層、 二二二路（trace)以及多條第二線路。介電層具有一表面、 =—凹刻圖案以及多個第二凹刻圖案，而第—凹刻圖案 _凹刻圖案位於介電層的表面之下。第—線路以及這 些弟二線路分別配置於第一凹刻圖案與第二凹刻圖案内， 6 200840447 22355twf.doc/e 路為屏蔽線路，而第二線路為訊號傳輪線路， 且弟-線路的厚度大於第二線_厚度。，路 半，2發明之—實施例中，第—凹刻圖案包括_第—溝 第—溝泪：凹刻圖案包括多條第二溝渠。第-線路配置於 内。第木# ’ ^些第二線路分別配置於這些第二溝竿 二的表™於各第二‘ 發ί實㈣巾，魏板之祕結構更包括第 說源第—訊號源，而第二線路對應第—與第二訊 ^、n:第—訊號傳輸線路以及第二訊號傳輸線路。此 路之^例中’第—線路位於第—與第二訊號傳輸線 :’以避免不同訊號源之間的雜訊干擾。 驟：、^月又提出一種線路板的線路製程，其包括以下步 多個，於一介電層之一表面下形成一第一凹刻圖案與 案=弟二關圖案。接著，形成—第—線路於第一凹刻圖 及形成多條第二線路於第二凹刻圖案内，其中第 線路的厚度大於每條第二線路的厚度。 刻圖ί本發明之—實施例中，形成第—凹刻圖案與第二凹 包括形成—第—溝渠與多條第二溝渠於該表 第一、:中第―輕相對於介電層的表面之深度大於每條 I溝渠相對於介電層的表面之深度^ 刻^本發明之—實施例中，形成i-凹刻圖案與第二凹 蝕Y /、的方法包括利用一雷射光對介電層的表面進行燒 200840447 22355twf.doc/e 一線路是 隹本贫明之一賞施例中，第一線路與這此 以電鐘法（electroplating)形成。 在本發明之-實施例中，在形成第—線路卜 線路之後，更包括形成一保護層於介電層上，二弟二 覆蓋第一線路與這些第二線路。 /、中保護層 本發明之線路板之線路結構藉由厚度 路來隔開這些第二線路，以避免這些第二線路=弟―線 號互相預，進而提升傳遞電子訊號的品質。内的電子訊 為讓本發明之上标其他目的、特徵 2下了文特舉較佳實施例’並配合所附圖式; 【實施方式】 ^ 一實施例 圖2是本發明第-實施例之線路 示意圖。需事先說明的是，本發明的剖面 層、四層、六層、八層或以上的多 ^構可以用於二 路結構的配置形態為代表說明，^ 板’圖2僅以線 線路層，或作為線路板中任何—層板的最外層 路板可選擇在完成習知線路板的内層因此，線 以增層法或疊合法完成本發明的線路衣表之後’接著 路層’或是在進行内層線路製程之产、、° M作為最外層線 一併完成本發明的線路製程，以以增層法或疊合法 路結構。故，本發明之圖 7二秦路板中任一層的線 制本發明。 便説明，並非用以限 δ 200840447 22355twf.doc/e 請2 ’線路板，線路結構包 21〇、-弟-線路22〇以及多條第二線路23q，== 路22〇,，第二線路23〇内埋於介電層⑽之二 内。值得注意的是，線路板之線 / & :，。的厚度刚二線:二== ς而=從圖2來看，第一線路22〇的厚度τ 二Grounding layer 120, power supply sound " mouth, however, the number of layers and thickness θ of the large-area board 100, no one road = will increase the demand for line accumulating circuit boards. ^Pay D is increasingly popular, thin, high, and different signal sources: the same - Lu Sui / Yan frequency electric coffee ^ When the signal is transmitted, the noise is coupled with 5 shadows: "丄〇:匕11〇b) More serious. Therefore, ^ a generates electromagnetic interference σ$ to avoid distortion when transmitting signals, and the sub-components are normal, and the real thing is not to be delayed. [Inventive content] The purpose of the road system is to provide the secret structure of the H-channel. The shortcomings of the electronic signals that interfere with the Wei line _, and thus improve the quality of the signal transmission. - Green "Ming proposed - the circuit structure of the circuit board, which includes the dielectric layer, two or two roads (trace And a plurality of second lines. The dielectric layer has a surface, a = intaglio pattern, and a plurality of second intaglio patterns, and the first intaglio pattern - intaglio pattern is located below the surface of the dielectric layer. The line and the two lines are respectively disposed in the first intaglio pattern and the second intaglio pattern, 6 200840447 22355twf.doc/e is a shielded line, and the second line is a signal transmission line, and the thickness of the line-line Greater than the second line _ thickness., the road half, 2 inventions - in the embodiment, The intaglio pattern comprises a _ _ d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d Table TM is in the second 'supplement' (four) towel, the secret structure of the Wei board includes the source of the source - the source of the signal, and the second line corresponds to the first and the second message ^, n: the first signal transmission line and the The second signal transmission line. In the case of the road, the 'first line is located at the first and the second signal transmission line: 'to avoid noise interference between different signal sources. Step: ^^ month also proposes a circuit board circuit process The method includes the following steps: forming a first intaglio pattern and a pattern in the surface of one of the dielectric layers. Then, forming a first line to form a first intaglio pattern and forming a plurality of lines The second line is in the second intaglio pattern, wherein the thickness of the first line is greater than the thickness of each of the second lines. In the embodiment of the present invention, forming the first intaglio pattern and the second recess includes forming - the first Ditch and a number of second ditches in the table first,: the first - light relative to the media The depth of the surface of the layer is greater than the depth of each of the I trenches relative to the surface of the dielectric layer. In the embodiment of the invention, the method of forming the i-etched pattern and the second recessed Y/, includes utilizing a The light is applied to the surface of the dielectric layer. 200840447 22355 twf.doc/e The first line is formed by electroplating in the embodiment of the present invention. In the present invention - the embodiment After forming the first line, the circuit further comprises forming a protective layer on the dielectric layer, and the second two covers the first line and the second lines. /, the middle protective layer is formed by the circuit structure of the circuit board of the present invention. These second lines are separated by a thickness path to prevent these second lines from being mutually pre-wired, thereby improving the quality of the transmitted electronic signals. The present invention is directed to other objects and features of the present invention, and the preferred embodiment is described in conjunction with the accompanying drawings. [Embodiment] ^ Embodiment 2 FIG. 2 is a first embodiment of the present invention. The schematic diagram of the line. It should be noted in advance that the cross-sectional layer, the four-layer, the six-layer, the eight-layer or more of the present invention can be used for the configuration of the two-way structure as a representative description, and the board 2 is only a line layer. Or as the outermost layer of any layer in the circuit board, the inner layer of the conventional circuit board can be selected. Therefore, after the line is layered or stacked to complete the line clothing table of the present invention, the 'continuous road layer' or For the production of the inner layer circuit process, the M is used as the outermost line to complete the line process of the present invention to form a layered method or a stacked circuit structure. Therefore, the present invention is made in accordance with any of the layers of the Fig. 7 second Qin road plate. It is stated that it is not limited to δ 200840447 22355twf.doc/e Please 2' circuit board, line structure package 21〇, - brother-line 22〇 and multiple second lines 23q, == road 22〇, second line 23〇 is buried in the second of the dielectric layer (10). It is worth noting that the line of the board / & :,. The thickness of the second line: two == ς and = from Figure 2, the thickness of the first line 22 τ τ
=線的厚* Τ2’而且第—線路22〇為屏蔽二， 弟一線路23〇為職傳輸線路 時，可藉由第—線路蔽—二合 (coupling)，以避免訊號相互干擾。 f實施例中，第—線路22G可以是接地屏蔽線路， 大面積的接地平面（树示，例如是機殼或金屬板) 機殼可將電子元件（例如是晶片或處理器，如圖 ♦工不）包覆於其中，以屏蔽外來電磁波的干擾。此外， =子兀件可與第二線路23()電性連接，以供傳遞訊號之 屑认使传電子兀件的輸人或輪出訊號可藉由第二線路230 傅輸而運作。 值彳于注思的是，電子元件可配置在線路板上或内埋於 二路板中，其可作為線路板的訊號源。當多個電子元件以 二一線路230來傳遞訊號時，第二線路23〇對應不同的訊 =源而區分為第一訊號傳輸線路23〇a以及第二訊號傳輸 ^路23〇b。如圖2所示，第_訊號傳輸線路23〇a為A群 =線路，用以傳輸第一訊號源的訊號，而第二訊號傳輸線 23〇b為B群組線路，用以傳輸第二訊號源的訊號，為 9 200840447 22355twf.doc/e J：間=雜訊干擾’本發明以厚度較厚 —置於廷些第二線路230之間，以將A、 可以八ίι ❿這些A群組與B群組線路23Ga、230b T1別傳遞兩種列來源或類㈣電子訊號。 mi路220與第二線路230可採用銅、铭或其他適 t的金屬材料製成，且第—線路220的厚度比每一條第二 '路23G厚’其可形成高屏蔽牆來阻隔分佈於A群組與b= line thickness * Τ 2' and the first line 22 〇 is the shield 2, and the second line 23 〇 is the transmission line, the first line can be combined with the coupling to avoid signal interference. In the embodiment, the first line 22G may be a grounded shielded line, and a large area of the ground plane (shown, for example, a casing or a metal plate). The casing may carry electronic components (for example, a wafer or a processor, as shown in FIG. Do not cover it to shield the interference of external electromagnetic waves. In addition, the sub-device can be electrically connected to the second line 23 () for transmitting the signal to recognize that the input or the round-out signal of the electronic component can be operated by the second line 230. The value is that the electronic components can be placed on the circuit board or buried in the two-way board, which can be used as the signal source of the circuit board. When a plurality of electronic components transmit signals by the two-wire line 230, the second line 23 is divided into a first signal transmission line 23a and a second signal transmission line 23a corresponding to different sources. As shown in FIG. 2, the _ signal transmission line 23 〇 a is a group = line for transmitting the signal of the first signal source, and the second signal transmission line 23 〇 b is a group B line for transmitting the second signal. The source signal is 9 200840447 22355twf.doc/e J: inter-noise interference 'the invention is thicker than thicker' - placed between the second line 230 of the court, to A, can eight ί ❿ these group A Two column sources or class (four) electronic signals are transmitted with the B group lines 23Ga, 230b T1. The mi road 220 and the second line 230 may be made of copper, metal or other suitable metal materials, and the thickness of the first line 220 is thicker than each second '23G', which can form a high shielding wall to block distribution. Group A and b
===間的電場以及電磁場，以使電磁效應所產生的雜 訊干^降低，進而不影響訊號傳輸的品質。因此利用接 地屏敝效，，第-線路22〇可以作為A群組與B群組線路 之間的屏蔽線路。> 此，能避免A群組内肖B群組内的電 子訊號互相干擾，進而提升線路板之線路結構2〇〇内之電 子訊號的傳遞品質。 私 在本實施例中，第一訊號傳輸線路23〇a例如是數位 訊號傳輸線路，而第二訊號傳輸線路23〇b例如是類比訊號 傳輸線路，利用屏蔽線路（即第一線路22〇)可使數位訊 號與類比訊號不會相互干擾。在另一實施例中，第一訊號 傳輸線路230a例如是高頻訊號傳輸線路，而第二訊號傳輸 線路230b例如是低頻訊號傳輸線路，利用屏蔽線路能使高 頻訊號與低頻訊號不會相互干擾。另外，第一訊號傳輸線 路230a亦可以是高壓訊號傳輸線路，而第二訊號傳輸線路 230b是低壓訊號傳輸線路，而利用屏蔽線路可使高壓訊號 與低壓訊號不會相互干擾。The electric field between the === and the electromagnetic field, so that the noise generated by the electromagnetic effect is reduced, so that the quality of the signal transmission is not affected. Therefore, the use of the ground screen is effective, and the first line 22 can be used as a shield line between the A group and the B group line. > This can avoid the mutual interference of the electronic signals in the group B in the group A, thereby improving the transmission quality of the electronic signals in the circuit structure 2 of the circuit board. In this embodiment, the first signal transmission line 23〇a is, for example, a digital signal transmission line, and the second signal transmission line 23〇b is, for example, an analog signal transmission line, and the shielding line (ie, the first line 22〇) can be used. The digital signal and the analog signal do not interfere with each other. In another embodiment, the first signal transmission line 230a is, for example, a high-frequency signal transmission line, and the second signal transmission line 230b is, for example, a low-frequency signal transmission line. The shielded line can prevent high-frequency signals and low-frequency signals from interfering with each other. . In addition, the first signal transmission line 230a may also be a high voltage signal transmission line, and the second signal transmission line 230b is a low voltage signal transmission line, and the shielded line may be used to prevent the high voltage signal and the low voltage signal from interfering with each other.
接下來將介紹本實施例之線路板的線路製程。圖3A 200840447 22355twf.doc/e 至圖3G為圖解圖2之線路結構的製作流程示意圖。請先 參閱圖3A與圖3B，首先’在介電層210的表面21〇a下 形成弟一凹刻圖案212與多個第二凹刻圖案214，也就是 形成第一溝渠212a與多條第二溝渠214a於表面21〇a。第 一溝渠212a與這些第二溝渠214a兩者相對於表面21〇a的 深度不同。在本實施例中，第一溝渠212a相對於表面21〇a 的深度大於與每一第二溝渠214a相對於表面21加的深度。 承上述，，可以用一雷射光對介電層210的表面210a 進行燒蝕，以形成不同深度的第一溝渠212a與第二溝渠 214a。在本實施例中，可以調整雷射光的強度或是 210a燒蝕的時間，以達到第一溝渠212a相對於表面21加 的深度大於各第二溝渠214a相對於表面21〇a的深度。除 了上述雷射燒蝕的方法之外，也可以利用微影與蝕刻 ^lithography)或其他相關的方法來形成第一溝渠21%與Next, the line process of the circuit board of this embodiment will be described. 3A 200840447 22355twf.doc/e to FIG. 3G are schematic diagrams showing the manufacturing process of the line structure of FIG. 2. Referring to FIG. 3A and FIG. 3B, firstly, a dimple pattern 212 and a plurality of second intaglio patterns 214 are formed under the surface 21〇a of the dielectric layer 210, that is, the first trench 212a and the plurality of strips are formed. The second trench 214a is on the surface 21〇a. Both the first trench 212a and the second trench 214a have different depths relative to the surface 21A. In the present embodiment, the depth of the first trench 212a relative to the surface 21A is greater than the depth of each of the second trenches 214a relative to the surface 21. In the above, the surface 210a of the dielectric layer 210 can be ablated with a laser light to form the first trench 212a and the second trench 214a of different depths. In this embodiment, the intensity of the laser light or the time of ablation of the 210a may be adjusted to achieve a depth of the first trench 212a relative to the surface 21 greater than a depth of each of the second trenches 214a relative to the surface 21A. In addition to the above method of laser ablation, it is also possible to form a first trench 21% by using lithography and etching (lithography) or other related methods.
第-，渠2Ha。㈣本發賴屬技術領域之具有通常知識 者在參照本文後應當可以自行推知前賴影絲刻的方 法，因此在此不介紹上述微影與蝕刻的方法。 μ請蒼_ 3C’在本實施例中，在形成第—溝渠21: 與第二溝渠214a之後，於介電層21()的表面肠上形; -種子層240，其全面性地覆蓋介電層21()。也就是說，^ 子層24〇 *但覆蓋介電層训的表面驗，也覆蓋這些; :溝渠214a與第-溝渠212a的底部與内壁。在本實施名 :，種子層240的材質可以是銘、銅或其他適當的金屬本 料’而形成種子層240的方法可以是無電_ 11 200840447 22355twf.doc/e (electroless plating )、物理氣相沉積（physical vapor deposition，PVD)、化學氣相沉積（chemical vap〇r deposition， CVD)、龟~氣相沉積法（eiectr〇iytic vapor deposition) 或其他適當的方法。 請蒼閱圖3D，在形成種子層240之後，可接著形成 一圖案化防鍍層250，其部分覆蓋種子層24〇並暴露位在 第一溝渠212a與這些第二溝渠214a内的種子層24〇。圖 案化防鍍層250可以是顯影後的乾膜光阻、濕式光阻、其 他適當的光阻層或絕緣材料層。接著，請參閱圖3E，對種 子層240進行電鍍以形成第一線路22〇與第二線路23〇。No. - Canal 2Ha. (4) Those who have common knowledge in the technical field of the present invention should be able to infer the method of lithography before they refer to this article. Therefore, the above methods of lithography and etching are not introduced here. In the present embodiment, after forming the first trench 21: and the second trench 214a, it is formed on the surface of the dielectric layer 21(); the seed layer 240 is comprehensively covered. Electrical layer 21 (). That is to say, the sub-layer 24 〇 * but covering the surface inspection of the dielectric layer training also covers these; the bottom and inner walls of the trench 214a and the first trench 212a. In the present embodiment, the material of the seed layer 240 may be a metal, or a suitable metal material, and the seed layer 240 may be formed without electricity. 11 200840447 22355twf.doc/e (electroless plating), physical gas phase Physical vapor deposition (PVD), chemical vap〇r deposition (CVD), eiectr〇iytic vapor deposition or other suitable methods. 3D, after forming the seed layer 240, a patterned anti-plating layer 250 can be formed, which partially covers the seed layer 24 and exposes the seed layer 24 in the first trench 212a and the second trenches 214a. . The patterned anti-plating layer 250 can be a developed dry film photoresist, wet photoresist, other suitable photoresist layer or layer of insulating material. Next, referring to Fig. 3E, the seed layer 240 is electroplated to form a first line 22 and a second line 23A.
由於圖案化防鍍層250部分覆蓋種子層24〇，因此，當對 種子層240進行電鍍時，能防止表面21此上的種子層2肋 ’交厚，以減少電鍍液的消耗，進而降低電鍍的成本。 之後，依序移除圖案化防鍍層MO以及表面2i〇a上 的種子層24G，如目3F所示。由_子層·的厚度很薄， =此可以抑研磨或微似彳（mi⑽etehing)的方式去除 表面210a上的種子層240。 值得-提的是，雖然圖3D、犯所 層胸以防止表面肠上的種子層m鐘 亦可以在不採用圖案化防二 的知况下凡成本叙明的線路板之線路結構2⑻。 目前本領域的通常知識者已知道可以_ ^ deCt_ating)，或者是於電鏡液中 2 土、、客态，w u 、、 Μ 别carrier)、 光澤心η加ener)與平整劑〇eveler)，以使在表面贏 12 200840447 2235!)twt.doc/e 上的種子層240 ’其厚度增加的速率遠小於在溝渠（212a 與214a) 0的種子層24〇。也就是說，在進行電鏡的過程 中，表面210a上的種子層24〇只會稍微變厚，甚至幾乎不 ^。此外，這種不採關案化隨層25G的方法也可以使 第一溝渠212a與這些第二溝渠214a内的種子層24〇之厚 度增加速率不同，進而可以同時完成不同厚度的第一線路 220與第1線路23〇。因此，圖3D、3E所示的圖案化防鐘 φ 層250只是舉例說明，而非限制本發明。 請，閱圖3G，在本實施例中，當形成第一線路22〇 ，、攻些苐二線路23G之後，更可以在介電層21()的表面 210a上形成-保護層，其覆蓋第一線路2如與這些第 二線路230，以保護第一線路220與第二線路230。保護層 260可以由樹脂或其他介電材料所製成，因此保護層· :作為線路_另—層介電層，並利用増層法在介電詹 210上形成一層或多層線路。 —貫施例 • ® 4)疋，發明第二實施例之線路板之線路結構的剖面 二二圖，°月*閱圖4 ’第二實施例的線路板之線路結構3〇〇 W Ϊ製程、結構及其第—線路320與第二線路330的功 U-實施例相似，故不再重複敘述。然而，第二實施 =的線路板之線路結構3⑽與第—實施例異之處在 線路板之線路結構3〇〇的多條第一線路32〇與多條第 一線路330之間的相對位置。 在本實施例中，第—線路320與第二線路330配置於 13 200840447 22355twf.doc/e =板之線路結構300的介電層310之表面31〇a内，而、言 二、二、泉路幻〇與弟一線路32Θ可依序交錯排列。因此^ 藉由^些隔開相鄰二條第二線路33㈣第一線路32 ，免k些第二線路33〇内的電子訊號互相干擾，以 路板線路結構3〇〇之電子訊號的傳遞品質。 線 紅上所述，本發明之線路板之線路結構利用厚度較戶 、弟一線路做為屏蔽線路，多條厚度較薄的第二線路作: 訊戒線路，並且第—線路配置於這些第二祕之間。如此、、， 用接地屏蔽效應，可使第—線路形成屏蔽牆來避免這些 弟二線路内的電子訊號互相干擾，進而防止電子訊號^ 真，以提升線路板之傳遞電子訊號的品質。 儿 ^雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習本發明所屬領域之具有通常知識 者，在不脫離本發明之精神和範圍内，當可作些許之更動 與潤飾，因此本發明之保護範圍當視後附之申請專利範圍 所界定者為準。 【圖式簡單說明】 圖1疋習知一種線路板之剖面示意圖。 一圖2是本發明第一實施例之線路板之線路結構的剖面 示意圖。 圖3A至圖3G為圖解圖2之線路板之線路結構的線 路製程之流程示意圖。 一圖4疋本發明第二實施例之線路板之線路結構的剖面 示意圖。 14 200840447 22355twi.doc/e 【主要元件符號說明】 1 〇 ·電子元件 112 :訊號線路 100 :線路板 120 :接地層 110a、ii〇b :訊號層 130 =電源層 140a、140b、140c ··介電芦 200、300 :線路板之線路結構 210、310 ··介電層 210a、310a :表面 212 :第一凹刻圖案 212a :第一溝渠 214 :第二凹刻圖案 214a :第二溝渠 220、320 :第一線路 230、330 :第二線路 230a :第一訊號傳輸線路 230b:第二訊號傳輸線路 240 :種子層 250 :圖案化防鍍層 260 :保護層 ΤΙ、T2 :厚度 _ 15Since the patterned anti-plating layer 250 partially covers the seed layer 24〇, when the seed layer 240 is plated, the seed layer 2 ribs on the surface 21 can be prevented from being thickened to reduce the consumption of the plating solution, thereby reducing the plating. cost. Thereafter, the patterned plating resist MO and the seed layer 24G on the surface 2i〇a are sequentially removed, as shown in Fig. 3F. The thickness of the layer _ sublayer is very thin, and this can remove the seed layer 240 on the surface 210a in a manner that inhibits grinding or micro-like mi (mi(10) etehing). It is worth mentioning that, although Fig. 3D, the layer of the chest is prevented to prevent the seed layer m on the surface of the intestine, the line structure 2(8) of the circuit board can be described without any use of the patterned anti-two. At present, the ordinary knowledge in the art has known that _ ^ deCt_ating), or in the electron microscopy liquid 2 soil, guest state, wu, Μ carrier), gloss η plus ener) and leveling agent 〇eveler) The seed layer 240' on the surface wins 12 200840447 2235!) twt.doc/e increases its thickness much less than the seed layer 24〇 in the trenches (212a and 214a) 0. That is to say, in the process of performing electron microscopy, the seed layer 24 on the surface 210a is only slightly thickened, or even hardly. In addition, the method of using the layer 25G can also make the thickness increase rate of the first trench 212a and the seed layer 24 这些 in the second trench 214a different, so that the first line 220 of different thickness can be simultaneously completed. With the first line 23 〇. Accordingly, the patterned anti-clock φ layer 250 illustrated in Figures 3D, 3E is merely illustrative and not limiting. Please refer to FIG. 3G. In this embodiment, after the first line 22 is formed and the second line 23G is formed, a protective layer may be formed on the surface 210a of the dielectric layer 21 ( A line 2 is associated with the second lines 230 to protect the first line 220 and the second line 230. The protective layer 260 may be made of a resin or other dielectric material, so that the protective layer is used as a wiring layer as a wiring layer, and one or more layers are formed on the dielectric substrate 210 by the germanium layer method. - Example: ® 4) 疋, Section 2 of the circuit structure of the circuit board of the second embodiment of the invention, °**Fig. 4 'Line structure of the circuit board of the second embodiment 3〇〇W ΪProcess The structure and its first line 320 are similar to the work U-embodiment of the second line 330, and therefore will not be repeated. However, the circuit structure 3 (10) of the second embodiment = is different from the first embodiment in the relative position between the plurality of first lines 32 〇 of the circuit board 3 〇 and the plurality of first lines 330 . In the present embodiment, the first line 320 and the second line 330 are disposed in the surface 31〇a of the dielectric layer 310 of the circuit structure 300 of the board 200840447 22355 twf.doc/e=, and the second, second, and spring The road illusion and the younger brother's line 32 can be staggered in order. Therefore, by separating the adjacent two second lines 33 (four) of the first line 32, the electronic signals in the second line 33 are prevented from interfering with each other, and the electronic signal transmission quality of the board line structure is reduced. According to the line red, the circuit structure of the circuit board of the present invention uses the thickness of the circuit as the shield line, and the second line with a thinner thickness is used as the signal line, and the first line is disposed in these lines. Between the second secretaries. In this way, the grounding shielding effect can be used to form the shielding wall to prevent the electronic signals in the two lines from interfering with each other, thereby preventing the electronic signal from being true, so as to improve the quality of the electronic signal transmitted by the circuit board. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and those skilled in the art to which the present invention pertains can be made without departing from the spirit and scope of the invention. The scope of protection of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a circuit board. Fig. 2 is a cross-sectional view showing the wiring structure of the wiring board of the first embodiment of the present invention. 3A to 3G are schematic flow charts showing the line process of the circuit structure of the circuit board of Fig. 2. Fig. 4 is a cross-sectional view showing the wiring structure of the wiring board of the second embodiment of the present invention. 14 200840447 22355twi.doc/e [Description of main components] 1 〇·electronic component 112: signal line 100: circuit board 120: ground plane 110a, ii〇b: signal layer 130 = power layer 140a, 140b, 140c ·· Electric reed 200, 300: circuit board circuit structure 210, 310 · dielectric layer 210a, 310a: surface 212: first intaglio pattern 212a: first trench 214: second intaglio pattern 214a: second trench 220, 320: first line 230, 330: second line 230a: first signal transmission line 230b: second signal transmission line 240: seed layer 250: patterned anti-plating layer 260: protective layer ΤΙ, T2: thickness _ 15