CN102244087A - Controllable power flip array light emitting diode (LED) chip and manufacturing method thereof - Google Patents

Controllable power flip array light emitting diode (LED) chip and manufacturing method thereof Download PDF

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CN102244087A
CN102244087A CN2011102147401A CN201110214740A CN102244087A CN 102244087 A CN102244087 A CN 102244087A CN 2011102147401 A CN2011102147401 A CN 2011102147401A CN 201110214740 A CN201110214740 A CN 201110214740A CN 102244087 A CN102244087 A CN 102244087A
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electrode
electrode layer
led chip
array
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邓朝勇
杨利忠
李绪诚
张荣芬
许铖
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Guizhou University
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Guizhou University
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Abstract

The invention discloses a controllable power flip array light emitting diode (LED) chip and a manufacturing method thereof. The controllable power flip array LED chip is an array consisting of a plurality of array units, wherein p electrode layers (10) of each row of all the array units are connected with one another and n electrode layers (5) of each column are connected with one another; in each array unit, an n-type buffer layer (3), an n-type semiconductor layer (6), an active layer (7), a p-type semiconductor layer (8), a transparent electrode layer (9) and the p electrode layer (10) are covered on a sapphire substrate (2); all the n electrode layers (5) and all the p electrode layers (10) are wrapped by insulation layers (4); the p electrode layers (10) of each row are connected with one another through p electrode connection metal layers (11) arranged above windows of the p electrode layers (10); and passivation layers (12) are arranged on the surfaces of the p electrode connection metal layers (11).

Description

Controlled power upside-down mounting array LED chip and manufacture method thereof
Technical field
The present invention relates to a kind of upside-down mounting array LED chip and manufacture method thereof, relate in particular to a kind of GaN controlled upside-down mounting array blue-light LED chip structure of base and manufacture method thereof that comprises the Multiple Quantum Well active area.
Background technology
White light LEDs has advantages such as brightness height, energy-conserving and environment-protective, has become one of the most potential lighting source.The energy consumption of white light LEDs only is 1/8 of an incandescent lamp, 1/2 of fluorescent lamp, and its life-span was 100,000 hours.This is " putting things right once and for all " concerning average family is bright, also can realize mercurylessly simultaneously, reclaims advantages such as easy, and is significant to environmental protection and energy savings.
The method for preparing at present large power white light LED mainly is to apply yellow fluorescent powder on blueness or near ultraviolet LED chip, obtains white light by colour mixture.This method that obtains white light by blue-ray LED, simple structure, with low cost, technology maturity is high, therefore utilization is extensively.The above large power white light LED of most of 5W is made by powerful blue-light LED chip.So make high-power blue-light LED chip is the basis that makes large power white light LED.
At present, the LED that regulates luminosity mainly is by following several modes: the first, single led chip mainly is that control is regulated luminosity by the electric current of led chip; The second, the combination of a plurality of led chip is regulated luminosity by the switch of controlling a plurality of led chips.But have differently because each led chip may not be electric property and the optical property of same batch of production, connect design and power drives by above control method, luminous harmony, the consistency of combined chip is relatively poor.
Present monochromatic display screen all has application on advertisement and the small-sized mobile digital equipment out of doors, so the monochromatic display screen of development LED also has very wide application prospect.
Summary of the invention
The technical problem to be solved in the present invention is, a kind of controlled power upside-down mounting array LED chip is provided, this chip can effectively be regulated the luminosity of high-power blue-ray LED flip-chip, also can be used as monochromatic display screen and uses, and reaches the purpose of character display by the scanning of control ranks; The present invention also provides a kind of manufacture method of this chip in addition, to overcome the deficiencies such as led chip luminosity adjusting difficulty that prior art exists.
Controlled power upside-down mounting array LED chip structure of the present invention is: the array LED chip is by a plurality of array element forming arrays, the p electrode layer of each row of wherein all array elements connects together, the n electrode layer of each row connects together, and it is luminous to control each array element separately like this; Described array element is that the Sapphire Substrate top covers n type resilient coating, n type semiconductor layer, active layer, p type semiconductor layer, transparent electrode layer, p electrode layer successively; The n electrode layer of each column array unit links together; And all n electrode layer and p electrode layer are coated by insulating barrier; P electrode above the p electrode layer window that insulating barrier coats connects metal level connects together the p electrode of each row.The exiting surface of Sapphire Substrate is a roughened surface, to improve light emission rate; Connect layer on surface of metal at the p electrode and also have passivation layer.The p electrode layer of chip adopts metals such as higher silver of light reflectivity or aluminium to increase the light reflection, and covers the transparent electrode layer of each array element fully.
Wherein, the led chip exiting surface is a Sapphire Substrate, adopts sapphire (Al 2O 3); And exiting surface is carried out organized surface roughening handle the formation roughened surface, to reduce light output surface, improve light emission rate to reflection of light, improve the luminous efficiency of LED.
Described n type semiconductor layer and p type semiconductor layer are to be made of GaN or GaAs or AlGaN semi-conducting material; Wherein the impurity that mixes of n type semiconductor layer is materials such as Si, and the impurity that the p type semiconductor layer is mixed is materials such as Mg; Active layer adopts the InGaN layer and the GaN layer of multilayer, forms multiple quantum well layer.
Led chip of the present invention is by the array element forming array that is mutually independent.But each column array unit n electrode layer links together; The material material of n electrode layer comprises Cu, Ti, Al, Ni or Au metal, adopts wherein single metal or combination metal; The p electrode layer adopts metal A g or the Al very high to visible reflectance, and covers the transparent electrode layer of each array element fully;
P electrode above the p electrode layer window that insulating barrier coats connects metal level connects together the p electrode of each row; The material that the p electrode connects metal level comprises Cu, Ti, Al, Ni or Au metal, adopts wherein single metal or combination metal.
Insulating barrier and passivation layer are by SiO x, SiN xOr SiO xN yConstitute Deng insulating material; Transparent electrode layer adopts metallic film Ni/Au or tin indium oxide (ITO) to make.
The manufacture method of controlled power upside-down mounting array LED chip of the present invention comprises following manufacturing step:
Step 1 is in the low-doped n type resilient coating of Sapphire Substrate growth, the n type semiconductor layer that regrowth is highly doped;
Step 2, the growth active layer is grown to the InGaN of individual layer, and perhaps alternating growth is the InGaN layer and the GaN layer in a plurality of cycles, forms multiple quantum well layer;
Step 3, growing p-type semiconductor layer on the basis of step 2;
Step 4, deposit transparent electrode layer and p electrode layer;
Step 5 is carried out photoetching and etching on the basis of step 4, expose the isolation channel of n type resilient coating and chip, for the deposition of n electrode is prepared;
Step 6, depositing metal layers, and carry out photoetching and etching, form the n electrode layer that each provisional capital connects together;
Step 7, depositing insulating layer, and carry out photoetching and etching, expose p electrode layer window, for the p electrode connection metal level of deposition p electrode layer window top is prepared; Simultaneously expose n electrode pad, connect for external circuit at the chip edge;
Step 8, deposition Cu, Ti, Al, Ni or Au metal adopt wherein single metal or combination metal, and carry out photoetching and etching, form p electrode connection metal level and the external pad of n electrode that each column array unit all links together, connect for external circuit;
Step 9, deposit passivation layer, and carry out photoetching and etching, and expose p electrode pad and n electrode pad, connect for external circuit;
Step 10 is carried out attenuate to Sapphire Substrate, and sapphire exiting surface is carried out organized roughened, forms roughened surface.
Step 1 adopts MOCVD(metallo-organic compound gas deposition to step 3) prepared, perhaps adopt the MBE(molecular beam epitaxy) the method preparation.
Step 5 adopts wet-etching technique, adopts ICP(to strengthen plasma etching) method or RIE(reactive ion etching) method, perhaps adopt the combination of these two kinds of methods.
Step 4, step 6 and step 7 adopt the method growth transparent electrode layer and the p electrode layer step 7 of magnetron sputtering or electron beam evaporation to adopt the PECVD(plasma-enhanced chemical vapor deposition) technology growth insulating barrier and passivation layer; Step 10 employing CMP(chemico-mechanical polishing) process equipment is with reducing thin of sapphire substrate.
Step 1, on Sapphire Substrate, adopt the MOCVD method n type GaN resilient coating of the low-doped Si of growth earlier, the n type GaN contact layer of the highly doped Si of regrowth; Promptly use the TMGa(trimethyl gallium), NH 3(ammonia) and silicon source SiH 4(silane) is at the n-GaN resilient coating of 570 ℃ of low-doped Si that growth 2 μ m are thick down; The n type GaN contact layer of the highly doped Si of regrowth 20nm;
Step 2, employing MOCVD method growth active layer.The InGaN layer in a plurality of cycles of alternating growth and GaN layer form Multiple Quantum Well-mqw layer.Detailed process is:
1, feed indium source TMIn(trimethyl indium) the thick InGaN of growth 3nm;
2, remove the indium source, feed silane (SiH 4) the thick n-GaN of growth 20nm;
3, repetitive process 1, more than 2 time just grow the InGaN/GaN Multiple Quantum Well;
Step 3, at MQW active layer top, adopt MOCVD method growing p-type semiconductor layer, promptly feed the TMGa(trimethyl gallium), NH 3(ammonia) and Cp 2Mg(two luxuriant magnesium), the thick p type semiconductor layer of growth 100nm;
Method with magnetron sputtering after step 4, process are cleaned deposits one deck ITO transparent conductive film as transparent electrode layer on the p type semiconductor layer, sputter-deposited Ag or Al metal form the p electrode layer on transparent electrode layer; The thickness of transparent electrode layer is 500nm, and the thickness of p electrode layer is 120nm;
Step 5, on the basis of step 4 resist coating, mask, etching is carried out in photoetching, exposes the isolation channel of n type resilient coating and chip, for the deposition of n electrode ready;
Step 6, usefulness magnetron sputtering deposition Cu/Au(copper/gold), the thickness of plated metal is 120nm; Form the n electrode layer, and carry out photoetching and etching, form the n electrode that each provisional capital connects together;
Step 7, employing PECVD(plasma-enhanced chemical vapor deposition) growth SiO 2Insulating barrier, and carry out photoetching and etching, expose the p electrode window through ray, for connecting metal level, the p electrode that further deposits p electrode layer window top prepares; Simultaneously expose n electrode pad, connect for external circuit at the chip edge;
Step 8, with magnetron sputtering deposition Cu/Au(copper/gold) wait the connection metal electrode layer of the p electrode of metal composition, this bed thickness 90-150 μ m, and carry out photoetching and etching, form p electrode connection metal and the external pad of n electrode that each column array unit all links together; Connect for external circuit;
Step 9, remove photoresist, adopt PECVD growth SiOx or SiNx passivation layer, promptly form the thick SiO of 80nm 2Passivation layer; And carry out photoetching and etching, and expose p electrode pad and n electrode pad, connect for external circuit;
Step 10, usefulness chemico-mechanical polishing (CMP) equipment are with the sapphire attenuate, be about to Sapphire Substrate and be thinned to 90 μ m～150 μ m by 350 μ m～450 μ m, and the method that adds ion etching with photoetching is carried out organized roughened to sapphire exiting surface, the formation roughened surface.
Can obtain a kind of upside-down mounting array-type LED chip of controlled power based on the manufacture method of above-mentioned steps, this chip is compared with traditional led chip, both can increase light-emitting area, whether array of controls unit luminous of the energising of the row and column of array that again can be by control chip, thereby power that can control chip reaches the purpose of control chip luminosity; Also can whether switch on, be used for character display by outside driven sweep circuit control chip row and column.
Adjust active layer structure (quantum well as a plurality of materials forms composite quantum well) and material component (adjust doping content and change emission wavelength) and can send out color of light multiple, this led chip category has also been contained in the present invention.
Above said content of the present invention, only provided and realized a kind of embodiment of the present invention, but chip structure in this scheme and the scheme and process conditions can change, this change does not break away from thought of the present invention and scope, and all changes that those skilled in the art oneself are understood should be included in the scope of the said claims.
Description of drawings
Fig. 1 is a process chart of the present invention;
Fig. 2 is sapphire Al 2O 3(0001) epitaxial growth n-GaN layer, n on the face substrate +The figure in the cross section behind-GaN layer, active layer, p-GaN layer, transparency electrode and the Ag/Al metal electrode;
The plane graph that obtains after Fig. 3 n region electrode photoetching and the etching;
Fig. 4 is the A-A sectional view of Fig. 3;
The plane graph of Fig. 5 for obtaining after the n region electrode etching;
Fig. 6 is the A-A sectional view of Fig. 5
Fig. 7 is SiO xOr the planar graph after the SiNx insulating barrier etching;
Fig. 8 is the A-A sectional view of Fig. 7;
Fig. 9 is p electrode district top deposition, photoetching are connected metal wire with p electrode after the etching a plane graph;
Figure 10 is the A-A sectional view of Fig. 8;
Figure 11 SiO xOr the planar graph after the SiNx passivation layer etching
Figure 12 is for carrying out the cross section figure that obtains after the organized roughened to the sapphire exiting surface;
Reference numeral:
The roughened surface of 1-Sapphire Substrate;
2-Sapphire Substrate;
3-n type resilient coating, i.e. n-GaN resilient coating;
4-(SiO xOr SiNx) insulating barrier;
5-n electrode layer;
6-n semiconductor layer, i.e. n +-GaN layer;
7-active layer;
8-p semiconductor layer, i.e. p-GaN layer;
9-transparent electrode layer;
10-p electrode layer;
11-p electrode connects metal level;
12-(SiO xOr SiNx) passivation layer.
Embodiment
Embodiments of the invention:, be that example illustrates chip structure of the present invention and manufacture method thereof with " from the luminous GaN base controlled power blue light upside-down mounting array-type LED chip of sapphire surface " at this.
Chip structure of the present invention is: the array LED chip is by a plurality of array element forming arrays, the p electrode layer 10 of each row of wherein all array elements connects together, the n electrode layer 5 of each row connects together, and it is luminous to control each array element separately like this; Described array element is that Sapphire Substrate 2 tops cover n type resilient coating 3, n type semiconductor layer 6, active layer 7, p type semiconductor layer 8, transparent electrode layer 9, p electrode layer 10 successively; The n electrode layer 5 of each column array unit links together; And all n electrode layer 5 and p electrode layer 10 are coated by insulating barrier 4; P electrode above p electrode layer 10 windows that insulating barrier 4 coats connects metal level 11 connects together the p electrode layer 10 of each row.The exiting surface of Sapphire Substrate 2 is a roughened surface 1, to improve light emission rate; Connect metal level 11 surfaces at the p electrode and also have passivation layer 12.The p electrode layer of chip adopts metals such as higher silver of light reflectivity or aluminium to increase the light reflection.
The gallium source is the TMGa(trimethyl gallium among the present invention), nitrogenous source is NH 3(ammonia), indium source are the TMIn(trimethyl indium), the silicon source is SiH 4(silane), magnesium source are Cp 2Mg(two luxuriant magnesium).
Below be the detailed methods of fabrication of this embodiment controlled power blue light upside-down mounting array-type LED chip structure, its flow process as schematically shown in Figure 1, it may further comprise the steps:
Step 1, on Sapphire Substrate 2, adopt the MOCVD method n type GaN resilient coating 3 of the low-doped Si of growth earlier, the n type GaN semiconductor layer 6 of the highly doped Si of regrowth; Promptly use the TMGa(trimethyl gallium), NH 3(ammonia) and silicon source SiH 4(silane) is at the n-GaN resilient coating 3 of 570 ℃ of low-doped Si that growth 2 μ m are thick down; The n type GaN semiconductor layer 6 of the highly doped Si of regrowth 20nm; As schematically shown in Figure 2.
Step 2, employing MOCVD method growth active layer 7.The InGaN layer in a plurality of cycles of alternating growth and GaN layer form Multiple Quantum Well-mqw layer.Detailed process is: the first, feed indium source TMIn(trimethyl indium) the thick InGaN of growth 3nm; The second, remove the indium source, feed silane (SiH 4) the thick n-GaN of growth 20nm; The 3rd, repetitive process first, second repeatedly, just grow the InGaN/GaN Multiple Quantum Well; As schematically shown in Figure 2
Step 3, at MQW active layer 7 tops, adopt MOCVD method growing p-type semiconductor layer 8, promptly feed the TMGa(trimethyl gallium), NH 3(ammonia) and Cp 2Mg(two luxuriant magnesium), the thick p type semiconductor layer 8 of growth 100nm;
Method with magnetron sputtering after step 4, process are cleaned deposits one deck ITO transparent conductive film as transparent electrode layer 9 on p type semiconductor layer 8, sputter-deposited Ag or Al metal form p electrode layer 10 on transparent electrode layer; The thickness of transparent electrode layer 9 is 500nm, and the thickness of p electrode layer 10 is 120nm;
Step 5, on the basis of step 4 resist coating, mask, etching is carried out in photoetching, exposes the isolation channel of n type resilient coating and chip, for the deposition of n electrode layer 5 is prepared; As shown in Figure 3, Figure 4;
Step 6, usefulness magnetron sputtering deposition Cu/Au(copper/gold), the thickness of plated metal is 120nm; Form n electrode layer 5, and carry out photoetching and etching, form the n electrode layer 5 that each provisional capital connects together; As shown in Figure 5 and Figure 6.
Step 7, employing PECVD(plasma-enhanced chemical vapor deposition) growth SiO 2Insulating barrier 4, and carry out photoetching and etching, expose p electrode layer 10 windows, for connecting metal level, the p electrode that further deposits p electrode layer 10 windows top prepares; Simultaneously expose n electrode pad, connect for external circuit at the chip edge; As Fig. 7, shown in Figure 8.
Step 8, on p electrode layer 10 with magnetron sputtering deposition Cu/Au(copper/gold) wait the connection metal electrode layer 11 of the p electrode of metal composition, this bed thickness 90-150 μ m, and carry out photoetching and etching, form p electrode connection metal and the external pad of n electrode that each column array unit all links together; Connect for external circuit; As Fig. 9, shown in Figure 10
Step 9, remove photoresist, adopt PECVD growth SiOx or SiNx passivation layer, promptly form the thick SiO of 80nm 2Passivation layer 12; And carry out photoetching and etching, and expose p electrode pad and n electrode pad, connect for external circuit;
Step 10, usefulness chemico-mechanical polishing (CMP) equipment are with Sapphire Substrate 2 attenuates, be about to Sapphire Substrate and be thinned to 90 μ m～150 μ m by 350 μ m～450 μ m, and the method that adds ion etching with photoetching is carried out organized roughened to sapphire exiting surface, formation roughened surface 1.
Led chip according to above-mentioned steps and technology are made obtains the upside-down mounting array-type LED chip than good quality.
Based on above-mentioned exemplary construction and manufacture method thereof, adjust active layer structure (quantum well as a plurality of materials forms composite quantum well) and material component (adjust doping content and change emission wavelength) and can send out color of light multiple, this led chip category has also been contained in the present invention.
Above said content of the present invention, only provided and realized a kind of embodiment of the present invention, but chip structure in this scheme and the scheme and process conditions can change, this change does not break away from thought of the present invention and scope, and all changes that those skilled in the art oneself are understood should be included in the described claim scope.

Claims (14)

1. controlled power upside-down mounting array LED chip is characterized in that: the array LED chip is by a plurality of array element forming arrays, and p electrode layer (10) of each row of wherein all array elements connects, and the n electrode layer (5) of each row connects; The structure of described each array element is that Sapphire Substrate (2) top covers n type resilient coating (3), n type semiconductor layer (6), active layer (7), p type semiconductor layer (8), transparent electrode layer (9), p electrode layer (10) successively; All n electrode layers (5) and p electrode layer (10) are coated by insulating barrier (4); Wherein the p electrode layer (10) of each row connects metal level (11) connection by the p electrode of p electrode layer (10) window top; Connect metal level (11) surface at the p electrode and also have passivation layer (12).
2. controlled power upside-down mounting array LED chip according to claim 1 is characterized in that: roughened surface (1) is handled the led chip exiting surface that forms for Sapphire Substrate (2) by surface roughening.
3. controlled power upside-down mounting array LED chip according to claim 1 is characterized in that: n type resilient coating (3), n type semiconductor layer (6) and p type semiconductor layer (8) are made of GaN, GaAs or AlGaN semi-conducting material; Wherein the impurity that mixes of n type layer is the Si material, and the impurity that p type layer mixes is the Mg material.
4. root controlled power upside-down mounting according to claim 1 array LED chip, it is characterized in that: active layer (7) is the InGaN of individual layer, or the InGaN layer of multilayer and GaN layer, forms multiple quantum well layer.
5. according to claim 1,2 or 3 described controlled power upside-down mounting array LED chips, it is characterized in that: led chip is by the array element forming array that is mutually independent, and the n electrode layer (5) of each column array unit connects; The material of n electrode layer (5) comprises Cu, Ti, Al, Ni or Au metal, adopts wherein single metal or combination metal.
6. according to claim 1,2 or 3 described controlled power upside-down mounting array LED chips, it is characterized in that: p electrode layer (10) adopts Ag or Al, and covers the transparent electrode layer (9) of each array element fully.
7. according to claim 1,2 or 3 described controlled power upside-down mounting array LED chips, it is characterized in that: the material that the p electrode connects metal level (11) comprises Cu, Ti, Al, Ni or Au metal, adopts wherein single metal or combination metal.
8. controlled power upside-down mounting array LED chip according to claim 1 is characterized in that: insulating barrier (4) and passivation layer (9) are by SiO x, SiN xOr SiO xN yInsulating material constitutes.
9. controlled power upside-down mounting array LED chip according to claim 1 is characterized in that: transparent electrode layer (9) adopts metallic film Ni/Au or tin indium oxide to make.
10. the manufacture method of a controlled power upside-down mounting array LED chip is characterized in that it comprises following manufacturing step:
Step 1 is in the low-doped n type resilient coating (3) of Sapphire Substrate growth, the n type semiconductor layer (6) that regrowth is highly doped;
Step 2, growth active layer (7) is grown to the InGaN of individual layer, and perhaps alternating growth is the InGaN layer and the GaN layer in a plurality of cycles, forms multiple quantum well layer;
Step 3, growing p-type semiconductor layer (8) on the basis of step 2;
Step 4, deposit transparent electrode layer (9) and p electrode layer (10);
Step 5 is carried out photoetching and etching on the basis of step 4, expose the isolation channel of n type resilient coating (3) and chip, for the deposition of n electrode is prepared;
Step 6, depositing metal layers, and carry out photoetching and etching, form the n electrode layer (5) that each provisional capital connects together;
Step 7, depositing insulating layer (4), and carry out photoetching and etching, expose p electrode layer (10) window, for the p electrode connection metal level (11) of deposition p electrode layer (10) window top is prepared; Expose n electrode pad simultaneously at the chip edge;
Step 8, plated metal comprise Cu, Ti, Al, Ni or Au metal, adopt wherein single metal or combination metal, and carry out photoetching and etching, form p electrode connection metal level (11) and the external pad of n electrode that each column array unit all links together;
Step 9, deposit passivation layer (12), and carry out photoetching and etching, expose p electrode pad and n electrode pad;
Step 10 is carried out attenuate to Sapphire Substrate (2), and sapphire exiting surface is carried out organized roughened, forms roughened surface (1).
11. the manufacture method of controlled power upside-down mounting array LED chip according to claim 10, it is characterized in that: in the above-mentioned manufacturing step, step 1 can exchange sedimentary sequence to step 3, i.e. earlier growing p-type semiconductor layer (8) and active layer (7) on substrate are at last in active layer grown on top n type semiconductor layer (6).
12. manufacture method according to claim 10 or 11 described controlled power upside-down mounting array LED chips, it is characterized in that: step 1 adopts the preparation of " MOCVD " metallo-organic compound vapor deposition process to step 3, perhaps adopts the preparation of " MBE " molecular beam epitaxial method.
13. the manufacture method of controlled power upside-down mounting array LED chip according to claim 9, it is characterized in that: step 5 adopts wet-etching technique, adopt " ICP " to strengthen plasma etching method or " RIE " reactive ion etching method, perhaps adopt the combination of these two kinds of methods.
14. the manufacture method of controlled power upside-down mounting array LED chip according to claim 9 is characterized in that: step 4, step 6 and step 7 adopt method growth transparent electrode layer (9), p electrode layer (10), the n electrode (5) of magnetron sputtering or electron beam evaporation to be connected metal level (11) with the p electrode; Step 7 adopts " PECVD " plasma-enhanced chemical vapor deposition growth insulating barrier (4) and passivation layer (12); Step 10 adopts chemico-mechanical polishing " CMP " equipment with Sapphire Substrate (2) attenuate.
CN2011102147401A 2011-07-29 2011-07-29 Controllable power flip array light emitting diode (LED) chip and manufacturing method thereof Pending CN102244087A (en)

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Application publication date: 20111116