CN102244087A - Controllable power flip array light emitting diode (LED) chip and manufacturing method thereof - Google Patents

Controllable power flip array light emitting diode (LED) chip and manufacturing method thereof Download PDF

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CN102244087A
CN102244087A CN2011102147401A CN201110214740A CN102244087A CN 102244087 A CN102244087 A CN 102244087A CN 2011102147401 A CN2011102147401 A CN 2011102147401A CN 201110214740 A CN201110214740 A CN 201110214740A CN 102244087 A CN102244087 A CN 102244087A
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step
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metal
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张荣芬
李绪诚
杨利忠
许铖
邓朝勇
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贵州大学
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Abstract

The invention discloses a controllable power flip array light emitting diode (LED) chip and a manufacturing method thereof. The controllable power flip array LED chip is an array consisting of a plurality of array units, wherein p electrode layers (10) of each row of all the array units are connected with one another and n electrode layers (5) of each column are connected with one another; in each array unit, an n-type buffer layer (3), an n-type semiconductor layer (6), an active layer (7), a p-type semiconductor layer (8), a transparent electrode layer (9) and the p electrode layer (10) are covered on a sapphire substrate (2); all the n electrode layers (5) and all the p electrode layers (10) are wrapped by insulation layers (4); the p electrode layers (10) of each row are connected with one another through p electrode connection metal layers (11) arranged above windows of the p electrode layers (10); and passivation layers (12) are arranged on the surfaces of the p electrode connection metal layers (11).

Description

可控功率倒装阵列LED芯片及其制造方法 Controllable power flip chip LED array and manufacturing method thereof

技术领域 FIELD

[0001] 本发明涉及一种倒装阵列LED芯片及其制造方法,尤其涉及一种包括多量子阱有源区的GaN基可控倒装阵列蓝光LED芯片结构及其制造方法。 [0001] The present invention relates to a flip-chip LED array and its manufacturing method, particularly to a flip-chip structure blue LED array and method of manufacturing a GaN-based multi-quantum well active region comprises controllable.

背景技术 Background technique

[0002] 白光LED具有亮度高、节能环保等优点,已经成为最有潜力的照明光源之一。 [0002] The white LED with high brightness, energy saving, etc., it has become one of the most promising sources of illumination. 白光LED的能耗仅为白炽灯的1/8,荧光灯的1/2,其寿命可长达10万小时。 Incandescent white LED power consumption is only 1/8, 1/2 of the fluorescent lamp, which can be up to 100,000 hours life. 这对普通家庭明来说可谓“一劳永逸”,同时还可实现无汞化,回收容易等优点,对环境保护和节约能源具有重 This is described as "once" out for the ordinary family, but can also mercury-free, easy recovery, etc., having a weight of environmental protection and energy conservation

要意义。 To sense.

[0003] 目前制备大功率白光LED的方法主要是在蓝色或近紫外LED芯片上涂覆黄色荧光粉,通过混色得到白光。 [0003] The present process for preparing high-power white LED is mainly yellow phosphor is coated on a blue or near-ultraviolet LED chip, a white light obtained by color mixing. 这种通过蓝光LED的得到白光的方法,构造简单、成本低廉、技术成熟度高,因此运用广泛。 This white light obtained by the blue LED method, simple structure, low cost, high technology is mature, so the use of a wide range. 大多数5W以上的大功率白光LED是由大功率的蓝光LED芯片制成的。 Most of the above power 5W high-power white LED is a blue LED chip made. 所以制造大功率蓝光LED芯片是制作大功率白光LED的基础。 The manufacturing of high-power blue LED chip is made on the basis of high-power white LED.

[0004] 目前,调节发光亮度的LED主要是通过以下几种方式:第一、单个LED芯片主要是控通过LED芯片的电流来调节发光亮度;第二、多个LED芯片的组合通过控制多个LED芯片的开关来调节发光亮度。 [0004] Currently, adjust brightness of the LED light emission mainly in the following ways: First, a single LED chip is mainly controlled to regulate the light emission brightness by a current of the LED chip; a combination of a second, by controlling a plurality of LED chips of the plurality of LED chip emission luminance adjusting switch. 但是由于每个LED芯片可能不是同一批次生产的电学性能和光学性能会有不同,通过以上的控制方法连接设计和电源驱动,组合芯片发光的协调性、一致性较差。 However, since each LED chip production run may not be the same electrical and optical properties will be different, by the above method of controlling the driving power and connection design, coordination of the light emitting chip composition, less consistent.

[0005] 目前单色显示屏在户外广告和小型移动数码设备上都有应用,所以发展LED单色显示屏也有很广的应用前景。 [0005] Currently monochrome display has applications in outdoor advertising and small mobile digital devices, so the development of LED monochrome display also has a very broad application prospects.

发明内容 SUMMARY

[0006] 本发明要解决的技术问题是,提供一种可控功率倒装阵列LED芯片,该芯片能有效调节大功率蓝光LED倒装芯片的发光亮度,还可作为单色显示屏使用,通过控制行列的扫描达到显示字符的目的;此外本发明还提供一种该芯片的制造方法,以克服现有技术存在的LED芯片发光亮度调节困难等不足。 [0006] The present invention is to solve the technical problem, to provide a controllable power LED array flip-chip, which can regulate the light emission brightness of the high power blue LED flip chip, it may be used as a monochrome display, by controlling the scan line of the character display purposes; the invention also provides a method of manufacturing the chip, in order to overcome the LED chip in the prior art is insufficient brightness adjustment difficulties.

[0007] 本发明的可控功率倒装阵列LED芯片结构为:阵列LED芯片由多个阵列单元构成阵列,其中所有的阵列单元每一行的P电极层连接到一起,每一列的η电极层连接到一起, 这样可以单独控制每个阵列单元发光;所述阵列单元是蓝宝石衬底上方依次覆盖η型缓冲层、η型半导体层、有源层、ρ型半导体层、透明电极层、ρ电极层;每一列阵列单元的η电极层连接在一起;并且全部η电极层和P电极层由绝缘层包覆;在绝缘层包覆的P电极层窗口上方的P电极连接金属层使每一行的P电极连接到一起。 [0007] a controllable power LED array flip-chip structure of the present invention is: an array of LED chips by a plurality of array elements constituting an array, P electrode layer, wherein each row of the array of all the cells are connected together, η electrode layer is connected to each column together, which can be controlled separately for each light emitting element array; the array unit is in turn covered over a sapphire substrate type buffer layer [eta], [eta] -type semiconductor layer, an active layer, a [rho] -type semiconductor layer, a transparent electrode layer, an electrode layer [rho] ; [eta] an electrode layer of each column of the array cells are connected together; [eta] and all the P-electrode layer and the electrode layer covering the insulating layer; P P electrode connection metal layer over the electrode layer, the insulating layer covering the window in each row of P electrodes are connected together. 蓝宝石衬底的出光面为粗糙化表面,以提高出光率;在P电极连接金属层表面还有钝化层。 The surface of the sapphire substrate is a surface roughened to improve light extraction efficiency; P-electrode connection surface of the metal layer as well as a passivation layer. 芯片的P电极层采用光反射率较高的银或铝等金属来增加光反射,并且完全覆盖每一个阵列单元的透明电极层。 P-electrode layer of the chip using a high light reflectance such as silver or aluminum to increase the light reflection, and the transparent electrode layer completely covers each of the array elements.

[0008] 其中,LED芯片出光面为蓝宝石衬底,采用蓝宝石(Al2O3);并对出光面进行有组织的表面粗糙化处理形成粗糙化表面,以减少出光表面对光的反射,提高出光率,改善LED的发光效率。 [0008] wherein, LED chips as the light emitting surface of the sapphire substrate, sapphire (of Al2O3); and the smooth surface roughening an organized form roughened surface treatment, to reduce the surface reflection light of light, to improve the light extraction efficiency, improve luminous efficiency of the LED.

[0009] 所述的η型半导体层和ρ型半导体层是由GaN、或GaAs、或AlGaN半导体材料构成; 其中η型半导体层掺入的杂质是Si等材料,ρ型半导体层掺入的杂质是Mg等材料;有源层采用多层的InGaN层和GaN层,形成多量子阱层。 [0009], wherein η and [rho] -type semiconductor layer-type semiconductor layer is formed of GaN, or GaAs, or AlGaN semiconductor material; wherein η-type semiconductor layer is doped impurity is Si or the like material, ρ-type semiconductor layer is doped with an impurity It is Mg and other materials; an active layer of multi-layer InGaN layer and the GaN layer, forming multiple quantum well layer.

[0010] 本发明的LED芯片由彼此相互独立的阵列单元构成阵列。 [0010] LED array chip of the present invention is constituted by the array elements independent from each other. 但是每一列阵列单元η 电极层是连接在一起的;η电极层的材料材料包括Cu、Ti、Al、M或Au金属,采用其中的单一金属或组合金属;P电极层采用对可见光反射率很高的金属^Vg或Al,并且完全覆盖每一个阵列单元的透明电极层; However, each column of array elements η electrode layers are connected together; η electrode material layer comprises a material of Cu, Ti, Al, M, or Au metal, wherein a single metal or a combination of metal; P electrode layer using visible light reflectance is ^ Vg high metal or Al, and completely covers the transparent electrode layer of each array unit;

在绝缘层包覆的P电极层窗口上方的P电极连接金属层使每一行的P电极连接到一起;P电极连接金属层的材料包括Cu、Ti、Al、Ni或Au金属,采用其中的单一金属或组合金jM ο P P electrode connected to the metal layer in the window over the electrode layer so that the insulating layer covering the electrode P of each row are connected together; electrode connection material P comprises a metal layer Cu, Ti, Al, Ni, or Au metal, wherein the single metallic gold or a combination jM ο

[0011] 绝缘层和钝化层是由SiOx、SiNx或SiOxNy等绝缘材料构成;透明电极层采用金属薄膜Ni/Au或氧化铟锡(ITO)制作。 [0011] The insulating layer and the passivation layer is made like SiOx, SiNx, or SiOxNy insulating material; a transparent electrode layer using a metal thin film Ni / Au or indium tin oxide (ITO) production.

[0012] 本发明的可控功率倒装阵列LED芯片的制造方法,包括以下制造步骤: [0012] The controllable power flip-chip LED array manufactured according to the present invention, comprises the following manufacturing steps:

步骤一,在蓝宝石衬底生长低掺杂的η型缓冲层,再生长高掺杂的η型半导体层; 步骤二,生长有源层,生长为单层的hGaN,或者交替生长为多个周期的hGaN层和GaN 层,形成多量子阱层; A step, a sapphire substrate grown low doped η-type buffer layer, a semiconductor layer regrown η-type highly doped; two step, growing an active layer grown as monolayer hGaN, or alternately a plurality of cycles of growth the hGaN layer and the GaN layer, forming multiple quantum well layer;

步骤三,在步骤二的基础上生长P型半导体层; 步骤四,沉积透明电极层和P电极层; Step three, the growth of P-type semiconductor layer on the basis of step II; Step 4 P depositing a transparent electrode layer and an electrode layer;

步骤五,在步骤四的基础上进行光刻和刻蚀,露出η型缓冲层和芯片的隔离槽,为η电极的沉积做准备; Step five, four step carried out on the basis of photolithography and etching, the exposed η-type buffer layer and the chip separation grooves, to prepare for the deposition of the electrode of η;

步骤六,沉积金属层,并进行光刻和刻蚀,形成每一行都连接到一起的η电极层; 步骤七,沉积绝缘层,并进行光刻和刻蚀,露出P电极层窗口,为沉积P电极层窗口上方的P电极连接金属层做准备;同时在芯片边沿露出η电极pad,以供外电路连接; Step six, depositing a metal layer, and photolithography and etching, forming each row are connected together η electrode layer; Step seven, depositing an insulating layer, and photolithography and etching, to expose the electrode P window layer, to deposit P-electrode connecting metal electrode layer over the window layer to prepare P; η exposed edge while the chip electrode pad, for connecting an external circuit;

步骤八,沉积Cu、Ti、Al、Ni或Au金属,采用其中的单一金属或组合金属,并进行光刻和刻蚀,形成每一列阵列单元都连接在一起的P电极连接金属层和η电极外接pad,以供外电路连接; Step eight, depositing Cu, Ti, Al, Ni, or Au metal, wherein a single metal or a combination of metal and photolithography and etching to form an electrode P of each column of the array cells are connected together and connected to the metal layer electrode η an external pad, for connecting an external circuit;

步骤九,沉积钝化层,并进行光刻和刻蚀,露出P电极pad和η电极pad,以供外电路连 Step 9, the passivation layer deposition, and photolithography and etching to expose the P electrode pad and the electrode pad η, for the external circuit is connected

接; Access;

步骤十,对蓝宝石衬底进行减薄,并对蓝宝石的出光面进行有组织的粗糙化处理,形成粗糙化表面。 Step 10, on the sapphire substrate is thinned, and the sapphire surface roughening treatment in organized form roughened surface.

[0013] 步骤一到步骤三采用MOCVD (金属有机化合物汽相沉积)工艺制备,或者采用MBE (分子束外延)方法制备。 [0013] Step a three step preparation of the MOCVD (metal organic compound vapor deposition) preparation process, or to use MBE (molecular beam epitaxy) method is employed.

[0014] 步骤五采用湿刻工艺,采用ICP (增强等离子刻蚀)方法、或者RIE (反应离子刻蚀) 方法,或者采用该两种方法的组合。 [0014] Step Five wet etching process using ICP (plasma-enhanced etching) method, or RIE (reactive ion etching) method, or using a combination of the two methods.

[0015] 步骤四、步骤六和步骤七采用磁控溅射或电子束蒸发的方法生长透明电极层和ρ 电极层步骤七采用PECVD (等离子增强化学汽相沉积)工艺生长绝缘层和钝化层;步骤十采用CMP (化学机械抛光)工艺设备将蓝宝石衬底减薄。 [0015] Step four, six and step seven step magnetron sputtering method or electron beam evaporation growth ρ transparent electrode layer and the electrode layer using a PECVD step seven (plasma enhanced chemical vapor deposition) process, the insulating layer and the passivation layer grown ; step 10 using a CMP (chemical mechanical polishing) process equipment thinned sapphire substrate.

[0016] 步骤一、在蓝宝石衬底上采用MOCVD方法先生长低掺杂Si的η型GaN缓冲层,再生长高掺杂Si的η型GaN接触层;即用TMGa (三甲基镓)、NH3 (氨)和硅源SiH4 (硅烷)在570°C下生长2 μ m厚的低掺杂Si的n-GaN缓冲层;再生长20nm的高掺杂Si的η型GaN接触层; [0016] Step a, on a sapphire substrate using MOCVD method Mr. long low Si-doped GaN buffer layer η-type, η-type regrown highly doped GaN contact layer made of Si; i.e. using of TMGa (trimethyl gallium), lower the NH3 (ammonia) and a silicon source of SiH4 (silane) 2 μ m thick is grown at 570 ° C Si-doped n-GaN buffer layer; 20nm high regrown η doped Si-type GaN contact layer;

步骤二、采用MOCVD方法生长有源层。 Step two, the MOCVD method for growing the active layer. 交替生长多个周期的InGaN层和GaN层,形成多量子讲一MQW层。 InGaN layer and the GaN layer alternately grown plurality of cycles to form a multi-quantum speak MQW layer. 具体过程为: Specific process is:

1、通入铟源TMh (三甲基铟)生长3nm厚的InGaN ; 1, into an indium source TMh of (trimethylindium) growing the InGaN 3nm thick;

2、去掉铟源,通入硅烷(SiH4)生长20nm厚的n-GaN ; 2, the indium source is removed, into silane (SiH4) grown 20nm thick n-GaN;

3、重复过程1、2多次,就生长出InGaN/GaN多量子阱; 3, the process is repeated 2 more times to grow the InGaN / GaN multi-quantum well;

步骤三、在MQW有源层顶部,采用MOCVD方法生长ρ型半导体层,即通入TMGa (三甲基镓)、NH3 (氨)和Cp2Mg (二茂镁),生长IOOnm厚的ρ型半导体层; Step three, MQW active layer on top, using the MOCVD method for growing ρ-type semiconductor layer, i.e. into of TMGa (trimethyl gallium), the NH3 (ammonia) and Cp2Mg (cyclopentadienyl magnesium), growth IOOnm type semiconductor layer thickness ρ ;

步骤四、经过清洗之后用磁控溅射的方法在P型半导体层上沉积一层ITO透明导电薄膜作为透明电极层,在透明电极层上溅镀沉积Ag或Al金属形成ρ电极层;透明电极层的厚度为500nm,ρ电极层的厚度为120nm ; Step four, after washing with a magnetron sputtering method of depositing a layer of ITO transparent conductive film on the P-type semiconductor layer as a transparent electrode layer on the transparent electrode layer of Ag or Al is deposited by sputtering a metal electrode layer formed ρ; a transparent electrode layer thickness of 500nm, the thickness of the electrode layer was 120 nm ρ;

步骤五、在步骤四的基础上涂光刻胶,掩膜,光刻,进行刻蚀,露出η型缓冲层和芯片的隔离槽,为η电极的沉积做好准备; Step five, four coating step on the basis of the photoresist mask, photolithography, etching, η-type buffer layer is exposed and the chip separation grooves, to prepare for the deposition of the electrode of η;

步骤六、用磁控溅射沉积Cu/Au (铜/金),沉积金属的厚度为120nm ;形成η电极层,并进行光刻和刻蚀,形成每一行都连接到一起的η电极; Step six, with magnetron sputtering Cu / Au (Cu / Au), thickness of the deposited metal is 120 nm; η electrode forming layer, and photolithography and etching, forming each row electrode η connected together;

步骤七、采用PECVD (等离子增强化学汽相沉积)生长S^2绝缘层,并进行光刻和刻蚀, 露出P电极窗口,为进一步沉积P电极层窗口上方的P电极连接金属层做准备;同时在芯片边沿露出η电极pad,以供外电路连接; Step seven, using a PECVD (plasma enhanced chemical vapor deposition) growth of S ^ 2 insulating layer, and photolithography and etching to expose the P electrode window, to make a P-electrode connection metal layer is further deposited over the electrode layer P window prepared; η chip edge is exposed while the electrode pad, for connecting an external circuit;

步骤八、用磁控溅射沉积Cu/Au (铜/金)等金属组成的ρ电极的连接金属电极层,该层厚90-150 μ m,并进行光刻和刻蚀,形成每一列阵列单元都连接在一起的ρ电极连接金属和η电极外接pad ;以供外电路连接; Step 8 connected to the metal electrode layer is deposited by magnetron sputtering Cu / Au (Cu / Au) composed of a metal such as ρ electrode, the layer thickness of 90-150 μ m, and photolithography and etching, are formed in each column of the array units are connected together and the connecting metal electrode η ρ external PAD electrode; for external circuit connection;

步骤九、除去光刻胶,采用PECVD生长SiOx或SiNx钝化层,即形成80nm厚的SW2钝化层;并进行光刻和刻蚀,露出P电极pad和η电极pad,以供外电路连接; Step 9, the resist is removed, grown by PECVD SiOx or SiNx passivation layer, i.e. a thickness of 80nm formed SW2 passivation layer; and photolithography and etching to expose the P electrode pad and the electrode pad η, for external circuit connection ;

步骤十、用化学机械抛光(CMP)设备将蓝宝石减薄,即将蓝宝石衬底由350μπι〜 450 μ m减薄至90 μ m〜150 μ m,并用光刻加离子刻蚀的方法对蓝宝石的出光面进行有组织的粗糙化处理,形成粗糙化表面。 Step 10, chemical mechanical polishing (CMP) apparatus sapphire thinned, thinning the sapphire substrate is about 450 [mu] m to 350μπι~ 90 μ m~150 μ m, by photolithography and etching method, and an ion of the sapphire light an organized surface roughening treatment, a roughened surface is formed.

[0017] 基于上述步骤的制造方法可以得到一种可控功率的倒装阵列式LED芯片,该芯片与传统LED芯片相比,既可以增大发光面积,又能够通过控制芯片的阵列的行和列的通电与否控制阵列单元的发光,从而可以控制芯片的功率,达到控制芯片发光亮度的目的;也可以通过外部的驱动扫描电路控制芯片行和列通电与否,用来显示字符。 [0017] The power can be controlled to obtain a flip chip type LED array manufacturing method based on the above-described steps, the chip is compared with the conventional LED chip, the light emitting area may be increased, but also to the control line through the array chip and controlling the energization or not a light emitting array unit columns, which can control the power of the chip, the chip to control the emission luminance of the object; may be by an external driving scanning circuit controls whether or not power chip in rows and columns, for displaying the character.

[0018] 调整有源层结构(如多个材料的量子阱形成复合量子阱)及材料组分(调整掺杂浓度改变发光波长)可以发多种颜色光,本发明也涵盖了这一LED芯片范畴。 [0018] Adjust the active layer structure (e.g., a plurality of quantum wells formed in the composite material of the quantum well) and the material component (dopant concentration adjustment to change the light emission wavelength) can send a variety of colors of light, the present invention also covers the LED chip category.

[0019] 本发明以上所述内容,仅给出了实现本发明的一种实施方案,但此方案和方案中的芯片结构以及工艺条件可以改变的,这种改变不脱离本发明的思想及范围,对本领域人员自己明了的所有变更应当包含在所述权利要求范围内。 [0019] The present invention described above content, is given only to achieve an embodiment of the present invention, but the chip structure and the process conditions of this embodiment and the embodiment can be changed, such changes without departing from the spirit and scope of the present invention All changes to their apparent to those skilled be embraced within the scope of the claims.

附图说明[0020] 图1为本发明的工艺流程图; BRIEF DESCRIPTION process flow diagram [0020] Figure 1 of the present invention;

图2为蓝宝石Al2O3 (0001)面衬底上外延生长n-GaN层、Ii+-GaN层、有源层、p-GaN层、 透明电极和Ag/Al金属电极后的截面的图; 图3 η区电极光刻和刻蚀后得到的平面图; 图4为图3的AA截面图; 图5为η区电极刻蚀后得到的平面图; 图6为图5的AA截面图图7为SiOx或SiNx绝缘层刻蚀后的平面图形; 图8为图7的AA截面图; FIG 2 is a substrate layer epitaxially grown n-GaN sapphire Al2O3 (0001) plane, FIG Ii + -GaN layer, active layer, p-GaN layer, a transparent electrode and the rear section of the Ag / Al metal electrode; FIG. 3 η region electrode obtained after photolithography and etching plan view; FIG. 4 is a sectional view AA of FIG. 3; FIG. 5 is a plan view of the electrode obtained etching region η; FIG. 6 is a sectional view AA of FIG. 5 FIG. 7 is a SiOx or SiNx graphics plane after etching the insulating layer; FIG. 8 is a sectional view AA of Figure 7;

图9为ρ电极区上方沉积、光刻和刻蚀后ρ电极连接金属线的平面图; 图10为图8的AA截面图; 图11 SiOx或SiNx钝化层刻蚀后的平面图形 FIG 9 is a plan view ρ is deposited over the electrode regions, photolithography and etching ρ electrode connecting metal lines; FIG. 10 is a sectional view AA of FIG. 8; FIG planar pattern after 11 SiOx or SiNx passivation layer etching

图12为对蓝宝石出光面进行有组织的粗糙化处理后的得到的截面图形; 附图标记: FIG 12 is a cross section of the pattern obtained after the sapphire surface roughening treatment in organized; reference numerals:

1一蓝宝石衬底的粗糙化表面; A roughened surface of a sapphire substrate;

2—蓝宝石衬底; 2- sapphire substrate;

3—η型缓冲层,即n-GaN缓冲层; 3-η-type buffer layer, i.e. n-GaN buffer layer;

4— (SiOx 或SiNx)绝缘层; 4- (SiOx or SiNx) insulating layer;

5—η电极层; 5-η electrode layer;

6— η半导体层,即Ii+-GaN层; 6- η semiconductor layer, i.e., Ii + -GaN layer;

7—有源层; 7- active layer;

8— ρ半导体层,即P-GaN层; 9一透明电极层; 8- ρ semiconductor layer, i.e., P-GaN layer; a transparent electrode layer 9;

10—ρ电极层; 10-ρ electrode layer;

11—P电极连接金属层; 11-P connected to the metal electrode layer;

12— (SiOx 或SiNx)钝化层。 12- (SiOx or SiNx) passivation layer.

具体实施方式 Detailed ways

[0021] 本发明的实施例:在此,以“从蓝宝石表面发光的GaN基可控功率蓝光倒装阵列式LED芯片”为例来说明本发明的芯片结构及其制造方法。 Example [0021] the present invention: Here, "the light emitting surface of the GaN from the sapphire substrate controllable power blue LED array flip-chip" chip structure will be described as an example and the manufacturing method of the present invention.

[0022] 本发明的芯片结构为:阵列LED芯片是由多个阵列单元构成阵列,其中所有的阵列单元每一行的P电极层10连接到一起,每一列的η电极层5连接到一起,这样可以单独控制每个阵列单元发光;所述阵列单元是蓝宝石衬底2上方依次覆盖η型缓冲层3、η型半导体层6、有源层7、ρ型半导体层8、透明电极层9、ρ电极层10 ;每一列阵列单元的η电极层5连接在一起;并且全部η电极层5和ρ电极层10由绝缘层4包覆;在绝缘层4包覆的P电极层10窗口上方的ρ电极连接金属层11使每一行的ρ电极层10连接到一起。 [0022] The chip structure of the present invention is: an array of LED array chips are constituted by a plurality of array elements, P electrode layer, wherein all of the array elements 10 in each row are connected together, [eta] of each column electrode layers 5 are connected together, so each light emitting unit may be controlled separately array; said array elements over a sapphire substrate 2 is sequentially covered with [eta]-type buffer layer 3, η-type semiconductor layer 6, active layer 7, ρ-type semiconductor layer 8, the transparent electrode layer 9, ρ electrode layer 10; [eta] of each column of the array electrode layer 5 units are linked together; [eta] and the entire electrode layer 510 and the cladding layer by an insulating layer [rho] electrode 4; ρ coated over the insulating layer 4 P electrode layer 10 of the window an electrode layer connected to the metal electrode 11 causes ρ layer 10 is connected to each row together. 蓝宝石衬底2的出光面为粗糙化表面1,以提高出光率;在ρ电极连接金属层11表面还有钝化层12。 The surface of the sapphire substrate 2 is a roughened surface, to improve the light extraction efficiency; ρ electrode connected to the surface of the metal layer 11 as well as a passivation layer 12. 芯片的ρ电极层采用光反射率较高的银或铝等金属来增加光反射。 Ρ chip electrode layer using a high light reflectance such as silver or aluminum to increase the light reflection.

[0023] 本发明中镓源为TMGa (三甲基镓),氮源为NH3 (氨),铟源为TMh (三甲基铟),硅源为SiH4 (硅烷),镁源为Cp2Mg (二茂镁)。 [0023] The present invention is a gallium source of TMGa (trimethyl gallium), the NH3 as a nitrogen source (ammonia), an indium source TMh of (trimethyl indium), the silicon source is of SiH4 (silane), the magnesium source is Cp2Mg (two Mao magnesium).

[0024] 以下是该实施例可控功率蓝光倒装阵列式LED芯片结构的详细制造方法,其流程如图1所示意,它包括以下步骤: [0024] The following is a detailed embodiment of a method for producing a controllable power blue LED array flip chip structure of the embodiment, the process illustrated in FIG. 1, comprising the steps of:

步骤一、在蓝宝石衬底2上采用MOCVD方法先生长低掺杂Si的η型GaN缓冲层3,再生长高掺杂Si的η型GaN半导体层6 ;即用TMGa (三甲基镓)、ΝΗ3 (氨)和硅源SiH4 (硅烷)在570°C下生长2 μ m厚的低掺杂Si的n-GaN缓冲层3 ;再生长20nm的高掺杂Si的η型GaN 半导体层6;如图2所示意。 A step, on a sapphire substrate using 2 MOCVD method Mr. long low Si-doped GaN buffer layer 3 η-type, the regrown Si highly doped η-type GaN semiconductor layer 6; ready to use of TMGa (trimethyl gallium), low ΝΗ3 (ammonia) and a silicon source of SiH4 (silane) 2 μ m thick is grown at 570 ° C Si-doped n-GaN buffer layer 3; 20nm high regrown Si-doped GaN η-type semiconductor layer 6; 2 schematically in FIG.

[0025] 步骤二、采用MOCVD方法生长有源层7。 [0025] Step two, the MOCVD method for growing the active layer 7. 交替生长多个周期的InGaN层和GaN层,形成多量子讲一MQW层。 InGaN layer and the GaN layer alternately grown plurality of cycles to form a multi-quantum speak MQW layer. 具体过程为:第一,通入铟源TMIn (三甲基铟)生长3nm厚的InGaN; 第二,去掉铟源,通入硅烷(SiH4)生长20nm厚的n-GaN ;第三,重复过程第一、第二多次,就生长出InGaN/GaN多量子阱;如图2所示意 Specific process: first, into the indium source of TMIn (trimethylindium) growing the InGaN 3nm thick; the second, the indium source is removed, into silane (SiH4) grown 20nm thick n-GaN; Third, the process is repeated a first, a second plurality of times, it is grown InGaN / GaN multiple quantum wells; 2 schematically in FIG.

步骤三、在MQW有源层7顶部,采用MOCVD方法生长ρ型半导体层8,即通入TMGa (三甲基镓)、NH3 (氨)和Cp2Mg (二茂镁),生长IOOnm厚的ρ型半导体层8 ; Step three, MQW active layer 7 on top, using the MOCVD method for growing ρ-type semiconductor layer 8, i.e., into of TMGa (trimethyl gallium), the NH3 (ammonia) and Cp2Mg (cyclopentadienyl magnesium), growth type IOOnm thick ρ The semiconductor layer 8;

步骤四、经过清洗之后用磁控溅射的方法在P型半导体层8上沉积一层ITO透明导电薄膜作为透明电极层9,在透明电极层上溅镀沉积Ag或Al金属形成ρ电极层10 ;透明电极层9的厚度为500nm,ρ电极层10的厚度为120nm ; Step four, after washing with a magnetron sputtering method of depositing a layer of ITO transparent conductive film on the P-type semiconductor layer 8 as the transparent electrode layer 9, on the transparent electrode layer sputter deposition of Ag or Al metal electrode layer 10 is formed ρ ; thickness of the transparent electrode layer 9 is 500nm, the thickness of the electrode layer 10 is ρ 120 nm;

步骤五、在步骤四的基础上涂光刻胶,掩膜,光刻,进行刻蚀,露出η型缓冲层和芯片的隔离槽,为η电极层5的沉积做准备;如图3、图4所示; Step five, four coating step on the basis of the photoresist mask, photolithography, etching, η-type buffer layer is exposed and the chip separation grooves, η is the electrode layer 5 is deposited to prepare; FIG. 3, FIG. 4;

步骤六、用磁控溅射沉积Cu/Au (铜/金),沉积金属的厚度为120nm ;形成η电极层5, 并进行光刻和刻蚀,形成每一行都连接到一起的η电极层5 ;如图5和图6所示。 Step six, with magnetron sputtering Cu / Au (Cu / Au), thickness of the deposited metal is 120 nm; η electrode layer 5 is formed, and photolithography and etching to form each row connected to the electrode layer together η 5; FIG. 5 and 6 as shown in FIG.

[0026] 步骤七、采用PECVD (等离子增强化学汽相沉积)生长SW2绝缘层4,并进行光刻和刻蚀,露出P电极层10窗口,为进一步沉积P电极层10窗口上方的P电极连接金属层做准备;同时在芯片边沿露出η电极pad,以供外电路连接;如图7、图8所示。 [0026] Step seven, using a PECVD (plasma enhanced chemical vapor deposition) growth SW2 insulating layer 4, and photolithography and etching to expose the electrode layer 10 a window P, P P electrode connected to the electrode layer is further deposited over the window 10 preparing a metal layer; while its outer edge is exposed η PAD electrode, for connecting an external circuit; FIG. 7, FIG. 8.

[0027] 步骤八、在ρ电极层10上用磁控溅射沉积Cu/Au (铜/金)等金属组成的ρ电极的连接金属电极层11,该层厚90-150 μ m,并进行光刻和刻蚀,形成每一列阵列单元都连接在一起的P电极连接金属和η电极外接pad ;以供外电路连接;如图9、图10所示 [0027] Step 8 connected to the metal electrodes deposited ρ Cu / Au (Cu / Au) composed of a metal such as magnetron sputtering electrode layer 11, the layer thickness of 90-150 μ m on the electrode layer 10 ρ, and photolithography and etching, and a P electrode is formed of metal connected to an external electrode pad η array elements in each column are connected together; for external circuit connection; 9, 10 shown in FIG.

步骤九、除去光刻胶,采用PECVD生长SiOx或SiNx钝化层,即形成80nm厚的SW2钝化层12 ;并进行光刻和刻蚀,露出ρ电极pad和η电极pad,以供外电路连接; Step 9, the resist is removed, grown by PECVD SiOx or SiNx passivation layer, i.e. a thickness of 80nm is formed a passivation layer 12 SW2; and photolithography and etching to expose the pad electrode and the η ρ pad electrodes, for external circuit connection;

步骤十、用化学机械抛光(CMP )设备将蓝宝石衬底2减薄,即将蓝宝石衬底由350 μ m〜 450 μ m减薄至90 μ m〜150 μ m,并用光刻加离子刻蚀的方法对蓝宝石的出光面进行有组织的粗糙化处理,形成粗糙化表面1。 Step 10, chemical mechanical polishing (CMP) apparatus thinned sapphire substrate 2, a sapphire substrate is about 350 μ m~ 450 μ m thinned to 90 μ m~150 μ m, by photolithography and ion etching plus the method of the sapphire surface roughening treatment in organized form a roughened surface.

[0028] 按照上述步骤和工艺制造的LED芯片,得到较好质量的倒装阵列式LED芯片。 [0028] According to the above steps and processes for manufacturing the LED chip to obtain good quality LED array flip chip.

[0029] 基于上述实例结构及其制造方法,调整有源层结构(如多个材料的量子阱形成复合量子阱)及材料组分(调整掺杂浓度改变发光波长)可以发多种颜色光,本发明也涵盖了这一LED芯片范畴。 [0029] Examples of the above-described structures and methods based on, adjust the active layer structure (e.g., a plurality of quantum wells formed in the composite material of the quantum well) and the material component (dopant concentration adjustment to change the light emission wavelength) can send multiple colors of light, the present invention also covers the LED chip category.

[0030] 本发明以上所述内容,仅给出了实现本发明的一种实施方案,但此方案和方案中的芯片结构以及工艺条件可以改变,这种改变不脱离本发明的思想及范围,对本领域人员自己明了的所有变更应当包含在所述的权利要求范围内。 [0030] The present invention described above content, is given only to achieve an embodiment of the present invention, but the chip structure and the process conditions in this embodiment and the embodiment may be changed, such changes without departing from the spirit and scope of the present invention, claim all modifications within the scope of their apparent to those skilled in the request should be included.

Claims (14)

1. 一种可控功率倒装阵列LED芯片,其特征在于:阵列LED芯片由多个阵列单元构成阵列,其中所有的阵列单元每一行的P电极层(10)连接,每一列的η电极层(5)连接;所述每个阵列单元的结构是蓝宝石衬底(2)上方依次覆盖η型缓冲层(3)、η型半导体层(6)、有源层(7)、ρ型半导体层(8)、透明电极层(9)、ρ电极层(10);所有的η电极层(5)和ρ电极层(10)由绝缘层(4)包覆;其中每一行的ρ电极层(10)通过ρ电极层(10)窗口上方的ρ 电极连接金属层(11)连接;在P电极连接金属层(11)表面还有钝化层(12 )。 A controllable power LED array flip-chip, wherein: an array of LED chips, wherein each row of the array elements of all P-electrode layer (10) is connected by a plurality of array elements constituting an array, each column electrode layer [eta] (5); said structural units each array is (2) over the sapphire substrate successively covered with [eta]-type buffer layer (3), η-type semiconductor layer (6), an active layer (7), ρ-type semiconductor layer (8), a transparent electrode layer (9), ρ electrode layer (10); all η electrode layer (5) and the electrode layer [rho] (10) (4) covered by an insulating layer; wherein each row electrode layer [rho] ( 10) (10) through the window electrode layer ρ ρ electrode connection metal layer (11) over the connection; the P-electrode connection metal layer (11) as well as a surface passivation layer (12).
2.根据权利要求1所述的可控功率倒装阵列LED芯片,其特征在于:粗糙化表面(1)为蓝宝石衬底(2)通过表面粗糙化处理形成的LED芯片出光面。 A controllable power according to claim LED array flip chip of claim 1, wherein: the roughened surface (1) is a sapphire substrate (2) by the LED chip surface roughening treatment of the surface is formed.
3.根据权利要求1所述的可控功率倒装阵列LED芯片,其特征在于:n型缓冲层(3)、n 型半导体层(6)和ρ型半导体层(8 )由GaN、GaAs或MGaN半导体材料构成;其中η型层掺入的杂质是Si材料,ρ型层掺入的杂质是Mg材料。 The controllable power LED array flip-chip according to claim 1, characterized in that: n-type buffer layer (3), n-type semiconductor layer (6) and ρ-type semiconductor layer (8) consists of GaN, GaAs, or MGaN semiconductor material; wherein η-type impurity is Si layer is doped material, ρ-type impurity is Mg layer is doped material.
4.根根据权利要求1所述的可控功率倒装阵列LED芯片,其特征在于:有源层(7)是单层的InGaN,或者是多层的InGaN层和GaN层,形成多量子阱层。 4. Root Claim controllable power LED array flip chip of claim 1, wherein: the active layer (7) is a single layer of InGaN, or a multilayer InGaN layer and the GaN layer, forming a multiple quantum well Floor.
5.根据权利要求1、2或3所述的可控功率倒装阵列LED芯片,其特征在于:LED芯片由彼此相互独立的阵列单元构成阵列,每一列阵列单元的η电极层(5)连接;η电极层(5)的材料包括Cu、Ti、Al、Ni或Au金属,采用其中的单一金属或组合金属。 The controllable power LED array flip chip 1, 2 or claim 3, wherein: LED chip array constituted by the mutually independent from each other cell array, the electrode layer [eta] (5) connected to each column of array elements ; η electrode material layer (5) comprising Cu, Ti, Al, Ni, or Au metal, wherein a single metal or a metal combination.
6.根据权利要求1、2或3所述的可控功率倒装阵列LED芯片,其特征在于:ρ电极层(10)采用Ag或Al,并且完全覆盖每一个阵列单元的透明电极层(9)。 The controllable power LED array flip chip 1, 2 or claim 3, wherein: ρ electrode layer (10) using Ag or Al, and completely covers the transparent electrode layer (9 array of cells each of ).
7.根据权利要求1、2或3所述的可控功率倒装阵列LED芯片,其特征在于:ρ电极连接金属层(11)的材料包括Cu、Ti、Al、Ni或Au金属,采用其中的单一金属或组合金属。 The controllable power LED array flip chip 1, 2 or claim 3, wherein: the metal material ρ electrode connection layer (11) comprising Cu, Ti, Al, Ni, or Au metal, wherein using the single metal or combinations of metals.
8.根据权利要求1所述的可控功率倒装阵列LED芯片,其特征在于:绝缘层(4)和钝化层(9)由SiOx、SiNx或SiOxNy绝缘材料构成。 According to claim controllable power LED array flip chip of claim 1, wherein: the insulating layer (4) and the passivation layer (9) consists of SiOx, SiNx, or SiOxNy insulating material.
9.根据权利要求1所述的可控功率倒装阵列LED芯片,其特征在于:透明电极层(9)采用金属薄膜Ni/Au或氧化铟锡制作。 According to claim controllable power LED array flip chip to claim 1, wherein: the transparent electrode layer (9) using the metal thin Ni / Au or indium tin oxide produced.
10. 一种可控功率倒装阵列LED芯片的制造方法,其特征在于,它包括以下制造步骤:步骤一,在蓝宝石衬底生长低掺杂的η型缓冲层(3),再生长高掺杂的η型半导体层(6);步骤二,生长有源层(7),生长为单层的hGaN,或者交替生长为多个周期的InGaN层和GaN层,形成多量子阱层;步骤三,在步骤二的基础上生长P型半导体层(8);步骤四,沉积透明电极层(9)和ρ电极层(10);步骤五,在步骤四的基础上进行光刻和刻蚀,露出η型缓冲层(3)和芯片的隔离槽,为η 电极的沉积做准备;步骤六,沉积金属层,并进行光刻和刻蚀,形成每一行都连接到一起的η电极层(5);步骤七,沉积绝缘层(4),并进行光刻和刻蚀,露出ρ电极层(1 O )窗口,为沉积ρ电极层(10)窗口上方的ρ电极连接金属层(11)做准备;同时在芯片边沿露出η电极pad ;步骤八,沉积金属包括Cu、T 10. A method for producing a controllable power LED array flip chip, characterized in that it comprises the following production steps: Step 1, a sapphire substrate grown low doped η-type buffer layer (3), the high-doped regrowth heteroaryl is η-type semiconductor layer (6); two step, growing an active layer (7), grown as monolayer hGaN, or alternately growing an InGaN layer and a GaN layer, a plurality of cycles to form a multiple quantum well layer; step three , grown in two steps based on a P-type semiconductor layer (8); step 4 depositing a transparent electrode layer (9) and ρ electrode layer (10); step five, photolithography and etching on the basis of step four, exposing η-type buffer layer (3) and a chip separation grooves, to prepare for the deposition of the electrode of η; step six, depositing a metal layer, and photolithography and etching, to form each row are connected together η electrode layer (5 ); step seven, depositing an insulating layer (4), and photolithography and etching, to expose the electrode layer [rho] (1 O) window, [rho] is the deposition of the electrode layer (10) ρ connection metal electrode layer over the window (11) do preparation; η electrode pad while exposing the chip edge; step eight, depositing a metal comprising Cu, T i、Al、Ni或Au金属,采用其中的单一金属或组合金属,并进行光刻和刻蚀,形成每一列阵列单元都连接在一起的P电极连接金属层(11)和η电极外接pad ;步骤九,沉积钝化层(12),并进行光刻和刻蚀,露出P电极pad和η电极pad ; 步骤十,对蓝宝石衬底(2)进行减薄,并对蓝宝石的出光面进行有组织的粗糙化处理, 形成粗糙化表面(1)。 i, Al, Ni, or Au metal, wherein a single metal or a combination of metal and photolithography and etching, the metal layer forming the P-electrode connection (11) of each column of the array cells are connected together, and external electrodes η PAD; step 9, depositing a passivation layer (12), and photolithography and etching, to expose the P electrode pad and the electrode pad η; step 10, on a sapphire substrate (2) is thinned, and the surface of sapphire has performed roughening treatment of the tissue, forming a roughened surface (1).
11.根据权利要求10所述的可控功率倒装阵列LED芯片的制造方法,其特征在于:上述制造步骤中,步骤一到步骤三可以交换沉积顺序,即先在衬底上生长P型半导体层(8)和有源层(7),最后在有源层顶部生长η型半导体层(6)。 A method for producing a controllable power LED array flip-chip according to claim 10, wherein: the above-described manufacturing steps, a step to the three step deposition sequence may be exchanged, i.e. first grown on a P-type semiconductor substrate, layer (8) and the active layer (7), and finally η-type semiconductor layer grown on top of the active layer (6).
12.根据权利要求10或11所述的可控功率倒装阵列LED芯片的制造方法,其特征在于:步骤一到步骤三采用“M0CVD”金属有机化合物汽相沉积工艺制备,或者采用“MBE”分子束外延方法制备。 A method for producing a controllable power LED array flip-chip according to claim 11 or claim 10, wherein: the step of using a three step to preparing metal-organic vapor phase deposition process "M0CVD", or with "MBE" preparation of a molecular beam epitaxy method.
13.根据权利要求9所述的可控功率倒装阵列LED芯片的制造方法,其特征在于:步骤五采用湿刻工艺,采用“ ICP”增强等离子刻蚀方法或者“RIE”反应离子刻蚀方法,或者采用该两种方法的组合。 A method for producing a controllable power LED array flip chip as claimed in claim 9, wherein: the step of five wet etching process, using "ICP" enhanced plasma etching method, or "RIE" reactive ion etching , or as a combination of the two methods.
14.根据权利要求9所述的可控功率倒装阵列LED芯片的制造方法,其特征在于:步骤四、步骤六和步骤七采用磁控溅射或电子束蒸发的方法生长透明电极层(9)、ρ电极层(10),η电极(5)和ρ电极连接金属层(11);步骤七采用“PECVD”等离子增强化学汽相沉积生长绝缘层(4)和钝化层(12);步骤十采用化学机械抛光“CMP”设备将蓝宝石衬底(2)减薄。 A method for producing a controllable power LED array flip-chip according to claim 9, wherein: step four, six and step seven step magnetron sputtering method or electron beam evaporation growth transparent electrode layer (9 ), ρ electrode layer (10), η electrode (5) and [rho] an electrode connected to the metal layer (11); step seven using "PECVD" plasma enhanced chemical vapor deposition growth of the insulating layer (4) and the passivation layer (12); step 10 using a chemical mechanical polishing "CMP" device sapphire substrate (2) is thinned.
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