CN113270439A - Controllable micro LED lattice manufacturing method - Google Patents
Controllable micro LED lattice manufacturing method Download PDFInfo
- Publication number
- CN113270439A CN113270439A CN202110488076.3A CN202110488076A CN113270439A CN 113270439 A CN113270439 A CN 113270439A CN 202110488076 A CN202110488076 A CN 202110488076A CN 113270439 A CN113270439 A CN 113270439A
- Authority
- CN
- China
- Prior art keywords
- layer
- type layer
- micro led
- top surface
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 52
- 239000002184 metal Substances 0.000 claims abstract description 52
- 238000002161 passivation Methods 0.000 claims abstract description 45
- 238000005530 etching Methods 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 23
- 238000007747 plating Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims description 10
- 229910052594 sapphire Inorganic materials 0.000 claims description 8
- 239000010980 sapphire Substances 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052681 coesite Inorganic materials 0.000 claims description 5
- 229910052906 cristobalite Inorganic materials 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 229910052682 stishovite Inorganic materials 0.000 claims description 5
- 229910052905 tridymite Inorganic materials 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 3
- 239000002245 particle Substances 0.000 abstract 1
- 239000000463 material Substances 0.000 description 8
- 239000011159 matrix material Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Chemical group 0.000 description 1
- -1 indium tin metal oxide Chemical class 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical group O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Led Devices (AREA)
Abstract
The invention discloses a controllable micro LED lattice manufacturing method, which comprises the following steps: firstly, manufacturing an epitaxial layer of the micro LED; secondly, etching the epitaxial layer; thirdly, etching the N-type layer; plating a passivation layer covering the P-type layer and the N-type layer, and etching the passivation layer; fifthly, plating a transparent conducting layer on the exposed part of the top surface of the P-type layer, wherein the transparent conducting layer protrudes out of the passivation layer; and sixthly, plating a plurality of strip-shaped metal layers correspondingly covering the P-type layer along the Y direction, then forming holes corresponding to the top surface of the P-type layer on the strip-shaped metal layers, and plating metal electrodes on the exposed ends of the N-type layer in the X direction to form a micro LED lattice. The controllable micro LED lattice manufacturing method can be applied to LED lattices with the particle size of less than 100um, does not need chip die bonding arrangement, directly completes the manufacturing of the lattice in the chip manufacturing process, and can effectively reduce equipment cost and process difficulty.
Description
Technical Field
The invention relates to the technical field of semiconductor light emitting, in particular to a controllable micro LED lattice manufacturing method.
Background
With the rapid development of LED technology and the gradual improvement of LED lighting effect, the application of LEDs is more and more extensive, the LED chip is gradually developed to a micro LED lattice from a single LED chip, and the structure of the LED chip comprises a substrate, a P-type semiconductor layer and an N-type semiconductor layer which are arranged on the substrate; the micro LED lattice is LED micro-scaling and matrixing, is a high-density micro-sized LED array integrated on a chip, reduces the distance of pixel points from millimeter level to micron level, generally adopts a process of N electrodes, and controls the lighting of each pixel point by the independent drive of a P electrode; the existing micro-LED lattice is generally realized by assembling one LED chip into an integral lattice, the manufacturing method has very complicated process in the packaging and fixing of the LED chips below 100um, the positioning requirement is high, high-precision equipment is needed, the cost is increased correspondingly, and improvement is needed.
Disclosure of Invention
The purpose of the invention is: the controllable micro LED dot matrix manufacturing method can directly manufacture the controllable LED chip dot matrix with the diameter less than 100um on a wafer, and saves a series of subsequent links such as cutting, packaging, die bonding and the like.
In order to solve the technical problem, the invention provides a controllable micro LED lattice manufacturing method.
A controllable micro LED lattice manufacturing method comprises the following steps:
firstly, sequentially growing an N-type layer and a P-type layer on a sapphire substrate by using MOCVD equipment to finish the manufacture of an epitaxial layer of the micro LED;
etching the epitaxial layer to expose the top surface of the N-type layer and form the P-type layer distributed in a lattice manner along the X direction and the Y direction;
etching the N-type layer to form a plurality of straight strip-shaped N-type layers extending along the X direction and distributed in parallel along the Y direction;
plating a passivation layer covering the P-type layer and the N-type layer, and etching the passivation layer to form an opening in the passivation layer on the top surface of the P-type layer, so that the top surface of the P-type layer is exposed in the passivation layer, and the end part of the N-type layer in the X direction is exposed;
fifthly, plating a transparent conducting layer on the exposed part of the top surface of the P-type layer, wherein the transparent conducting layer protrudes out of the passivation layer;
and sixthly, plating a plurality of strip-shaped metal layers correspondingly covering the P-type layer along the Y direction, then forming openings corresponding to the top surface of the P-type layer on the strip-shaped metal layers, exposing the transparent conducting layers in the openings of the strip-shaped metal layers, and plating metal electrodes on the exposed ends of the N-type layer in the X direction to form a micro LED lattice.
As a preferable scheme of the invention, in the third step, the distance between each N-type layer is more than or equal to 3 um.
As a preferable scheme of the present invention, in the fourth step, the size of the etching opening of the passivation layer on the top surface of the P-type layer is smaller than the size of the top surface of the P-type layer.
As a preferable aspect of the present invention, in the fifth step, the size of the top surface of the transparent conductive layer is smaller than or equal to the size of the top surface of the P-type layer, and the size of the top surface of the transparent conductive layer is larger than the size of the etching opening of the passivation layer on the P-type layer.
As a preferable embodiment of the present invention, in the sixth step, the size of the opening of the bar-shaped metal layer is smaller than the size of the top surface of the transparent conductive layer.
In a preferred embodiment of the present invention, the passivation layer is made of SiO2。
In a preferred embodiment of the present invention, the material of the transparent conductive layer is ITO.
In a preferred embodiment of the present invention, the material of the metal bar layer and the metal electrode is one or more of Cr, Al, Ti, Pt, and Au.
As a preferable scheme of the invention, the length and width of the micro LED lattice are more than or equal to 10 um.
As a preferred embodiment of the present invention, in the sixth step, the metal bar layer and the metal electrode are plated by using an evaporation process.
Compared with the prior art, the controllable micro LED dot matrix manufacturing method has the beneficial effects that: the LED lattice can be applied to LED lattices with the thickness of less than 100um, chip die bonding arrangement is not needed, lattice manufacturing is directly completed in the chip manufacturing process, and equipment cost and process difficulty can be effectively reduced.
Drawings
FIG. 1 is a front view of a micro LED lattice structure made in accordance with one embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view taken along line A-A of FIG. 1;
FIG. 3 is a schematic cross-sectional view taken along line B-B of FIG. 1;
in the figure, 1, a sapphire substrate; 2. a passivation layer; 3. a transparent conductive layer; 4. a bar-shaped metal layer; 5. and a metal electrode.
Detailed Description
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
In the description of the present invention, it is to be understood that the terms "mounted," "connected," and "connected" are used broadly and are defined as, for example, either fixedly connected, detachably connected, or integrally connected, unless otherwise explicitly stated or limited; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In the description of the present invention, it is to be further understood that the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the machine or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.
Referring to fig. 1, a method for manufacturing a controllable micro LED dot matrix according to a preferred embodiment of the present invention includes the following steps:
firstly, sequentially growing an N-type layer and a P-type layer on a sapphire substrate 1 by using MOCVD equipment to finish the manufacture of an epitaxial layer of the GaN-based micro LED;
etching the epitaxial layer, naturally removing the P-type layer from top to bottom in the etching process, and etching the corresponding part of the P-type layer and removing the other part of the P-type layer by correspondingly setting, so that the P-type layer can be arranged according to requirements to form corresponding array distribution, and meanwhile, the corresponding N-type layer is correspondingly exposed, therefore, the top surface of the N-type layer is preferably exposed by etching, the P-type layer distributed in a lattice manner along the X direction and the Y direction is formed, and the X direction and the Y direction mutually and vertically form a plane rectangular coordinate system on the plane of the sapphire substrate 1;
etching the N-type layer to form a plurality of straight-bar N-type layers extending below the P-type layer along the X direction and distributed in parallel along the Y direction, wherein each N-type layer is used as a common cathode of the corresponding P-type layer;
plating a passivation layer 2 covering the P-type layer and the N-type layer, etching the passivation layer 2 to form an opening in the passivation layer 2 on the top surface of the P-type layer, exposing the top surface of the P-type layer in the passivation layer 2, exposing the end part of the N-type layer outside the lattice in the X direction, protecting the P-type layer and the N-type layer through the passivation layer 2, and etching and removing the passivation layer 2 at the corresponding position respectively by the P-type part and the N-type layer to facilitate subsequent conductive connection of the P-type layer and the N-type layer;
fifthly, plating a transparent conducting layer 3 at the exposed position of the top surface of the P-type layer, wherein the transparent conducting layer 3 protrudes out of the passivation layer 2, and the transparent conducting layer 3 is conductive to the top surface of the P-type layer and is transparent;
and sixthly, plating a plurality of strip metal layers 4 correspondingly covering the P-type layer along the Y direction, namely, the strip metal layers 4 are distributed in parallel along the X direction and are vertical to the N-type layer, then forming holes corresponding to the top surface of the P-type layer on the strip metal layers 4, exposing the transparent conducting layers 3 in the holes of the strip metal layers 4, and plating metal electrodes 5 on the exposed end parts of the N-type layer outside the dot matrix in the X direction to form micro LED dot matrixes, wherein the strip metal layers 4 are conductive to the P-type layer through each transparent conducting layer 3, and the metal electrodes 5 are conductive to the N-type layer, so that the corresponding electrification of each dot matrix is realized.
In the third step, the distance between each N-type layer is greater than or equal to 3um, so that the finest process is optimally realized and etching residues between the strip-shaped N-type layers are avoided.
Referring to fig. 2 and 3, for example, in the fourth step, the size of the etching opening of the passivation layer 2 on the top surface of the P-type layer is smaller than that of the top surface of the P-type layer, so that the top surface of the P-type layer is well covered and protected by the passivation layer 2, and the transparent conductive layer 4 can be plated conveniently to be conductive with the P-type layer.
Referring to fig. 2 and 3, for example, in the fifth step, the size of the top surface of the transparent conductive layer 3 protruding from the passivation layer 2 is smaller than or equal to the size of the top surface of the P-type layer, and the size of the top surface of the transparent conductive layer 3 is larger than the size of the etching opening of the passivation layer 2 on the P-type layer, so that the transparent conductive layer 3 has an optimal conductive and light-transmitting effect between the bar-shaped metal layer 4 and the P-type layer.
Referring to fig. 2 and 3, for example, in the sixth step, the size of the opening of the bar-shaped metal layer 4 is smaller than the size of the top surface of the transparent conductive layer 3, so as to ensure that the bar-shaped metal layer 4 and the top surface of the transparent conductive layer 3 have a sufficient conductive surface.
Illustratively, the material of the passivation layer 2 is SiO2From SiO2The film layer can isolate P, N electrodes to prevent short circuit, prevent water vapor and impurity atoms from adsorbing the surface of the chip, protect the transparent conducting layer 3 and improve the luminous efficiency, and the material of the passivation layer 2 can also be SiNx, Al2O3 or other materials.
Illustratively, the material of the transparent conductive layer 3 is ITO, which is an abbreviation of indium tin metal oxide, and the formed indium tin oxide film has good conductivity and transparency.
Illustratively, the material of the bar-shaped metal layer 4 and the metal electrode 5 is one or more of Cr, Al, Ti, Pt, and Au.
Illustratively, the length and width dimensions of the micro LED lattice are more than or equal to 10 um.
In the sixth step, the strip-shaped metal layer 4 and the metal electrode 5 are plated by using an evaporation process, so that the method has the advantages of simple film forming method, high film purity and compactness, unique film structure and performance and the like.
Referring to fig. 1-3, the controllable micro LED lattice obtained by the manufacturing method of the present invention comprises, in the order of process, a sapphire substrate 1, N-type layers, P-type layers, a passivation layer 2, a transparent conductive layer 3, a bar-shaped metal layer 4 and a metal electrode 5, wherein the N-type layers are a plurality of layers extending in the X direction into a straight bar shape and distributed in parallel on the sapphire substrate 1 in the Y direction, the P-type layers are a plurality of layers distributed in a lattice shape on the N-type layers in the X and Y directions, the passivation layer 2 covers the P-type layers and covers the vicinity of the end of the N-type layers in the X direction, an opening is formed on the top surface of the passivation layer 2, the transparent conductive layer 3 is disposed on the P-type layer in the opening of the passivation layer 2, the transparent conductive layer 3 protrudes out of the passivation layer 2, and the bar-shaped metal layers 4 are distributed in parallel in the X, each strip metal layer 4 correspondingly extends along the Y direction to cover a plurality of P-type layers, the strip metal layers 4 shield the top surfaces and the peripheral side walls of the P-type layers, the transparent conductive layers 3 are abutted against the strip metal layers 4, openings which correspond to the top surfaces of the P-type layers and expose the transparent conductive layers 3 are formed in the strip metal layers 4, and the metal electrodes 5 are arranged on the left end portion and the right end portion of the N-type layer in the X direction; a chip in a lattice is formed between each P-type layer and the N-type layer, the P-type layers and the N-type layers are generated on the sapphire substrate 1 and are correspondingly etched, then the passivation layer 2 is plated to cover, protect and insulate the P-type layer, and abdications are reserved only on the top surface of the P-type layer and at the two ends of the N-type layer, so that the P-type layers arranged along the Y direction can be in conductive connection by plating the transparent conductive layer 3 in the opening of the passivation layer 2 and conducting and transmitting light with the P-type layer and plating the strip-shaped metal strip 4, wherein the strip metal layer 4 is connected with the transparent conductive layer 3 in an attaching and abutting way, and blocks the lateral light divergence by covering and shielding the side wall of the P-type layer, and the axial light outlet is reserved only through the opening to obtain the light with axial concentration, thereby solving the problem of facula during light emitting, and the metal electrodes 5 plated on the two ends of the N-type layer make the N-type layer extending along the X direction conduct with the same N pole in the transverse direction.
Illustratively, the distance between the N-type layers is larger than or equal to 3um, and the length and width dimensions of the micro LED lattice are larger than or equal to 10 um.
Referring to fig. 2 and 3, for example, the opening size of the passivation layer 2 on the top surface of the P-type layer is smaller than the size of the top surface of the P-type layer.
Referring to fig. 2 and 3, for example, the size of the top surface of the transparent conductive layer 3 protruding the passivation layer 2 is smaller than or equal to the size of the top surface of the P-type layer, and the size of the top surface of the transparent conductive layer 3 is larger than the size of the etching opening of the passivation layer 2 on the P-type layer.
Referring to fig. 2 and 3, for example, the size of the opening of the bar-shaped metal layer 4 is smaller than the size of the top surface of the transparent conductive layer 3.
Illustratively, the material of the passivation layer 2 is SiO2The transparent conductive layer 3 is made of ITO, and the strip-shaped metal layer 4 and the metal electrode 5 are made of one or more of Cr, Al, Ti, Pt, and Au.
Referring to fig. 2 and 3, illustratively, the strip-shaped metal layer 4 extends downwards along the peripheral sidewall of the P-type layer and correspondingly covers the passivation layer 2, so as to further ensure complete blocking of lateral light divergence and high process requirements.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and substitutions can be made without departing from the technical principle of the present invention, and these modifications and substitutions should also be regarded as the protection scope of the present invention.
Claims (10)
1. A controllable micro LED lattice manufacturing method is characterized by comprising the following steps:
firstly, sequentially growing an N-type layer and a P-type layer on a sapphire substrate by using MOCVD equipment to finish the manufacture of an epitaxial layer of the micro LED;
etching the epitaxial layer to expose the top surface of the N-type layer and form the P-type layer distributed in a lattice manner along the X direction and the Y direction;
etching the N-type layer to form a plurality of straight strip-shaped N-type layers extending along the X direction and distributed in parallel along the Y direction;
plating a passivation layer covering the P-type layer and the N-type layer, and etching the passivation layer to form an opening in the passivation layer on the top surface of the P-type layer, so that the top surface of the P-type layer is exposed in the passivation layer, and the end part of the N-type layer in the X direction is exposed;
fifthly, plating a transparent conducting layer on the exposed part of the top surface of the P-type layer, wherein the transparent conducting layer protrudes out of the passivation layer;
and sixthly, plating a plurality of strip-shaped metal layers correspondingly covering the P-type layer along the Y direction, then forming openings corresponding to the top surface of the P-type layer on the strip-shaped metal layers, exposing the transparent conducting layers in the openings of the strip-shaped metal layers, and plating metal electrodes on the exposed ends of the N-type layer in the X direction to form a micro LED lattice.
2. The method for manufacturing a controllable micro LED lattice according to claim 1, wherein: in the third step, the distance between each N-type layer is more than or equal to 3 um.
3. The method for manufacturing a controllable micro LED lattice according to claim 1, wherein: in the fourth step, the size of the etching opening of the passivation layer on the top surface of the P-type layer is smaller than that of the top surface of the P-type layer.
4. The method for manufacturing a controllable micro LED lattice according to claim 1, wherein: in the fifth step, the size of the top surface of the transparent conducting layer is smaller than or equal to that of the P-type layer, and the size of the top surface of the transparent conducting layer is larger than that of an etching opening of the passivation layer on the P-type layer.
5. The method for manufacturing a controllable micro LED lattice according to claim 1, wherein: in the sixth step, the size of the opening of the bar-shaped metal layer is smaller than the size of the top surface of the transparent conductive layer.
6. The method for manufacturing a controllable micro LED lattice according to any one of claims 1 to 5, wherein: the passivation layer is made of SiO2。
7. The method for manufacturing a controllable micro LED lattice according to any one of claims 1 to 5, wherein: the transparent conducting layer is made of ITO.
8. The method for manufacturing a controllable micro LED lattice according to any one of claims 1 to 5, wherein: the strip-shaped metal layer and the metal electrode are made of one or more of Cr, Al, Ti, Pt and Au.
9. The method for manufacturing a controllable micro LED lattice according to any one of claims 1 to 5, wherein: the length and width of the micro LED lattice are more than or equal to 10 um.
10. The method for manufacturing a controllable micro LED lattice according to any one of claims 1 to 5, wherein: and in the sixth step, the strip-shaped metal layer and the metal electrode are plated by adopting an evaporation process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110488076.3A CN113270439B (en) | 2021-04-30 | 2021-04-30 | Controllable micro-LED lattice manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110488076.3A CN113270439B (en) | 2021-04-30 | 2021-04-30 | Controllable micro-LED lattice manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113270439A true CN113270439A (en) | 2021-08-17 |
| CN113270439B CN113270439B (en) | 2024-02-20 |
Family
ID=77229957
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110488076.3A Active CN113270439B (en) | 2021-04-30 | 2021-04-30 | Controllable micro-LED lattice manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113270439B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070069222A1 (en) * | 2005-09-26 | 2007-03-29 | Samsung Electro-Mechanics Co., Ltd. | Gallium nitride based semiconductor light emitting diode and method of manufacturing the same |
| CN102244087A (en) * | 2011-07-29 | 2011-11-16 | 贵州大学 | Controllable power flip array light emitting diode (LED) chip and manufacturing method thereof |
| US20110297914A1 (en) * | 2010-06-07 | 2011-12-08 | Xiamen Sanan Optoelectronics Technology Co., Ltd. | Gallium nitride-based flip-chip light-emitting diode with double reflective layers on its side and fabrication method thereof |
| KR20120084558A (en) * | 2011-01-20 | 2012-07-30 | 갤럭시아포토닉스 주식회사 | Light emitting diode having current blocking pattern and light emitting diode package |
| CN105720140A (en) * | 2016-03-03 | 2016-06-29 | 映瑞光电科技(上海)有限公司 | GaN-based LED (Light-Emitting Diode) vertical chip structure and preparation method |
| CN107068826A (en) * | 2017-01-18 | 2017-08-18 | 中国科学院半导体研究所 | LED chip of bloom outgoing efficiency and preparation method thereof |
| US20180151632A1 (en) * | 2016-11-29 | 2018-05-31 | Gwangju Institute Of Science And Technology | Micro display having vertically stacked structure and method of forming the same |
| CN108538876A (en) * | 2018-04-24 | 2018-09-14 | 万金平 | A kind of Light Transmission AR glasses display chips and preparation method thereof |
-
2021
- 2021-04-30 CN CN202110488076.3A patent/CN113270439B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070069222A1 (en) * | 2005-09-26 | 2007-03-29 | Samsung Electro-Mechanics Co., Ltd. | Gallium nitride based semiconductor light emitting diode and method of manufacturing the same |
| US20110297914A1 (en) * | 2010-06-07 | 2011-12-08 | Xiamen Sanan Optoelectronics Technology Co., Ltd. | Gallium nitride-based flip-chip light-emitting diode with double reflective layers on its side and fabrication method thereof |
| KR20120084558A (en) * | 2011-01-20 | 2012-07-30 | 갤럭시아포토닉스 주식회사 | Light emitting diode having current blocking pattern and light emitting diode package |
| CN102244087A (en) * | 2011-07-29 | 2011-11-16 | 贵州大学 | Controllable power flip array light emitting diode (LED) chip and manufacturing method thereof |
| CN105720140A (en) * | 2016-03-03 | 2016-06-29 | 映瑞光电科技(上海)有限公司 | GaN-based LED (Light-Emitting Diode) vertical chip structure and preparation method |
| US20180151632A1 (en) * | 2016-11-29 | 2018-05-31 | Gwangju Institute Of Science And Technology | Micro display having vertically stacked structure and method of forming the same |
| CN107068826A (en) * | 2017-01-18 | 2017-08-18 | 中国科学院半导体研究所 | LED chip of bloom outgoing efficiency and preparation method thereof |
| CN108538876A (en) * | 2018-04-24 | 2018-09-14 | 万金平 | A kind of Light Transmission AR glasses display chips and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113270439B (en) | 2024-02-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105789236B (en) | Wafer LED packaging part and its manufacturing method | |
| EP2530748B1 (en) | Light emitting device | |
| EP2333852B1 (en) | Light emitting device and light emitting package | |
| KR101069061B1 (en) | Stacked solar cell device | |
| KR101017394B1 (en) | Light emitting device and method of fabricating the same | |
| US10290769B2 (en) | Vertical type light emitting diode having groove disposed under the first conductivity type semiconductor layer | |
| CN102024892B (en) | Group III nitride semiconductor light-emitting device | |
| CN102347414B (en) | Luminescent device | |
| WO2012091042A1 (en) | Light emitting element, light emitting element unit, and light emitting element package | |
| CN104241486A (en) | Semiconductor light emitting device and method of manufacturing the same | |
| CN103828053A (en) | Semiconductor light emitting device and light emitting module | |
| KR20100079843A (en) | Light emitting device having plurality of non-polar light emitting cells and method of fabricating the same | |
| KR101047720B1 (en) | Light emitting device, method for fabricating the light emitting device and light emitting device package using the light emitting device | |
| EP2246891B1 (en) | Light emitting device, light emitting device package, and lighting system including the same | |
| CN105390582B (en) | Luminescent device, the method and light emitting device package for manufacturing luminescent device | |
| EP2448014B1 (en) | Semiconductor light emitting device | |
| CN102386313B (en) | Light emitting device, light emitting device package, and light unit | |
| US20190371990A1 (en) | Light emitting diode and light emitting device having the same | |
| US20130236997A1 (en) | Method of fabricating light emitting device | |
| US9589940B2 (en) | Light emitting device | |
| CN113270439A (en) | Controllable micro LED lattice manufacturing method | |
| CN215342602U (en) | Controllable micro LED lattice | |
| US20210366980A1 (en) | Light-emitting device, light source module, and method of manufacturing light-emitting device | |
| CN113270438B (en) | Manufacturing process of flip micro LED lattice | |
| CN214505494U (en) | Inverted micro LED dot matrix |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |