CN102244043B - 接垫结构、线路载板及集成电路芯片 - Google Patents
接垫结构、线路载板及集成电路芯片 Download PDFInfo
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Abstract
本发明公开一种接垫结构、线路载板及集成电路芯片,该接垫结构适用于一线路载板或一集成电路芯片。接垫结构包括一内部垫、一导电块及一外部垫。导电块连接内部垫。外部垫连接导电块以适于连接一导电球或一导电凸块。外部垫的外径大于内部垫的外径。
Description
技术领域
本发明涉及一种接垫结构,且特别是涉及一种适用于线路载板或集成电路芯片以连接导电球或导电凸块的接垫结构。
背景技术
对于电子工业而言,焊接是主要的连接技术,例如应用于芯片与载板之间的覆晶接合,或一般电子零件与电路板之间的连接。除了焊料、接垫本身及接垫的表面材料以外,接垫结构也是影响接合可靠度的关键因素。
芯片的多功能及小型化是电子产品的趋势,这使得芯片上的接点密度也对应增加。在这样的情况下,对于特定电性要求(例如低阻抗、高频率、耦合灵敏度等...)的信号而言,线宽及线距可能需要增加,因而造成空间限制。
接垫外径取决于焊球或凸块的间距及尺寸和防焊开口的尺寸,因此接垫外径及接垫结构之间具有相当大的依赖性,也因此决定两接垫间的距离或走线空间,但这不利于布线设计上的弹性。
当走线空间不够时,可应用减少的线宽及线距来增加走线空间,但这造成电性效能的劣化,例如信号反射、串音及耦合等的发生。由于高密度接点设计的趋势,上述这些问题将会变得越来越严重。
发明内容
本发明的目的在于提出一种接垫结构,可提高布线密度。
本发明再一目的在于提出一种线路载板,可提高布线密度。
本发明另一目的在于提出一种集成电路芯片,可提高布线密度。
为达上述目的,本发明提供一种接垫结构,适用于一线路载板或一集成电路芯片。接垫结构包括一内部垫、一导电块及一外部垫。导电块连接内部垫。外部垫连接导电块以适于连接一导电球或一导电凸块。外部垫的外径大于内部垫的外径。
本发明还提供一种线路载板,其包括一基础层、一内部线路层、一介电层、一第一导电块及一第一外部垫。内部线路层配置在基础层上且具有一第一内部垫。介电层配置在基础层上且覆盖内部线路层。第一导电块配置于介电层内且连接第一内部垫。第一外部垫配置在介电层上且连接第一导电块。第一内部垫的外径小于第一外部垫的外径。
本发明还提供一种集成电路芯片,其包括一半导体基底、一集成电路叠构、一内部线路层、一介电层、一第一导电块及一第一外部垫。半导体基底具有一有源面(主动面)。集成电路叠构配置在有源面上。内部线路层配置在集成电路叠构上且具有一第一内部垫。介电层配置在集成电路叠构上且覆盖内部线路层。第一导电块配置于介电层内且连接第一内部垫。第一外部垫配置在介电层上且连接第一导电块。第一内部垫的外径小于第一外部垫的外径。
基于上述,本发明缩小接垫结构的内部垫的外径,以提高内部垫所在线路层(即内部线路层)的布线弹性,因而提高布线密度或提升电性效能。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合所附附图作详细说明如下。
附图说明
图1为本发明的一实施例的线路载板的局部剖视图;
图2为图1的部分X的放大图;
图3为图2的接垫结构的立体图;
图4为图2的两接垫结构及多条走线的俯视图;
图5为本发明的另一实施例的接垫结构的立体图;
图6为图5的两接垫结构及多条走线的俯视图;
图7为本发明的另一实施例的两接垫结构及多条走线的俯视图;
图8为本发明的另一实施例的两接垫结构及多条走线的俯视图;
图9为本发明的另一实施例的两接垫结构及多条走线的俯视图;
图10为本发明的另一实施例的两接垫结构及多条走线的俯视图;
图11为本发明的另一实施例的集成电路芯片的局部剖视图;
图12为图11的部分Y的放大图。
主要元件符号说明
10:线路载板
12:基础层
14:内部线路层
14’:走线
14”:线段
16:介电层
16’:开口
18:导电球
20:集成电路芯片
21:半导体基底
21a:有源面
22:集成电路叠构
24:内部线路层
26:介电层
101、102、103、104、105、106:接垫结构
110:内部垫
110’:切边
120、120’:导电块
130:外部垫
201:接垫结构
210:内部垫
220:导电块
230:外部垫
A:距离
C1、C2:形心
E:延伸方向
L:纵长方向
P:距离
R1、R2:距离
S:直线
具体实施方式
图1为本发明的一实施例的线路载板的局部剖视图,而图2为图1的部分X的放大图。请参考图1及图2,本实施例的线路载板10包括一基础层12。基础层12可为一个由多个介电树脂层及多个图案化导电金属层所交替叠合的线路叠构,或可为单一材料层。线路载板10还包括一内部线路层14及一介电层16。内部线路层14为一图案化金属层且配置在基础层12上。介电层16配置在该基础层12上且覆盖内部线路层14。在本实施例中,介电层16可为一防焊层。
图3为图2的接垫结构的立体图。请参考图2及图3,线路载板10可包括一接垫结构101。接垫结构101包括一内部垫110、一导电块120及一外部垫130。在本实施例中,内部线路层14的一部分形成内部垫110,且介电层16有一开口16’,且开口16’暴露内部垫110。导电块120配置于开口16’内且连接内部垫110。外部垫130配置在介电层16上且连接导电块120,以提供更大的接合面积来连接一导电球18。
图4为图2的两接垫结构及多条走线的俯视图,其中外部垫130以虚线绘示。请参考图2及图4,在本实施例中,内部垫110的外径可小于外部垫130的外径,这起因于介电层16的开口16’可通过激光烧蚀而成。由于激光的对位精准度优于传统的印刷或光刻(包括曝光及显影)的对位精准度,所以内部垫110不需预留较大的尺寸以预防对位的误差,故内部垫110的外径可以缩小,使得内部垫110的外径可小于外部垫130的外径。
相比较于现有技术,在外部垫具有相同外径及/或相同密度的条件下,本发明缩小了内部垫110的外径,这有助于提高内部垫110所在线路层(即内部线路层14)的布线弹性,用以提高布线密度或提升电性效能。举例而言,在本实施例中,当内部垫110缩小以后,内部线路层所形成的一条走线14’在外部垫130所在几何平面上的正投影可与外部垫130相重叠。
在本实施例中,线路载板10更可包括另一接垫结构101,而这两个接垫结构101位于多条走线14’的两侧。
图5为本发明的另一实施例的接垫结构的立体图,图6为图5的两接垫结构及多条走线的俯视图。请参考图5及图6,相较于图3及图4的接垫结构101的单一导电块120位于对应的内部垫110及对应的外部垫130之间,本实施例的接垫结构102具有多个导电块120’同时位于对应的内部垫110及对应的外部垫130之间。除了图5及图6中所绘示的四个导电块120’以外,导电块120’的数量仍可依照内部垫110的面积或导电块120’的外径来加以调整。同样地,在本实施例中,两个接垫结构102位于多条走线14’的两侧。值得一提的是,上述的小尺寸的导电块120’所对应的介电层的多个开口同样也可通过激光烧蚀而成。而且,通过形成多个小尺寸的导电块120’可达到等同一个较大尺寸的导电块120(见图3及图4)的电性效果。
图7为本发明的另一实施例的两接垫结构及多条走线的俯视图。请参考图7,相较于图4的实施例,本实施例的接垫结构103的内部垫110具有一切边110’。切边110’朝向与切边110’相邻的线段14”,且切边110’实质上平行于与切边110’相邻的一线段14”的延伸方向E,其中线段14”为走线14的一部分。此外,由于内部垫110具有一切边110’,故内部垫110可以更进一步缩小,并且通过切边110’可增加两相邻内部垫110之间的距离,而这些都有助于提高内部垫110所在线路层的布线弹性,用以提高布线密度或提升电性效能。举例而言,在外部垫130具有相同外径及相同密度的条件下,图4的实施例允许四条走线于这两内部垫110之间,而图7中具有切边110’的实施例允许五条走线于这两内部垫110之间。
请再参考图7,在本实施例中,对于这两个接垫结构103而言,这两内部垫110的形心C1及形心C2之间的距离为P,左侧的内部垫110的形心C1至其轮廓任一点的最大距离为R1,右侧的内部垫110的形心C2至其轮廓任一点的最大距离为R2,这两个内部垫110的轮廓之间的最短距离为A,且P减去R1及R2总和的差值小于A,即[P-(R1+R2)]<A。P减去R1及R2总和的差值等于A,即[P-(R1+R2)]=A的情况出现在图4的实施例中。在图4的实施例中,内部垫110不具有切边110’。
图8为本发明的另一实施例的两接垫结构及多条走线的俯视图。请参考图8,相较于图7的实施例,本实施例的每个接垫结构104具有多个较小尺寸的导电块120’,其同时位于对应的内部垫110及对应的外部垫130之间。通过形成多个小尺寸的导电块120’也可达到等同一个较大尺寸的导电块120(见图3及图4)的电性效果。
图9为本发明的另一实施例的两接垫结构及多条走线的俯视图。请参考图9,相较于图8的实施例,本实施例的每个接垫结构105的内部垫110呈纵长形状(例如长方形或椭圆形),且内部垫110的纵长方向L实质上平行于与内部垫110a相邻的一线段14”的延伸方向E。通过改变内部垫110的形状、增加内部垫110的面积及增加导电块120的数量有助于提升导电球18(见图2)的机械强度,如抗拉或剪切力。
图10为本发明的另一实施例的两接垫结构及多条走线的俯视图。请参考图10,相较于图9的实施例,本实施例的每个接垫结构106的内部垫110的纵长方向L随着这些走线14’的延伸方向E旋转,这有助于缩短走线14’的长度并减少信号反射。具体而言,这些内部垫110的纵长方向L均倾斜于(即非正交于)一穿过这两内部垫的形心C1及C2的直线S。
图11为本发明的另一实施例的集成电路芯片的局部剖面图,而图12为图11的部分Y的放大图。请参考图11及图12,本实施例的集成电路芯片20包括一半导体基底21及一集成电路叠构22,其中半导体基底21具有一有源面21a,而集成电路叠构22配置在有源面21a上。集成电路叠构22可由多个有源元件(例如晶体管)、多个被动元件(例如电容器及电感器等)及多重内连线结构(multilevel interconnect structure)等所构成。集成电路芯片20更包括一内部线路层24及一介电层26,其中内部线路层24配置在该集成电路叠构22上,介电层26配置在集成电路叠构22上且覆盖内部线路层24。
请参考图12,集成电路芯片20可包括一接垫结构200。接垫结构200包括一内部垫210、一导电块220及一外部垫230。在本实施例中,内部线路层24的一部分形成内部垫210,且介电层26有一开口26’,且开口26’暴露内部垫210。导电块220配置于开口26’内且连接内部垫210。外部垫230配置在介电层26上且连接导电块220,以提供更大的接合面积来连接一导电凸块28。值得注意的是,内部垫210的外径小于外部垫230的外径。类似于图1及图2的线路载板10的接垫结构100,图11及图12的集成电路芯片20的接垫结构200也可衍生出多种变化,如同图6、图7、图8、图9及图10的实施例所示,于此不再赘述。
综上所述,本发明缩小接垫结构的内部垫的外径,以提高内部垫所在线路层(即内部线路层)的布线弹性,因而提高布线密度或提升电性效能。此外,本发明更可通过改变内部垫的形状、增加内部垫的面积及增加导电块的数量,以提升外部垫所接合的导电球或导电凸块的机械强度,如抗拉或剪切力。
虽然结合以上实施例揭露了本发明,然而其并非用以限定本发明,任何所属技术领域中熟悉此技术者,在不脱离本发明的精神和范围内,可作些许的更动与润饰,故本发明的保护范围应以附上的权利要求所界定的为准。
Claims (14)
1.一种接垫结构,适用于一线路载板或一集成电路芯片,该接垫结构包括:
第一内部垫;
第一导电块,连接该第一内部垫;
第一外部垫,连接该第一导电块以适于连接一导电球或一导电凸块,且该第一外部垫的外径大于该第一内部垫的外径;
该接垫结构还包括:
第二导电块;以及
第二内部垫和第二外部垫,该第二导电块连接该第二内部垫,该第二外部垫连接该第二导电块,且该第二外部垫的外径大于该第二内部垫的外径;
其中该第一内部垫的形心及该第二内部垫的形心之间的距离为P,该第一内部垫的形心至其轮廓任一点的最大距离为R1,该第二内部垫的形心至其轮廓任一点的最大距离为R2,该第一内部垫的轮廓及该第二内部垫的轮廓之间的最短距离为A,且P减去R1及R2总和的差值小于A,[P-(R1+R2)]<A。
2.如权利要求1所述的接垫结构,还包括:
多个该第一导电块,位于该第一内部垫与该第一外部垫之间,且连接该第一内部垫及该第一外部垫。
3.如权利要求1所述的接垫结构,其中该第一内部垫的形状具有一切边。
4.如权利要求1所述的接垫结构,其中该第一内部垫的形状呈纵长形状。
5.一种线路载板,包括:
基础层;
内部线路层,配置在该基础层上且具有第一内部垫;
介电层,配置在该基础层上且覆盖该内部线路层;
第一导电块,配置于该介电层内且连接该第一内部垫;以及
第一外部垫,配置在该介电层上且连接该第一导电块,该第一内部垫的外径小于该第一外部垫的外径;
该线路载板还包括:
第二导电块;以及
第二外部垫,其中该内部线路层还具有第二内部垫,该第二导电块配置于该介电层内且连接该第二内部垫,该第二外部垫连接该第二导电块,且该第二外部垫的外径大于该第二内部垫的外径;
其中该第一内部垫的形心及该第二内部垫的形心之间的距离为P,该第一内部垫的形心至其轮廓任一点的最大距离为R1,该第二内部垫的形心至其轮廓任一点的最大距离为R2,该第一内部垫的轮廓及该第二内部垫的轮廓之间的最短距离为A,且P减去R1及R2总和的差值小于A,[P-(R1+R2)]<A。
6.如权利要求5所述的线路载板,其中该内部线路层还具有一走线,该走线在该第一外部垫所在几何平面上的正投影与该第一外部垫相重叠。
7.如权利要求5所述的线路载板,其中该内部线路层还具有一走线,该第一内部垫具有第一切边,该第一切边朝向与该第一切边相邻的一线段,且该第一切边实质上平行于该线段的延伸方向,其中该线段为该走线的一部分。
8.如权利要求5所述的线路载板,其中该内部线路层还具有一走线,该第一内部垫呈纵长形状,且该第一内部垫的纵长方向实质上平行于与该第一内部垫相邻的一线段的延伸方向,其中该线段为该走线的一部分。
9.如权利要求5所述的线路载板,其中该内部线路层还具有一走线,该第一内部垫及该第二内部垫呈纵长形状,该第一内部垫的纵长方向实质上平行于与该第一内部垫相邻的一线段的延伸方向,该第二内部垫的纵长方向实质上平行于该线段的延伸方向,且该第一内部垫的纵长方向及该第二内部垫的纵长方向倾斜于一穿过该第一内部垫的形心与该第二内部垫的形心的直线,其中该线段为该走线的一部分。
10.一种集成电路芯片,包括:
半导体基底,具有一有源面;
集成电路叠构,配置在该有源面上;
内部线路层,配置在该集成电路叠构上且具有第一内部垫;
介电层,配置在该集成电路叠构上且覆盖该内部线路层;
第一导电块,配置于该介电层内且连接该第一内部垫;以及
第一外部垫,配置在该介电层上且连接该第一导电块,该第一内部垫的外径小于该第一外部垫的外径;
该集成电路芯片还包括:
第二导电块;以及
第二外部垫,其中该内部线路层还具有第二内部垫,该第二导电块配置于该介电层内且连接该第二内部垫,该第二外部垫连接该第二导电块,且该第二外部垫的外径大于该第二内部垫的外径;
其中该第一内部垫的形心及该第二内部垫的形心之间的距离为P,该第一内部垫的形心至其轮廓任一点的最大距离为R1,该第二内部垫的形心至其轮廓任一点的最大距离为R2,该第一内部垫的轮廓及该第二内部垫的轮廓之间的最短距离为A,且P减去R1及R2总和的差值小于A,[P-(R1+R2)]<A。
11.如权利要求10所述的集成电路芯片,其中该内部线路层还具有一走线,该走线在该第一外部垫所在几何平面上的正投影与该第一外部垫相重叠。
12.如权利要求10所述的集成电路芯片,其中该内部线路层还具有一走线,该第一内部垫具有第一切边,该第一切边朝向与该第一切边相邻的一线段,且该第一切边实质上平行于该线段的延伸方向,其中该线段为该走线的一部分。
13.如权利要求10所述的集成电路芯片,其中该内部线路层还具有一走线,该第一内部垫呈纵长形状,且该第一内部垫的纵长方向实质上平行于与该第一内部垫相邻的一线段的延伸方向,其中该线段为该走线的一部分。
14.如权利要求10所述的集成电路芯片,其中该内部线路层还具有一走线,该第一内部垫及该第二内部垫呈纵长形状,该第一内部垫的纵长方向实质上平行于与该第一内部垫相邻的一线段的延伸方向,该第二内部垫的纵长方向实质上平行于该线段的延伸方向,且该第一内部垫的纵长方向及该第二内部垫的纵长方向倾斜于一穿过该第一内部垫的形心与该第二内部垫的形心的直线,其中该线段为该走线的一部分。
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