CN102231391B - Quantum-effect device based on MIS (Metal-Insulator-Semiconductor) structure - Google Patents
Quantum-effect device based on MIS (Metal-Insulator-Semiconductor) structure Download PDFInfo
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- CN102231391B CN102231391B CN 201110177230 CN201110177230A CN102231391B CN 102231391 B CN102231391 B CN 102231391B CN 201110177230 CN201110177230 CN 201110177230 CN 201110177230 A CN201110177230 A CN 201110177230A CN 102231391 B CN102231391 B CN 102231391B
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Abstract
The invention belongs to the technical field of quantum-effect devices, in particular relates to a quantum-effect device based on an MIS (Metal-Insulator-Semiconductor) structure. The quantum-effect device comprises a semiconductor substrate, a source electrode, a drain electrode, a tunneling insulator layer and a metal layer, wherein the source electrode, the drain electrode, the tunneling insulator layer and the metal layer are arranged on the semiconductor substrate; and the metal layer, the tunneling insulator layer and the semiconductor layer form an MIS structure. The quantum-effect device further comprises a grid electrode and a grating type insulator layer, wherein the grid electrode is arranged at one side of the MIS structure, and the grating type insulator layer is arranged between the MIS structure and the grid electrode. According to the quantum-effect device based on the MIS structure, a quantum tunneling effect and a gated diode are integrated together, and a gated metal insulator semiconductor diode based on the quantum tunneling effect is manufactured by using a platform process. A suitable bias voltage is applied to the quantum-effect device so that the tunneling efficiency of the quantum-effect device can be controlled, a drain current can be reduced to be much smaller than the drain current of a normal diode, and the power dissipation of a chip is reduced.
Description
Technical field
The invention belongs to quantum effect device technology field, be specifically related to a kind of quantum effect device based on the metal-insulator semiconductor structure.
Background technology
In recent years, the microelectric technique take silicon integrated circuit as core has obtained development rapidly.Integrated level is followed Moore's Law basically as one of important indicator of weighing the integrated circuit development, and namely the integrated level of semiconductor chip is with every speed increment of doubling in 18 months, and this requires the size of device constantly to dwindle.Feature sizes of semiconductor devices constantly dwindle process, when the characteristic size of chip is in micro-meter scale, electronics wherein mainly is corpuscular property in wave-particle duality, the most semiconductor device has only utilized the corpuscular property of electronics; When the characteristic size of chip is in nanoscale, especially grow or the mean free path of electronics can be compared or more hour when the moral cloth Glass of characteristic size and electronics, electronics wherein mainly is fluctuation in wave-particle duality, this The Wave Behavior of Electrons is exactly a kind of quantum effect.The energy that so-called quantum effect is electronics is by quantization, and the motion of electronics suffers restraints on certain direction.
Tunneling effect also makes potential barrier run through, and according to classical theory, gross energy can not realization response lower than potential barrier.But according to the quantum mechanics viewpoint, no matter whether particle energy is higher than potential barrier, can not affirm that all whether particle can cross potential barrier, can only say the size that particle is crossed the potential barrier probability.It depends on the energy of barrier height, width and particle itself.Energy higher than potential barrier, the direction of motion is suitable may not necessarily react, and can only say that reaction probability is larger.And energy is lower than the certain probability realization response of still having of potential barrier, namely may some particle passes through potential barrier as passing through from the mountain tunnel, Here it is tunneling effect.
Along with further developing of integrated circuit (IC)-components technology, the size of semiconductor device is more and more less, quantum tunneling effect plays more and more important effect in the work of semiconductor device, therefore also become the focus of current research based on the semiconductor device of quantum tunneling effect.
Summary of the invention
The object of the invention is to propose a kind of new semiconductor device based on quantum tunneling effect, to reduce chip power-consumption.
For reaching above-mentioned purpose of the present invention, the present invention proposes a kind of quantum effect device based on the metal-insulator semiconductor structure, specifically comprise:
A Semiconductor substrate;
Be positioned at the source electrode that forms on described Semiconductor substrate;
Be positioned at the drain electrode that forms on described Semiconductor substrate;
Be positioned at the tunnelling insulator layer that described semiconductor substrate surface forms;
The metal level that forms between described drain electrode and described tunnelling insulator layer;
Described metal level, tunnelling insulator layer and described Semiconductor substrate consist of a MIS(metal-insulator semiconductor) structure;
Be positioned at the grid that on described Semiconductor substrate, described MIS structure one side forms;
The gate insulator layer that forms between described MIS structure and described grid.
Simultaneously, the invention allows for the manufacture method of above-mentioned quantum effect device based on the metal-insulator semiconductor structure, concrete steps comprise:
A Semiconductor substrate is provided;
Form the ground floor insulation film;
Form the ground floor conductive film;
The described ground floor conductive film of etching;
The described ground floor insulation film of etching;
Continue the described Semiconductor substrate of etched portions;
Form second layer insulation film;
The described second layer insulation film of etching forms contact hole;
Form second layer conductive film;
The described second layer conductive film of etching forms electrode.
Further, described Semiconductor substrate is monocrystalline silicon, polysilicon or is the silicon (SOI) on insulator.Described ground floor insulation film is SiO
2, Al
2O
3, La
2O
3, HfO
2, TiO
2Deng insulating material.Described ground floor conductive film is the metal materials such as Al, Co, Ti, Pt.Described second layer insulation film is SiO
2, Al
2O
3, La
2O
3, HfO
2, TiO
2, Si
3N
4Deng insulating material.Described second layer conductive film is metal, alloy or the polysilicon for adulterating.
The present invention combines quantum tunneling effect and a kind of gate control diode, adopts platform technology to produce grid-control metal-insulator semiconductor (MIS) diode based on quantum tunneling effect.By quantum effect device provided by the present invention is applied suitable bias voltage, can control its tunnelling efficient, reverse current is reduced to the degree that is far smaller than general-purpose diode, reduced chip power-consumption.
Description of drawings
Fig. 1 is the sectional view of an embodiment of the quantum effect device based on the metal-insulator semiconductor structure provided by the present invention.
Fig. 2 to Figure 10 is the process chart of an embodiment of manufacturing provided by the present invention quantum effect device as shown in Figure 1.
Embodiment
Below with reference to accompanying drawings an exemplary embodiment of the present invention is elaborated.In the drawings, for convenience of description, zoomed in or out the thickness in layer and zone, shown in size do not represent actual size.Although the actual size that reflects device that these figure can not entirely accurate, they or complete reflection zone and form mutual alignment between structure, particularly form up and down and neighbouring relations between structure.Expression in reference diagram is schematically, but this should not be considered to limit the scope of the invention.Simultaneously in the following description, the term substrate of using can be understood as and comprises the just Semiconductor substrate in processes, may comprise other prepared thin layer thereon.
Fig. 1 is the sectional view of an embodiment of the quantum effect device based on the metal-insulator semiconductor structure provided by the present invention.As shown in Figure 1, this quantum effect device is formed on silicon (SOI) substrate 200 on insulator, and SOI substrate 200 comprises thin monocrystalline silicon top layer 200a, thin insulator layer 200b and thick p-type layer-of-substrate silicon 200c.Metal level 202, tunneling insulation layer 201 consist of the MIS structure with substrate 200c, and gate insulation layer 203 covers substrate 200c and gate electrode 205 and described MIS structure are isolated.Metal level 204,206 is respectively drain electrode and the source electrode of device.
When drain electrode, grid, source electrode were applied respectively voltage 1v, 3v, 0v, silicon substrate 200c surface meeting transoid become N-shaped, and because source terminal pn knot is partially anti-, the pressure drop of pn knot is large, and tunnelling efficient is low, and reverse current is very little, and device is in cut-off state.
When drain electrode, grid, source electrode were applied respectively voltage 0v, 3v, 1v, silicon substrate 200c surface meeting transoid become N-shaped, and due to source terminal pn knot positively biased, tunnelling efficient is high, and forward current is large, and device is in conducting state.
When grid was applied voltage 0v, device was in the grid " shut " mode", if to drain electrode apply voltage 0v, source electrode applies voltage 1v, this moment, silicon substrate 200c side had the quantum state that can occupy, tunnelling current is little.If to drain electrode apply voltage 1v, source electrode applies voltage 0v, silicon substrate 200c side electron density is little, tunnelling current is little.
Quantum effect device based on the metal-insulator semiconductor structure disclosed in this invention can be by a lot of method manufacturings.It is following that what narrate is the manufacturing provided by the present invention technological process based on an embodiment of the quantum effect device of metal-insulator semiconductor structure as shown in Figure 1.Concrete steps are:
A Semiconductor substrate is provided;
Form the ground floor insulation film;
Form the ground floor conductive film;
Form ground floor photoresist and photoetching and form figure;
The described ground floor conductive film of etching;
The described ground floor insulation film of etching;
Divest the ground floor photoresist;
Form second layer photoresist and photoetching and form figure;
The described Semiconductor substrate of etched portions;
Divest second layer photoresist;
Form second layer insulation film;
Form the 3rd layer photoetching glue and photoetching and form figure;
The described second layer insulation film of etching forms contact hole;
Divest photoresist for the third time;
Form the described second layer conductive film of second layer conductive film and etching and form electrode.
Further describe below in conjunction with accompanying drawing:
At first, silicon (SOI) substrate 100 on insulator is provided, SOI substrate 100 comprises thin monocrystalline silicon top layer 100a, thin insulator layer 100b and thick p-type layer-of-substrate silicon 100c, then the thick tunnelling insulator layer 101 of deposit one deck 3-15nm on SOI substrate 100, tunnelling insulator layer 101 is such as being silicon dioxide, as shown in Figure 2.
Next, deposit layer of metal layer 102 on tunnelling insulator layer 101 is such as being titanium, as shown in Figure 3.
Next, deposit one deck photoresist and photoetching form figure, then etch away the metal level 102 of exposure, then continue etching tunnelling insulator layer 101 along remaining metal level 102.Divest photoresist that after photoresist, deposit one deck is new again and photoetching and form figure, then etched portions layer-of-substrate silicon 100c and divest photoresist after as shown in Figure 4, wherein Fig. 5 is that the A of structure shown in Figure 4 is to view.
Next, the gate insulator layer 103 that deposit one deck 5-20nm is thick is such as being silicon nitride, as shown in Figure 6.Then, deposit one deck photoresist and photoetching form figure, and then etching gate insulator layer 103 forms contact holes, divest after photoresist as shown in Figure 7, and wherein Fig. 8 is that the A of structure shown in Figure 7 is to view.
At last, deposit layer of metal 104, then deposit one deck photoresist and photoetching form image, then etching sheet metal 104 forms electrodes, divests after photoresist as shown in Figure 9, and wherein Figure 10 is that the A of structure shown in Figure 9 is to view.
As mentioned above, in the situation that do not depart from spirit and scope of the invention, can also consist of many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the instantiation described in specification.
Claims (6)
1. manufacture method based on the quantum effect device of metal-insulator semiconductor structure is characterized in that concrete steps comprise:
A Semiconductor substrate is provided;
Form the ground floor insulation film;
Form the ground floor conductive film;
The described ground floor conductive film of etching;
The described ground floor insulation film of etching;
Continue the described Semiconductor substrate of etched portions;
Form second layer insulation film;
The described second layer insulation film of etching forms contact hole;
Form second layer conductive film;
The described second layer conductive film of etching forms electrode;
Described quantum effect device based on the metal-insulator semiconductor structure comprises:
A Semiconductor substrate;
Be positioned at the source electrode that forms on described Semiconductor substrate;
Be positioned at the drain electrode that forms on described Semiconductor substrate;
Be positioned at the tunnelling insulator layer that described semiconductor substrate surface forms;
The metal level that forms between described drain electrode and described tunnelling insulator layer;
Described metal level, tunnelling insulator layer and described Semiconductor substrate consist of a MIS structure;
Be positioned at the grid that on described Semiconductor substrate, described MIS structure one side forms;
The gate insulator layer that forms between described MIS structure and described grid.
2. manufacture method according to claim 1, is characterized in that, described Semiconductor substrate is monocrystalline silicon, polysilicon or is the silicon on insulator.
3. manufacture method according to claim 1, is characterized in that, described ground floor insulation film is SiO
2, Al
2O
3, La
2O
3, HfO
2Or TiO
2Insulating material.
4. manufacture method according to claim 1, is characterized in that, described ground floor conductive film is Al, Co, Ti or Pt metal material.
5. manufacture method according to claim 5, is characterized in that, described second layer insulation film is SiO
2, Al
2O
3, La
2O
3, HfO
2, TiO
2Or Si
3N
4Insulating material.
6. manufacture method according to claim 1, is characterized in that, described second layer conductive film is metal, alloy or the polysilicon for adulterating.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110177230 CN102231391B (en) | 2011-06-28 | 2011-06-28 | Quantum-effect device based on MIS (Metal-Insulator-Semiconductor) structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110177230 CN102231391B (en) | 2011-06-28 | 2011-06-28 | Quantum-effect device based on MIS (Metal-Insulator-Semiconductor) structure |
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| CN102231391A CN102231391A (en) | 2011-11-02 |
| CN102231391B true CN102231391B (en) | 2013-06-12 |
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| CN102592997B (en) * | 2012-03-11 | 2014-08-06 | 复旦大学 | Manufacturing method of gate controlled diode semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101916783A (en) * | 2010-08-13 | 2010-12-15 | 复旦大学 | Transverse and longitudinal diffusion type field effect transistor of depressed channel and manufacturing method thereof |
| CN102097477A (en) * | 2010-12-15 | 2011-06-15 | 复旦大学 | MIS (metal-insulator-semiconductor) and MIM (metal-insulator-metal) device provided with gate |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57130469A (en) * | 1981-02-05 | 1982-08-12 | Seiko Epson Corp | Mis type semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101916783A (en) * | 2010-08-13 | 2010-12-15 | 复旦大学 | Transverse and longitudinal diffusion type field effect transistor of depressed channel and manufacturing method thereof |
| CN102097477A (en) * | 2010-12-15 | 2011-06-15 | 复旦大学 | MIS (metal-insulator-semiconductor) and MIM (metal-insulator-metal) device provided with gate |
Non-Patent Citations (1)
| Title |
|---|
| JP昭57-130469A 1982.08.12 |
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