CN102222686A - Fence-type grid-controlled metal-insulator device based on electronic tunneling - Google Patents

Fence-type grid-controlled metal-insulator device based on electronic tunneling Download PDF

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Publication number
CN102222686A
CN102222686A CN2011101772265A CN201110177226A CN102222686A CN 102222686 A CN102222686 A CN 102222686A CN 2011101772265 A CN2011101772265 A CN 2011101772265A CN 201110177226 A CN201110177226 A CN 201110177226A CN 102222686 A CN102222686 A CN 102222686A
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grid
type
semiconductor substrate
layer
insulator
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CN2011101772265A
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Chinese (zh)
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林曦
王玮
王鹏飞
孙清清
张卫
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Fudan University
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Fudan University
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Priority to CN2011101772265A priority Critical patent/CN102222686A/en
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Abstract

The invention belongs to the technical field of quantum effect device, and particularly relates to a fence-type grid-controlled metal-insulator device based on electronic tunneling. The device comprises a semiconductor substrate, and a source electrode, a drain electrode, a source doping region, a tunneling insulator layer and a metal layer positioned on the semiconductor substrate; an MIS (Management Information System) structure consists of the metal layer, the tunneling insulator layer and the semiconductor substrate; and the device further comprises a grid insulator layer and a grid electrode positioned on the grid insulator layer for surrounding the MIS structure in a circle. In the invention, the fence-type grid-controlled metal-insulator device based on electronic tunneling effect is manufactured with platform technology, and the grid electrode surrounds the metal-insulator structure in a circle for enhancing the control ability of the grid electrode; and simultaneously, proper bias voltage is applied on the fence-type grid-controlled metal-insulator device so as to control the tunneling efficiency, decrease the leakage current and improve the sub-threshold swing amplitude performance.

Description

Enclose grid type grid-control metal-insulator device based on electron tunneling
Technical field
The invention belongs to quantum effect device technology field, be specifically related to a kind ofly enclose grid type grid-control metal-insulator device based on electron tunneling.
Background technology
In recent years, be that the microelectric technique of core has obtained development rapidly with the silicon integrated circuit.Integrated level is followed Moore's Law basically as one of important indicator of weighing the integrated circuit development, and promptly the integrated level of semiconductor chip is with per speed increment of doubling in 18 months, and this requires size of devices constantly to dwindle.Constantly dwindling in the process of feature sizes of semiconductor devices, when the chip feature size was in micro-meter scale, electronics wherein mainly was corpuscular property in wave-particle duality, and present most of semiconductor device have only utilized the corpuscular property of electronics; When the chip feature size is in nanoscale, especially grow or the mean free path of electronics can be compared or more hour when the moral cloth Glass of characteristic size and electronics, electronics wherein mainly is fluctuation in wave-particle duality, this The Wave Behavior of Electrons is exactly a kind of quantum effect.The energy that so-called quantum effect is an electronics is by quantization, and electronic motion suffers restraints on certain direction.
Tunneling effect also makes potential barrier run through, and according to classical theory, gross energy is lower than potential barrier can not realization response.But according to the quantum mechanics viewpoint, no matter whether particle energy is higher than potential barrier, can not affirm that all whether particle can cross potential barrier, can only say the size that particle is crossed the potential barrier probability.It depends on the energy of barrier height, width and particle itself.Energy be higher than potential barrier, the direction of motion is suitable may not necessarily react, and can only say that reaction probability is bigger.And energy is lower than the certain probability realization response of still having of potential barrier, promptly may some particle passes through potential barrier as passing through from the mountain tunnel, Here it is tunneling effect.
Along with further developing of integrated circuit (IC)-components technology, size of semiconductor device is more and more littler, thing followed short-channel effect is also obvious further, leakage current rises gradually, quantum tunneling effect plays more and more important effect in the work of semiconductor device, therefore also become the focus of current research based on the semiconductor device of quantum tunneling effect.
Summary of the invention
The objective of the invention is to propose a kind of new semiconductor device, to improve the performance of semiconductor device based on quantum tunneling effect.
For reaching above-mentioned purpose of the present invention, the present invention proposes a kind of based on electron tunneling enclose grid type grid-control metal-insulator device, specifically comprise:
Semiconductor substrate with first kind of doping type;
Be positioned at the source electrode that forms on the described Semiconductor substrate;
Be positioned at the drain electrode that forms on the described Semiconductor substrate;
Be positioned at the source dopant region with second kind doping type of described Semiconductor substrate near source electrode;
Be positioned at the tunnelling insulator layer that described semiconductor substrate surface forms;
Be positioned at the metal level that forms on the tunnelling insulator layer;
Described metal level, tunnelling insulator layer and described Semiconductor substrate constitute a MIS(metal-insulator semiconductor) structure;
Cover the gate insulator layer that described Semiconductor substrate and described MIS structure form;
Be positioned at the grid that forms around described one week of MIS structure on the described gate insulator layer.
Simultaneously, the invention allows for the above-mentioned manufacture method of enclosing grid type grid-control metal-insulator device based on quantum tunneling effect, concrete steps comprise:
Concrete steps comprise:
Semiconductor substrate with first kind of doping type is provided;
Form the ground floor insulation film;
Form the ground floor conductive film;
The described ground floor conductive film of etching;
The described ground floor insulation film of etching;
Continue the described Semiconductor substrate of etched portions;
Carry out ion and inject, in described Semiconductor substrate, form doped region with second kind of doping type;
Form second layer insulation film;
The described second layer insulation film of etching forms contact hole;
Form second layer conductive film;
The described second layer conductive film of etching forms electrode.
Further, described Semiconductor substrate is monocrystalline silicon, polysilicon or is the silicon (SOI) on the insulator.Described ground floor insulation film is SiO 2, Al 2O 3, La 2O 3, HfO 2Or TiO 2Deng insulating material.Described ground floor conductive film is metal materials such as Al, Co, Ti or Pt.Described second layer insulation film is SiO 2, Al 2O 3, La 2O 3, HfO 2, TiO 2Or Si 3N 4Deng insulating material.Described second layer conductive film is metal, alloy or the polysilicon for mixing.
Further, described first kind of doping type is the n type, and described second kind of doping type is the p type, and perhaps described first kind of doping type is the p type, and described second kind of doping type is the n type.
The present invention adopts platform technology to make to enclose grid type grid-control metal-insulator device based on quantum tunneling effect, employing is enclosed grid type grid device is controlled, strengthened the control ability of grid, simultaneously, by the grid type grid-control metal-insulator device that encloses provided by the present invention is applied suitable bias voltage, can control its tunnelling efficient, reduce reverse current, improve subthreshold value amplitude of oscillation performance.
Description of drawings
Fig. 1 is the sectional view of the embodiment who encloses grid type grid-control metal-insulator device based on quantum tunneling effect provided by the present invention.
Fig. 2 is that the A of structure shown in Figure 1 is to view.
Fig. 3 to Figure 10 is the process chart of a manufacturing provided by the present invention embodiment who encloses grid type grid-control metal-insulator device as shown in Figure 1.
Embodiment
Below with reference to accompanying drawings an exemplary embodiment of the present invention is elaborated.In the drawings, for convenience of description, amplify or dwindled the thickness in layer and zone, shown in size do not represent actual size.Although the actual size that reflects device that these figure can not entirely accurate, their zones that still has been complete reflection and form mutual alignment between the structure, particularly form between the structure up and down and neighbouring relations.Expression in the reference diagram is schematically, but this should not be considered to limit the scope of the invention.Simultaneously in the following description, employed term substrate can be understood as and comprises the just Semiconductor substrate in processes, may comprise other prepared thin layer thereon.
Fig. 1 is the sectional view of the embodiment who encloses grid type grid-control metal-insulator device based on quantum tunneling effect provided by the present invention, and Fig. 2 is that the A of structure shown in Figure 1 is to view.As shown in Figure 1, this encloses grid type grid-control metal-insulator device and is formed on silicon (SOI) substrate 100 on the insulator, and SOI substrate 100 comprises thin monocrystalline silicon top layer 100a, thin insulator layer 100b and thick p type layer-of-substrate silicon 100c.Metal level 102, tunneling insulation layer 101 constitute the MIS structure with layer-of-substrate silicon 100c, gate insulator layer 104 covers layer-of-substrate silicon 100c and described MIS structure, grid 106 is positioned on the described gate insulator layer 104 and around described one week of MIS structure, is used to strengthen the control ability of grid.Metal level 105,107 is respectively the drain electrode and the source electrode of device, is formed with n type doped region 103 near source electrode 107 places in layer-of-substrate silicon 100c.
When drain electrode, grid, source electrode were applied voltage 0v, 3v, 1v respectively, p type layer-of-substrate silicon 100c surface can transoid become the n type, and device is in conducting state.
When grid was applied voltage 0v, device was in the grid " shut " mode", if to drain electrode apply voltage 0v, source electrode applies voltage 1v, then silicon substrate 100c side has the quantum state that can occupy, pn knot is partially anti-, tunnelling current is little.If to drain electrode apply voltage 1v, source electrode applies voltage 0v, then layer-of-substrate silicon 200c side electron density is little, tunnelling current is little.
Disclosed in this invention based on quantum tunneling effect enclose grid type grid-control metal-insulator device can be by a lot of method manufacturings.It is following that what narrate is the manufacturing provided by the present invention technological process based on the embodiment who encloses grid type grid-control metal-insulator device of quantum tunneling effect as shown in Figure 1.The steps include:
Semiconductor substrate with first kind of doping type is provided;
Form the ground floor insulation film;
Form the ground floor conductive film;
Form ground floor photoresist and photoetching and form figure;
The described ground floor conductive film of etching;
The described ground floor insulation film of etching;
Divest the ground floor photoresist;
Form second layer photoresist and photoetching and form figure;
The described Semiconductor substrate of etched portions;
Divest second layer photoresist;
Form the 3rd layer photoetching glue and photoetching and form figure;
Carry out ion and inject the doped region that formation has second kind of doping type;
Divest the 3rd layer photoetching glue;
Form second layer insulation film;
Form the 4th layer photoetching glue and photoetching and form figure;
The described second layer insulation film of etching forms contact hole;
Divest the 4th layer photoetching glue;
Form the described second layer conductive film of second layer conductive film and etching and form electrode.
Further describe as follows below in conjunction with accompanying drawing:
At first, silicon (SOI) substrate 200 on the insulator is provided, SOI substrate 200 comprises thin monocrystalline silicon top layer 200a, thin insulator layer 200b and thick p type layer-of-substrate silicon 200c, follow deposit one deck tunnelling insulator layer 201 on SOI substrate 200, tunnelling insulator layer 201 is such as being silicon dioxide, deposit layer of metal layer 202 on tunnelling insulator layer 201 then is such as being titanium, as shown in Figure 3.
Next, deposit one deck photoresist and photoetching form figure, etch away the metal level 202 of exposure then, then continue to etch away the tunnelling insulator layer 201 of exposure.Divest deposit one deck is new again behind the photoresist photoresist and photoetching and form figure, then etched portions layer-of-substrate silicon 200c and divest photoresist after as shown in Figure 4, wherein Fig. 5 is that the A of structure shown in Figure 4 is to view.
Next, deposit one deck photoresist and photoetching form figure, carry out ion then and inject and form n type doped region 203, divest behind the photoresist as shown in Figure 6.
Next, deposit gate insulator layer 204 is such as being silicon nitride.Then, deposit one deck photoresist and photoetching form figure, and etching gate insulator layer 204 forms contact holes then, divest behind the photoresist as shown in Figure 7, and wherein Fig. 8 is that the A of structure shown in Figure 7 is to view.
At last, deposit layer of metal 205, deposit one deck photoresist and photoetching form image again, and etching sheet metal 205 forms electrodes then, divests behind the photoresist as shown in Figure 9, and wherein Figure 10 is that the A of structure shown in Figure 9 is to view.
As mentioned above, under the situation that does not depart from spirit and scope of the invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the instantiation described in the specification.

Claims (12)

  1. One kind based on electron tunneling enclose grid type grid-control metal-insulator device, comprising:
    Semiconductor substrate with first kind of doping type;
    Be positioned at the source electrode that forms on the described Semiconductor substrate;
    Be positioned at the drain electrode that forms on the described Semiconductor substrate;
    Be positioned at the source dopant region with second kind doping type of described Semiconductor substrate near source electrode;
    Be positioned at the tunnelling insulator layer that described semiconductor substrate surface forms;
    Be positioned at the metal level that forms on the tunnelling insulator layer;
    Described metal level, tunnelling insulator layer and described Semiconductor substrate constitute a MIS structure;
    It is characterized in that, also comprise:
    Cover the gate insulator layer that described Semiconductor substrate and described MIS structure form;
    Be positioned at the grid that forms around described one week of MIS structure on the described gate insulator layer.
  2. 2. the grid type grid-control metal-insulator device that encloses according to claim 1 is characterized in that described tunnelling insulator layer is by SiO 2, Al 2O 3, La 2O 3, HfO 2Or TiO 2Insulating material forms.
  3. 3. the grid type grid-control metal-insulator device that encloses according to claim 1 is characterized in that described metal level is formed by Al, Co, Ti or Pt metal material.
  4. 4. the grid type grid-control metal-insulator device that encloses according to claim 1 is characterized in that described gate insulator layer is by SiO 2, Al 2O 3, La 2O 3, HfO 2, TiO 2Or Si 3N 4Insulating material forms.
  5. 5. the grid type grid-control metal-insulator device that encloses according to claim 1, it is characterized in that described first kind of doping type is the n type, described second kind of doping type is the p type, perhaps described first kind of doping type is the p type, and described second kind of doping type is the n type.
  6. 6. manufacture method of enclosing grid type grid-control metal-insulator device based on electron tunneling is characterized in that concrete steps comprise:
    Semiconductor substrate with first kind of doping type is provided;
    Form the ground floor insulation film;
    Form the ground floor conductive film;
    The described ground floor conductive film of etching;
    The described ground floor insulation film of etching;
    Continue the described Semiconductor substrate of etched portions;
    Carry out ion and inject, in described Semiconductor substrate, form doped region with second kind of doping type;
    Form second layer insulation film;
    The described second layer insulation film of etching forms contact hole;
    Form second layer conductive film;
    The described second layer conductive film of etching forms electrode.
  7. 7. manufacture method according to claim 6 is characterized in that, described Semiconductor substrate is monocrystalline silicon, polysilicon or is the silicon on the insulator.
  8. 8. manufacture method according to claim 6 is characterized in that, described ground floor insulation film is SiO 2, Al 2O 3, La 2O 3, HfO 2Or TiO 2Insulating material.
  9. 9. manufacture method according to claim 6 is characterized in that, described ground floor conductive film is Al, Co, Ti or Pt metal material.
  10. 10. manufacture method according to claim 6 is characterized in that, described second layer insulation film is SiO 2, Al 2O 3, La 2O 3, HfO 2, TiO 2Or Si 3N 4Insulating material.
  11. 11. manufacture method according to claim 6 is characterized in that, described second layer conductive film is metal, alloy or the polysilicon for mixing.
  12. 12. manufacture method according to claim 6 is characterized in that, described first kind of doping type is the n type, and described second kind of doping type is the p type, and perhaps described first kind of doping type is the p type, and described second kind of doping type is the n type.
CN2011101772265A 2011-06-28 2011-06-28 Fence-type grid-controlled metal-insulator device based on electronic tunneling Pending CN102222686A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100163845A1 (en) * 2008-12-30 2010-07-01 Niti Goel Tunnel field effect transistor and method of manufacturing same
CN102097477A (en) * 2010-12-15 2011-06-15 复旦大学 MIS (metal-insulator-semiconductor) and MIM (metal-insulator-metal) device provided with gate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100163845A1 (en) * 2008-12-30 2010-07-01 Niti Goel Tunnel field effect transistor and method of manufacturing same
CN102097477A (en) * 2010-12-15 2011-06-15 复旦大学 MIS (metal-insulator-semiconductor) and MIM (metal-insulator-metal) device provided with gate

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Application publication date: 20111019