CN102214659B - Nonvolatile memory and manufacture method thereof - Google Patents
Nonvolatile memory and manufacture method thereof Download PDFInfo
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- CN102214659B CN102214659B CN201110142037.4A CN201110142037A CN102214659B CN 102214659 B CN102214659 B CN 102214659B CN 201110142037 A CN201110142037 A CN 201110142037A CN 102214659 B CN102214659 B CN 102214659B
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Abstract
The present invention relates to a kind of nonvolatile memory and manufacture method thereof.Described nonvolatile memory comprises: substrate; Be partially submerged in described substrate two construction units be separated, each construction unit comprises couplant and described floating boom described in the couplant, floating boom, spacer medium, Supporting Media and the sidewall that set gradually and embeds in described substrate; Be filled in the coupling transmitting medium between described two construction units be separated, floating boom described in described couplant, spacer medium and side walls enclose, described floating boom is isolated with the described transmitting medium that is coupled; Be positioned at the tunnel dielectric of the substrate surface outside described construction unit; Be positioned at the control gate in described tunnel dielectric, described control gate and described floating boom are isolated.Nonvolatile memory structure of the present invention is simple, easy to make, is conducive to the size further reducing memory cell.
Description
Technical field
The present invention relates to a kind of nonvolatile memory and manufacture method thereof, particularly a kind of nonvolatile memory of gate-distribution embedding type floating gate and manufacture method thereof.
Background technology
Nonvolatile memory (Non-VolatileMemory, NVM) be a kind of memory cell with mos transistor structure, because of have can repeatedly carry out data stored in, read, the characteristic such as to erase, and stored in data also can not disappear after power is turned off, therefore, be widely used in personal computer and electronic equipment.But along with semiconductor subassembly develops gradually towards miniaturization, the size of memory also reduces along with live width and reduces, and the related coupling efficiency of the source electrode in non-volatility memorizer to floating grid that make significantly reduces.
Usually, nonvolatile memory generally comprises source region, drain region, channel region, control gate and floating boom.Floating gate structure is MOS transistor and the topmost difference of common MOS transistor of non-volatile memory cells, it plays the effect of stored charge in this memory cell structure, make memory cell in the event of a power failure, still can keep the information stored more, thus make this memory have non-volatile feature.At present, the floating gate structure of nonvolatile memory comprises folded grid and grid dividing structure.
As shown in Figure 1, be the structural representation of the nonvolatile memory of existing a kind of grid dividing structure.Described nonvolatile memory comprises: Semiconductor substrate 10; Be positioned at two construction units be separated in Semiconductor substrate 10.Described construction unit comprises the couplant layer 11 be positioned at successively in Semiconductor substrate 10, floating boom 12, spacer medium layer 13 and supporting medium layer 14, and wherein said floating boom 12 lateral surface is angular shape; Source electrode 17 in Semiconductor substrate 10 between two construction units be separated; Be positioned at the first side wall layer 15 of two couplant layers 11 be separated, floating boom 12, spacer medium layer 13 madial wall; Fill the coupling conducting shell 16 in the gap between two construction units be separated; Be positioned on two construction unit lateral walls and described construction unit outer semiconductor substrate 10 be separated, the tunnel dielectric layer 18 in L-type; Be positioned at the control gate 19 outside L-type tunnel dielectric layer 18; Be positioned at the drain electrode 20 of control gate 19 outer semiconductor substrate 10.
Along with diminishing of nonvolatile memory size, the size of floating boom also diminishes thereupon, and when other conditions are constant, source electrode reduces the coupling area of floating boom, thus affect the ability of non-volatile memory cell programming, cause non-volatile memory cells hydraulic performance decline.
Summary of the invention
The object of the present invention is to provide a kind of nonvolatile memory that can solve the problem.
Another object of the present invention is to the manufacture method that a kind of above-mentioned nonvolatile memory is provided.
A kind of nonvolatile memory, comprising: substrate; Be partially submerged into two construction units be separated in described substrate, each construction unit comprises couplant, floating boom, spacer medium, Supporting Media and sidewall, described couplant, floating boom, spacer medium, Supporting Media set gradually, described couplant and described floating boom embed in described substrate, described sidewall be arranged at described two be separated construction units between and attach described couplant, floating boom, spacer medium, Supporting Media; Coupling transmitting medium, described coupling transmitting medium is filled between described two construction units be separated, floating boom described in described couplant, spacer medium and side walls enclose, and described floating boom is isolated with the described transmitting medium that is coupled; Be positioned at the tunnel dielectric of the substrate surface outside described construction unit; Be positioned at the control gate in described tunnel dielectric, described control gate and described floating boom are isolated.
The preferred a kind of technical scheme of above-mentioned nonvolatile memory, described nonvolatile memory also comprises the source electrode between two described construction units being arranged in described substrate.
The preferred a kind of technical scheme of above-mentioned nonvolatile memory, described nonvolatile memory also comprises the drain electrode be positioned at outside described control gate be arranged in described substrate.
The preferred a kind of technical scheme of above-mentioned nonvolatile memory, the surface of described floating boom is higher than the surface of described substrate.
The preferred a kind of technical scheme of above-mentioned nonvolatile memory, described sidewall attaches the described Supporting Media of described couplant, floating boom, spacer medium and part.
A manufacture method for nonvolatile memory, comprises the steps: the etching barrier layer with opening forming substrate and be positioned at described substrate surface; With described etching barrier layer for mask, etch described substrate, in described substrate, form groove, form couplant layer at described trench wall, be embedded in floating boom at described couplant layer; Spacer medium layer is formed at the opening sidewalls of described etching barrier layer and the surface of described floating boom; Two the supporting dielectric layers be separated being positioned at described spacer medium layer surface are formed at described opening sidewalls; With described etching barrier layer and described supporting medium layer for mask, etch described spacer medium layer, floating boom and couplant layer and form two construction units be separated; The side wall layer attaching described couplant layer, floating boom, spacer medium layer, supporting medium layer is formed between described two construction units be separated; Between described two construction units be separated, fill coupling conducting shell, described floating boom is isolated with the described conducting shell that is coupled; Remove described etching barrier layer, the substrate surface outside described construction unit forms tunnel dielectric layer; Formation control grid in described tunnel dielectric layer, described control gate and described floating boom are isolated.
The preferred a kind of technical scheme of said method, etch after described spacer medium layer, floating boom and couplant layer form two construction units be separated, with described etching barrier layer and described supporting medium layer for mask, in described substrate, carry out ion implantation, form the source electrode of the memory cell of described nonvolatile memory.
The preferred a kind of technical scheme of said method, in described tunnel dielectric layer after formation control grid, carries out ion implantation in the substrate outside described control gate, forms the drain electrode of the memory cell of described nonvolatile memory.
The preferred a kind of technical scheme of said method, the material of at least one in described floating boom, control gate, supporting medium layer and coupling conducting shell is polysilicon.
The preferred a kind of technical scheme of said method, the material of at least one in described couplant layer, spacer medium layer, side wall layer and tunnel dielectric layer is silica.
Compared with prior art, floating boom is imbedded in substrate by nonvolatile memory of the present invention, increases charge carrier move distance between the source and drain, thus is conducive to the coverage increasing raceway groove, avoids the short-channel effect of the metal-oxide-semiconductor under small size.And the structure of the nonvolatile memory of the floating boom of this flush type is simple, easy to make, be conducive to the size further reducing memory cell.
Accompanying drawing explanation
Fig. 1 is a kind of structural representation of nonvolatile memory of grid dividing structure of prior art.
Fig. 2 is the structural representation of nonvolatile memory of the present invention.
Fig. 3 to Figure 14 is the schematic diagram step by step of the manufacture method of nonvolatile memory of the present invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail.
Refer to Fig. 2, Fig. 2 is the structural representation of nonvolatile memory of the present invention.Described nonvolatile memory comprises substrate 21, be partially submerged into two construction units be separated in described substrate 21, be arranged at the source electrode 27 between two described construction units in described substrate 21, be filled in the coupling transmitting medium 29 between described two construction units be separated, be arranged at the tunnel dielectric 30 on substrate 21 surface outside described construction unit, be arranged at the control gate 31 in described tunnel dielectric 30 and be arranged at the drain electrode 32 be positioned at outside described control gate 31 in described substrate 21.
Each construction unit comprises couplant 23, floating boom 24, spacer medium 25, Supporting Media 26 and sidewall 28.Described couplant 23, floating boom 24, spacer medium 25, Supporting Media 26 set gradually from below to up.Described couplant 23 and described floating boom 24 embed in described substrate 21.Described sidewall 28 be arranged at described two be separated construction units between and attach described couplant 23, floating boom 24, spacer medium 25, Supporting Media 26.Preferably, the surface of described floating boom 24 is higher than the surface of described substrate 21.Described sidewall 28 attaches the described Supporting Media 26 of part.Described couplant 23, spacer medium 25 and sidewall 28 surround described floating boom 24, thus described floating boom 24 is isolated with the described transmitting medium 29 that is coupled, control gate 31.Described Supporting Media 26 is identical or similar with the material of described coupling transmitting medium 29, both are made to connect, thus play the object improving coupling efficiency, preferably, described Supporting Media 26 and the material of the described conducting shell 29 that is coupled are the polysilicon of the polysilicon that adulterates of N-type or P type or doping metals impurity.
Below in conjunction with Fig. 3 to Figure 14, describe the manufacture method of above-mentioned nonvolatile memory step by step in detail:
There is provided substrate 21, deposition-etch barrier layer 22 on described substrate 21, described etching barrier layer 22 forms opening, as shown in Figure 3.Preferably, the material of described substrate 21 is silicon or the SiGe (SiGe) of monocrystalline, polycrystalline or non crystalline structure, and also can be isolate supports (SOI), the material of described etching barrier layer 22 be silicon nitride.Be formed with the isolation structure for isolating active area in described substrate 21, described isolation structure is fleet plough groove isolation structure (STI) preferably.Namely a memory cell (Cell) of nonvolatile memory of the present invention is formed between two adjacent groove structures.The technique that described etching barrier layer 22 is formed opening can be any one prior art well known to those skilled in the art, is not described in detail at this.
With described etching barrier layer 22 for mask, etch described substrate 21, in described substrate 21, form groove.Form couplant layer 23 at described formation inwall, be embedded in floating boom 24 at described couplant layer 23, as shown in Figure 4.Described couplant layer 23 is for substrate described in electric insulation 21 and described floating boom 24, and material can be silica or silicon oxynitride (SiNO) or hafnium oxide or aluminium oxide or zirconia.The manufacture craft of described couplant layer 23 can be chemical vapour deposition (CVD) (CVD), plasma enhanced chemical vapor deposition (PECVD) technique or thermal oxidation method etc.Etch described substrate 21 form the technique of groove can for dry etching, the gash depth of formation be slightly less than described couplant layer 23 and described floating boom 24 thickness and, namely the surface of described floating boom 24 is higher than the surface of described substrate 21.The material of described floating boom 24 can be the polysilicon of polysilicon or doping metals impurity.The method forming described floating boom 24 comprises chemical vapour deposition (CVD), physical vapour deposition (PVD) (PVD), plasma enhanced chemical vapor deposition processes.Usually, after employing chemical vapor deposition method deposits described floating boom 24, also CMP (Chemical Mechanical Polishing) process to be carried out, to remove the floating gate portion on groove top to described floating boom 24.
Spacer medium layer 25 is formed, as shown in Figure 5 at the opening sidewalls of described etching barrier layer 22 and the surface of described floating boom 24.Described spacer medium layer 25 is for isolating described floating boom 24.Described spacer medium layer 25 be insulating material, preferably, be any one in silica, silicon nitride, silicon oxynitride, hafnium oxide, aluminium oxide or zirconia or several combination, manufacture craft can adopt chemical vapour deposition technique.
Two the supporting dielectric layers 26 be separated being positioned at described spacer medium layer 25 surface are formed, as shown in Figure 6 at described opening sidewalls.Preferably, the circumference of described supporting dielectric layer 26 is arc, in its technique and semiconductor technology, the formation process of side wall is similar to, such as, deposition of insulative material in described opening, then adopts plasma etching industrial to etch described insulating material, carry out chemical etching and physical bombardment in described plasma etch process simultaneously, remove the insulating material of open intermediary portion, after etching technics completes, curved support medium 26 will be formed at two of an opening sidewall.Preferably, the material of described Supporting Media 26 is the polysilicon of N-type or the doping of P type or the polysilicon of doping metals impurity.
With described etching barrier layer 22 and described supporting medium layer 26 for mask, etch described spacer medium layer 25, floating boom 24 and couplant layer 23 until expose channel bottom to form two construction units be separated, as shown in Figure 7.Described etching technics can be dry plasma etch or reactive ion etching, also can select the technology well known in the art such as wet-etching technology, be not described in detail at this.
With described etching barrier layer 22 and described supporting medium layer 26 for mask, in described substrate 21, carry out ion implantation, form the source electrode 27 of the memory cell of described nonvolatile memory, as shown in Figure 8.Described ion can for comprising the ion of the 3rd major element or the 5th major element, such as boron ion, phosphonium ion, arsenic ion, boron fluoride ion etc.According to the doping type of trap in substrate 21 and the type of described nonvolatile memory, different Doped ions can be chosen.Concrete injection technology also can adjust according to the needs of technological design.
The side wall layer 28 attaching described couplant layer 23, floating boom 24, spacer medium layer 25, supporting medium layer 26 is formed, as shown in Figure 9 between described two construction units be separated.Described couplant layer 23, spacer medium layer 25 and side wall layer 28 surround described floating boom 24 to isolate described floating boom 24.The material of described side wall layer 28 is any one in silica, silicon nitride, silicon oxynitride or several combination.Preferably, described side wall layer 28 attaches the described supporting medium layer 26 of part, namely perpendicular in orientation, the height of described side wall layer 28 is greater than the height of described couplant layer 23, floating boom 24, spacer medium layer 25, but is less than the height of described couplant layer 23, floating boom 24, spacer medium layer 25, supporting medium layer 26.
Coupling conducting shell 29 is filled, as shown in Figure 10 between described two construction units be separated.Described coupling conducting shell 29 is in electrical contact with described source electrode 27.Because described couplant layer 23, spacer medium layer 25 and side wall layer 28 surround described floating boom 24, described coupling conducting shell 29 is isolated with described floating boom 24.The material of described coupling conducting shell 29 is the polysilicon of N-type or the doping of P type or the polysilicon of doping metals impurity, its doping type is identical with the doping type of substrate 21 and floating boom 24 in principle, manufacture craft first can adopt the polycrystalline silicon material of filling doping in the gap of chemical vapor deposition method between two construction units be separated, adopt polycrystalline silicon material described in CMP process subsequently, until exposed portion supporting medium layer 26.Described Supporting Media 26 is identical or similar with the material of described coupling transmitting medium 29, makes both connect, thus plays the object improving coupling efficiency.
Remove described etching barrier layer 22, as shown in figure 11.The technique removing described etching barrier layer 22 can for adopting wet-etching technology, and the etching agent that described wet etching adopts can be hot phosphoric acid.
Substrate 21 surface outside described construction unit forms tunnel dielectric layer 30, as shown in figure 12.Described tunnel dielectric layer 30 is insulating material, preferably, is silica.Described tunnel dielectric layer 30 as the tunnel dielectric layer of the nonvolatile memory of gate-distribution embedding type floating gate, to realize the programming operations such as the read-write of memory.
Formation control grid 31 in described tunnel dielectric layer 30, described control gate 31 is isolated with described substrate 21 by described tunnel dielectric layer 30.Preferably, the material of described control gate 31 is the polysilicon of polysilicon or doping metals impurity.The method of formation control grid 31 can be any prior art well known to those skilled in the art, as first adopted chemical vapor deposition method deposit spathic silicon in tunnel dielectric layer 30, adopting plasma etching industrial to remove partial polysilicon subsequently and forming described control gate 31.
Carry out ion implantation in substrate 21 outside described control gate 31, form the drain electrode 32 of the memory cell of described nonvolatile memory.The technique of described formation drain electrode 32 can be any prior art well known to those skilled in the art, can the formation process of reference source 27, is not described in detail at this.
Compared with prior art, floating boom 24 is imbedded in substrate 21 by nonvolatile memory of the present invention, increase the move distance of charge carrier between source electrode 27 and drain electrode 32, thus be conducive to the coverage increasing raceway groove, avoid the short-channel effect of the metal-oxide-semiconductor under small size.And the structure of the nonvolatile memory of the floating boom of this flush type is simple, easy to make, be conducive to the size further reducing memory cell.
Many embodiments having very big difference can also be formed when without departing from the spirit and scope of the present invention.Should be appreciated that except as defined by the appended claims, the invention is not restricted to specific embodiment described in the description.
Claims (9)
1. a nonvolatile memory, is characterized in that, comprising:
Substrate;
Be partially submerged into two construction units be separated in described substrate, each construction unit comprises couplant, floating boom, spacer medium, Supporting Media and sidewall, described couplant, floating boom, spacer medium, Supporting Media set gradually, described couplant and described floating boom embed in described substrate, the surface of described floating boom is higher than the surface of described substrate, and described sidewall to be arranged between described two construction units be separated and to attach described couplant, floating boom, spacer medium, Supporting Media;
Coupling transmitting medium, described coupling transmitting medium is filled between described two construction units be separated, floating boom described in described couplant, spacer medium and side walls enclose, and described floating boom is isolated with the described transmitting medium that is coupled;
Tunnel dielectric, described tunnel dielectric is positioned at the surface of the substrate outside described construction unit;
Control gate, described control gate is positioned in described tunnel dielectric, and described control gate and described floating boom are isolated.
2. nonvolatile memory as claimed in claim 1, is characterized in that, described nonvolatile memory also comprises and being arranged in described substrate and source electrode between two described construction units.
3. nonvolatile memory as claimed in claim 1, is characterized in that, described nonvolatile memory also comprises and being arranged in described substrate and the drain electrode be positioned at outside described control gate.
4. nonvolatile memory as claimed in claim 1, it is characterized in that, described sidewall attaches the described Supporting Media of described couplant, floating boom, spacer medium and part.
5. a manufacture method for nonvolatile memory, is characterized in that, comprises the steps:
Form substrate and be positioned at the etching barrier layer with opening of described substrate surface;
With described etching barrier layer for mask, etch described substrate, in described substrate, form groove, form couplant layer at described trench wall, be embedded in floating boom at described couplant layer;
Spacer medium layer is formed at the opening sidewalls of described etching barrier layer and the surface of described floating boom;
Two supporting medium layer be separated being positioned at described spacer medium layer surface are formed at described opening sidewalls;
With described etching barrier layer and described supporting medium layer for mask, etch described spacer medium layer, floating boom and couplant layer and form two construction units be separated, the surface of described floating boom is higher than the surface of described substrate;
The side wall layer attaching described couplant layer, floating boom, spacer medium layer, supporting medium layer is formed between described two construction units be separated;
Between described two construction units be separated, fill coupling conducting shell, described floating boom is isolated with the described conducting shell that is coupled;
Remove described etching barrier layer, the substrate surface outside described construction unit forms tunnel dielectric layer;
Formation control grid in described tunnel dielectric layer, described control gate and described floating boom are isolated.
6. the manufacture method of nonvolatile memory as claimed in claim 5, it is characterized in that, etch after described spacer medium layer, floating boom and couplant layer form two construction units be separated, with described etching barrier layer and described supporting medium layer for mask, in described substrate, carry out ion implantation, form the source electrode of the memory cell of described nonvolatile memory.
7. the manufacture method of nonvolatile memory as claimed in claim 5, it is characterized in that, in described tunnel dielectric layer after formation control grid, in the substrate outside described control gate, carry out ion implantation, form the drain electrode of the memory cell of described nonvolatile memory.
8. the manufacture method of nonvolatile memory as claimed in claim 5, it is characterized in that, the material of at least one in described floating boom, control gate, supporting medium layer and coupling conducting shell is polysilicon.
9. the manufacture method of nonvolatile memory as claimed in claim 5, it is characterized in that, the material of at least one in described couplant layer, spacer medium layer, side wall layer and tunnel dielectric layer is silica.
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| CN101770991A (en) * | 2010-01-12 | 2010-07-07 | 上海宏力半导体制造有限公司 | Nonvolatile memory of gate-distribution embedding type floating gate and manufacturing method thereof |
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| US6706592B2 (en) * | 2002-05-14 | 2004-03-16 | Silicon Storage Technology, Inc. | Self aligned method of forming a semiconductor array of non-volatile memory cells |
| KR20070019351A (en) * | 2005-08-12 | 2007-02-15 | 삼성전자주식회사 | Non-Volatile Memory Device And Method Of Fabricating The Same |
| CN101667581B (en) * | 2009-09-09 | 2012-04-11 | 上海宏力半导体制造有限公司 | Separated grid type embedded layer float grid nonvolatile storage unit and manufacturing method thereof |
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