CN102214659A - NVM (nonvolatile memory) and manufacturing method thereof - Google Patents
NVM (nonvolatile memory) and manufacturing method thereof Download PDFInfo
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- CN102214659A CN102214659A CN2011101420374A CN201110142037A CN102214659A CN 102214659 A CN102214659 A CN 102214659A CN 2011101420374 A CN2011101420374 A CN 2011101420374A CN 201110142037 A CN201110142037 A CN 201110142037A CN 102214659 A CN102214659 A CN 102214659A
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Abstract
The invention relates to an NVM (nonvolatile memory) and a manufacturing method thereof. The NVM comprises a substrate, two construction units, coupled conductive media, tunnel media and a control grid, wherein the two construction units are separated and parts of the two construction units are embedded into the substrate; each construction unit comprises the coupling media, a floating gate, spacer media, support media and a side wall in sequence; the coupling media and the floating gate are embedded into the substrate; the coupled conductive media are filled in the space between the two separated construction units; the coupling media, the spacer media and the side wall surround the floating gate; the floating gate and the coupled conductive media are separated; the tunnel media are arranged on the substrate surfaces outside the construction units; and the control grid is arranged on the tunnel media and separated from the floating gate. The NVM is simple in structure, convenient to manufacture and beneficial to reducing the sizes of memory cells.
Description
Technical field
The present invention relates to a kind of nonvolatile memory and manufacture method thereof, particularly a kind of nonvolatile memory of gate-distribution embedding type floating gate and manufacture method thereof.
Background technology
Nonvolatile memory (Non-Volatile Memory, NVM) be a kind of memory cell with mos transistor structure, can repeatedly carry out depositing in of data because of having, read, characteristic such as erase, and the data that deposit in can not disappear after outage yet, therefore, are widely used in personal computer and electronic equipment.Yet along with semiconductor subassembly develops gradually towards miniaturization, the size of memory also reduces along with live width and dwindles, and relatedly makes the source electrode in the non-volatility memorizer significantly reduce the coupling efficiency of floating grid.
Usually, nonvolatile memory generally comprises source region, drain region, channel region, control gate and floating boom.Floating gate structure is the MOS transistor and the common MOS transistor major different of non-volatile memory cells, it plays the effect of stored charge in this memory cell structure, make memory cell under the situation of outage, still can keep many canned datas, thereby make sort memory that non-volatile characteristics be arranged.At present, the floating gate structure of nonvolatile memory comprises folded grid and grid dividing structure.
As shown in Figure 1, be the structural representation of the nonvolatile memory of existing a kind of grid dividing structure.Described nonvolatile memory comprises: Semiconductor substrate 10; Be positioned at two separated structural units on the Semiconductor substrate 10.Described construction unit comprises couplant layer 11, floating boom 12, spacer medium layer 13 and the supporting medium layer 14 that is positioned at successively on the Semiconductor substrate 10, and wherein said floating boom 12 lateral surfaces are angular shape; Source electrode 17 in the Semiconductor substrate 10 between two separated structural units; Be positioned at couplant layer 11, the floating boom 12 of two separation, the first side wall layer 15 of spacer medium layer 13 madial wall; Fill the coupling conducting shell 16 in the gap between two separated structural units; Be positioned on two separated structural units lateral walls and the described construction unit outer semiconductor substrate 10, be the tunnel dielectric layer 18 of L type; Be positioned at the control grid 19 in L type tunnel dielectric layer 18 outsides; Be positioned at the drain electrode 20 of control grid 19 outer semiconductor substrates 10.
Along with diminishing of nonvolatile memory size, the size of floating boom also diminishes thereupon, and under the constant situation of other conditions, source electrode reduces the coupling area of floating boom, thereby influence the ability of non-volatile memory cell programming, cause the non-volatile memory cells decreased performance.
Summary of the invention
The object of the present invention is to provide a kind of nonvolatile memory that can address the above problem.
Another object of the present invention is to provide a kind of manufacture method of above-mentioned nonvolatile memory.
A kind of nonvolatile memory comprises: substrate; Be partially submerged into two separated structural units in the described substrate, each construction unit comprises couplant, floating boom, spacer medium, Supporting Media and sidewall, described couplant, floating boom, spacer medium, Supporting Media set gradually, described couplant and described floating boom embed in the described substrate, and described sidewall is arranged between described two separated structural units and attaches described couplant, floating boom, spacer medium, Supporting Media; The coupling transmitting medium, described coupling transmitting medium is filled between described two separated structural units, the described floating boom of described couplant, spacer medium and side walls enclose, described floating boom and described coupling transmitting medium are isolated; Be positioned at the tunnel dielectric of the substrate surface in the described construction unit outside; Be positioned at the control grid on the described tunnel dielectric, described control grid and described floating boom are isolated.
The preferred a kind of technical scheme of above-mentioned nonvolatile memory, described nonvolatile memory also comprise the source electrode between two described construction units that are arranged in the described substrate.
The preferred a kind of technical scheme of above-mentioned nonvolatile memory, described nonvolatile memory also comprise the drain electrode that is positioned at the described control grid outside that is arranged in the described substrate.
The preferred a kind of technical scheme of above-mentioned nonvolatile memory, the surface of described floating boom is higher than the surface of described substrate.
The preferred a kind of technical scheme of above-mentioned nonvolatile memory, described sidewall attaches the described Supporting Media of described couplant, floating boom, spacer medium and part.
A kind of manufacture method of nonvolatile memory comprises the steps: to form substrate and is positioned at the etching barrier layer with opening of described substrate surface; With described etching barrier layer is mask, and the described substrate of etching forms groove in described substrate, forms the couplant layer at described trench wall, is embedded in floating boom at described couplant layer; Form the spacer medium layer at the opening sidewalls of described etching barrier layer and the surface of described floating boom; Form the supporting dielectric layer of two separation that are positioned at described spacer medium laminar surface at described opening sidewalls; With described etching barrier layer and described supporting medium layer is mask, and the described spacer medium layer of etching, floating boom and couplant layer form two separated structural units; Between described two separated structural units, form the side wall layer that attaches described couplant layer, floating boom, spacer medium layer, supporting medium layer; Fill the coupling conducting shell between described two separated structural units, described floating boom and described coupling conducting shell are isolated; Remove described etching barrier layer, the substrate surface in the described construction unit outside forms tunnel dielectric layer; Form the control grid on described tunnel dielectric layer, described control grid and described floating boom are isolated.
The preferred a kind of technical scheme of said method, after the described spacer medium layer of etching, floating boom and couplant layer form two separated structural units, with described etching barrier layer and described supporting medium layer is mask, in described substrate, carry out ion and inject, form the source electrode of the memory cell of described nonvolatile memory.
The preferred a kind of technical scheme of said method after forming the control grid on the described tunnel dielectric layer, is carried out ion and is injected in the substrate in the described control grid outside, form the drain electrode of the memory cell of described nonvolatile memory.
The preferred a kind of technical scheme of said method, at least a material in described floating boom, control grid, supporting medium layer and the coupling conducting shell is a polysilicon.
The preferred a kind of technical scheme of said method, at least a material in described couplant layer, spacer medium layer, side wall layer and the tunnel dielectric layer is a silica.
Compared with prior art, nonvolatile memory of the present invention is imbedded floating boom in the substrate, has strengthened the move distance of charge carrier between source electrode and drain electrode, thereby helps increasing the coverage of raceway groove, has avoided the short-channel effect of the metal-oxide-semiconductor under the small size.And the nonvolatile memory of the floating boom of this flush type is simple in structure, easy to make, helps further reducing the size of memory cell.
Description of drawings
Fig. 1 is a kind of structural representation of nonvolatile memory of grid dividing structure of prior art.
Fig. 2 is the structural representation of nonvolatile memory of the present invention.
Fig. 3 is the schematic diagram step by step of the manufacture method of nonvolatile memory of the present invention to Figure 14.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
See also Fig. 2, Fig. 2 is the structural representation of nonvolatile memory of the present invention.Described nonvolatile memory comprises substrate 21, be partially submerged into two separated structural units in the described substrate 21, be arranged at the source electrode 27 between two described construction units in the described substrate 21, be filled in the coupling transmitting medium 29 between described two separated structural units, be arranged at the tunnel dielectric 30 on substrate 21 surfaces in the described construction unit outside, be arranged at the control grid 31 on the described tunnel dielectric 30 and be arranged at the drain electrode 32 that is positioned at described control grid 31 outsides in the described substrate 21.
Each construction unit comprises couplant 23, floating boom 24, spacer medium 25, Supporting Media 26 and sidewall 28.Described couplant 23, floating boom 24, spacer medium 25, Supporting Media 26 are from setting gradually down.Described couplant 23 and described floating boom 24 embed in the described substrate 21.Described sidewall 28 is arranged between described two separated structural units and attaches described couplant 23, floating boom 24, spacer medium 25, Supporting Media 26.Preferably, the surface of described floating boom 24 is higher than the surface of described substrate 21.Described sidewall 28 attaches the described Supporting Media 26 of part.Described couplant 23, spacer medium 25 and sidewall 28 surround described floating boom 24, thereby make described floating boom 24 and described coupling transmitting medium 29, control grid 31 isolate.Described Supporting Media 26 is identical or similar with the material of described coupling transmitting medium 29, both can be connected, thereby play the purpose that improves coupling efficiency, preferably, described Supporting Media 26 is N type or the polysilicon of P type doping or the polysilicon of doping metals impurity with the material of described coupling conducting shell 29.
To Figure 14, describe the manufacture method of above-mentioned nonvolatile memory below in conjunction with Fig. 3 step by step in detail:
With described etching barrier layer 22 is mask, and the described substrate 21 of etching forms groove in described substrate 21.Form couplant layer 23 at described formation inwall, be embedded in floating boom 24 at described couplant layer 23, as shown in Figure 4.Described couplant layer 23 is used for described substrate 21 of electric insulation and described floating boom 24, and material can be silica or silicon oxynitride (SiNO) or hafnium oxide or aluminium oxide or zirconia.The manufacture craft of described couplant layer 23 can be chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) technology or thermal oxidation method etc.The technology that the described substrate of etching 21 forms grooves can be dry etching, the gash depth of formation be slightly less than described couplant layer 23 and described floating boom 24 thickness and, the surface of promptly described floating boom 24 is higher than the surface of described substrate 21.The material of described floating boom 24 can be the polysilicon of polysilicon or doping metals impurity.The method that forms described floating boom 24 comprises chemical vapour deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition processes.Usually after adopting chemical vapor deposition method to deposit described floating boom 24, also to carry out CMP (Chemical Mechanical Polishing) process, to remove the floating boom part on groove top to described floating boom 24.
Form spacer medium layer 25 at the opening sidewalls of described etching barrier layer 22 and the surface of described floating boom 24, as shown in Figure 5.Described spacer medium layer 25 is used to isolate described floating boom 24.Described spacer medium layer 25 be insulating material, preferred, be any or several combinations in silica, silicon nitride, silicon oxynitride, hafnium oxide, aluminium oxide or the zirconia, manufacture craft can adopt chemical vapour deposition technique.
Form the supporting dielectric layer 26 of two separation that are positioned at described spacer medium layer 25 surface at described opening sidewalls, as shown in Figure 6.Preferably, the peripheral profile of described supporting dielectric layer 26 is an arc, the formation technology of side wall is approximate in its technology and the semiconductor technology, for example, deposition of insulative material in described opening adopts the described insulating material of plasma etching industrial etching then, carry out chemical etching and physical bombardment in the described plasma etch process simultaneously, remove the insulating material of opening mid portion, after etching technics is finished, will form arc Supporting Media 26 at two sidewalls of opening.Preferably, the material of described Supporting Media 26 is N type or the polysilicon of P type doping or the polysilicon of doping metals impurity.
With described etching barrier layer 22 and described supporting medium layer 26 is mask, and the described spacer medium layer 25 of etching, floating boom 24 and couplant layer 23 are until exposing channel bottom to form two separated structural units, as shown in Figure 7.Described etching technics can be dry plasma etch or reactive ion etching, also can select technology well known in the art such as wet-etching technology for use, is not described in detail at this.
With described etching barrier layer 22 and described supporting medium layer 26 is mask, carries out ion and inject in described substrate 21, forms the source electrode 27 of the memory cell of described nonvolatile memory, as shown in Figure 8.Described ion can be for comprising the ion of the 3rd major element or the 5th major element, for example boron ion, phosphonium ion, arsenic ion, boron fluoride ion etc.According to the doping type of trap in the substrate 21 and the type of described nonvolatile memory, can choose different dopant ions.Concrete injection technology also can be adjusted according to the needs of technological design.
Between described two separated structural units, form the side wall layer 28 that attaches described couplant layer 23, floating boom 24, spacer medium layer 25, supporting medium layer 26, as shown in Figure 9.Described couplant layer 23, spacer medium layer 25 and side wall layer 28 are surrounded described floating boom 24 to isolate described floating boom 24.The material of described side wall layer 28 is any or several combinations in silica, silicon nitride, the silicon oxynitride.Preferably, described side wall layer 28 attaches the described supporting medium layer 26 of part, promptly on perpendicular to orientation, the height of described side wall layer 28 is greater than the height of described couplant layer 23, floating boom 24, spacer medium layer 25, but less than the height of described couplant layer 23, floating boom 24, spacer medium layer 25, supporting medium layer 26.
Between described two separated structural units, fill coupling conducting shell 29, as shown in figure 10.Described coupling conducting shell 29 electrically contacts with described source electrode 27.Because described couplant layer 23, spacer medium layer 25 and side wall layer 28 are surrounded described floating boom 24, described coupling conducting shell 29 is isolated with described floating boom 24.The material of described coupling conducting shell 29 is N type or the polysilicon of P type doping or the polysilicon of doping metals impurity, its doping type doping type with substrate 21 and floating boom 24 in principle is identical, manufacture craft can adopt earlier and fill the polycrystalline silicon material that mixes in the gap of chemical vapor deposition method between two separated structural units, adopt the described polycrystalline silicon material of CMP PROCESS FOR TREATMENT subsequently, until exposed portions serve supporting medium layer 26.Described Supporting Media 26 is identical or similar with the material of described coupling transmitting medium 29, and both can be connected, thereby plays the purpose that improves coupling efficiency.
Remove described etching barrier layer 22, as shown in figure 11.The technology of removing described etching barrier layer 22 can be for adopting wet-etching technology, and the etching agent that described wet etching adopts can be hot phosphoric acid.
In the substrate 21 in described control grid 31 outsides, carry out ion and inject, form the drain electrode 32 of the memory cell of described nonvolatile memory.The technology of described formation drain electrode 32 can be any prior art well known to those skilled in the art, and formation technology that can reference source 27 is not described in detail at this.
Compared with prior art, nonvolatile memory of the present invention is imbedded floating boom 24 in the substrate 21, strengthen the move distance of charge carrier between source electrode 27 and drain electrode 32, thereby helped increasing the coverage of raceway groove, avoided the short-channel effect of the metal-oxide-semiconductor under the small size.And the nonvolatile memory of the floating boom of this flush type is simple in structure, easy to make, helps further reducing the size of memory cell.
Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the specific embodiment described in the specification.
Claims (10)
1. a nonvolatile memory is characterized in that, comprising:
Substrate;
Be partially submerged into two separated structural units in the described substrate, each construction unit comprises couplant, floating boom, spacer medium, Supporting Media and sidewall, described couplant, floating boom, spacer medium, Supporting Media set gradually, described couplant and described floating boom embed in the described substrate, and described sidewall is arranged between described two separated structural units and attaches described couplant, floating boom, spacer medium, Supporting Media;
The coupling transmitting medium, described coupling transmitting medium is filled between described two separated structural units, the described floating boom of described couplant, spacer medium and side walls enclose, described floating boom and described coupling transmitting medium are isolated;
Tunnel dielectric, described tunnel dielectric are positioned at the surface of the substrate in the described construction unit outside;
The control grid, described control grid is positioned on the described tunnel dielectric, and described control grid and described floating boom are isolated.
2. nonvolatile memory as claimed in claim 1 is characterized in that, described nonvolatile memory also comprises and is arranged in the described substrate and the source electrode between two described construction units.
3. nonvolatile memory as claimed in claim 1 is characterized in that, described nonvolatile memory also comprises the drain electrode that is arranged in the described substrate and is positioned at the described control grid outside.
4. nonvolatile memory as claimed in claim 1 is characterized in that, the surface of described floating boom is higher than the surface of described substrate.
5. nonvolatile memory as claimed in claim 1 is characterized in that, described sidewall attaches the described Supporting Media of described couplant, floating boom, spacer medium and part.
6. the manufacture method of a nonvolatile memory is characterized in that, comprises the steps:
Form substrate and be positioned at the etching barrier layer with opening of described substrate surface;
With described etching barrier layer is mask, and the described substrate of etching forms groove in described substrate, forms the couplant layer at described trench wall, is embedded in floating boom at described couplant layer;
Form the spacer medium layer at the opening sidewalls of described etching barrier layer and the surface of described floating boom;
Form the supporting dielectric layer of two separation that are positioned at described spacer medium laminar surface at described opening sidewalls;
With described etching barrier layer and described supporting medium layer is mask, and the described spacer medium layer of etching, floating boom and couplant layer form two separated structural units;
Between described two separated structural units, form the side wall layer that attaches described couplant layer, floating boom, spacer medium layer, supporting medium layer;
Fill the coupling conducting shell between described two separated structural units, described floating boom and described coupling conducting shell are isolated;
Remove described etching barrier layer, the substrate surface in the described construction unit outside forms tunnel dielectric layer;
Form the control grid on described tunnel dielectric layer, described control grid and described floating boom are isolated.
7. the manufacture method of nonvolatile memory as claimed in claim 6, it is characterized in that, after the described spacer medium layer of etching, floating boom and couplant layer form two separated structural units, with described etching barrier layer and described supporting medium layer is mask, in described substrate, carry out ion and inject, form the source electrode of the memory cell of described nonvolatile memory.
8. the manufacture method of nonvolatile memory as claimed in claim 6, it is characterized in that, after forming the control grid on the described tunnel dielectric layer, in the substrate in the described control grid outside, carry out ion and inject, form the drain electrode of the memory cell of described nonvolatile memory.
9. the manufacture method of nonvolatile memory as claimed in claim 6 is characterized in that, at least a material in described floating boom, control grid, supporting medium layer and the coupling conducting shell is a polysilicon.
10. the manufacture method of nonvolatile memory as claimed in claim 6 is characterized in that, at least a material in described couplant layer, spacer medium layer, side wall layer and the tunnel dielectric layer is a silica.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030215999A1 (en) * | 2002-05-14 | 2003-11-20 | Chern Geeng-Chuan Michael | Self aligned method of forming a semiconductor array of non-volatile memory cells |
| KR20070019351A (en) * | 2005-08-12 | 2007-02-15 | 삼성전자주식회사 | Non-Volatile Memory Device And Method Of Fabricating The Same |
| CN101667581A (en) * | 2009-09-09 | 2010-03-10 | 上海宏力半导体制造有限公司 | Separated grid type embedded layer float grid nonvolatile storage unit and manufacturing method thereof |
| CN101770991A (en) * | 2010-01-12 | 2010-07-07 | 上海宏力半导体制造有限公司 | Nonvolatile memory of gate-distribution embedding type floating gate and manufacturing method thereof |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030215999A1 (en) * | 2002-05-14 | 2003-11-20 | Chern Geeng-Chuan Michael | Self aligned method of forming a semiconductor array of non-volatile memory cells |
| KR20070019351A (en) * | 2005-08-12 | 2007-02-15 | 삼성전자주식회사 | Non-Volatile Memory Device And Method Of Fabricating The Same |
| CN101667581A (en) * | 2009-09-09 | 2010-03-10 | 上海宏力半导体制造有限公司 | Separated grid type embedded layer float grid nonvolatile storage unit and manufacturing method thereof |
| CN101770991A (en) * | 2010-01-12 | 2010-07-07 | 上海宏力半导体制造有限公司 | Nonvolatile memory of gate-distribution embedding type floating gate and manufacturing method thereof |
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