CN101770991B - Nonvolatile memory of gate-distribution embedding type floating gate and manufacturing method thereof - Google Patents
Nonvolatile memory of gate-distribution embedding type floating gate and manufacturing method thereof Download PDFInfo
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- CN101770991B CN101770991B CN2010100227089A CN201010022708A CN101770991B CN 101770991 B CN101770991 B CN 101770991B CN 2010100227089 A CN2010100227089 A CN 2010100227089A CN 201010022708 A CN201010022708 A CN 201010022708A CN 101770991 B CN101770991 B CN 101770991B
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Abstract
The invention relates to a method for manufacturing a nonvolatile memory of a gate-distribution embedding type floating gate. The method comprises the following steps of: forming an opening on an etching blocking layer on a semiconductor substrate; forming a groove in the semiconductor substrate, forming a coupling medium layer on the inner wall of the groove, and then forming a first conducting layer embedded into the coupling medium layer; sequentially depositing isolation medium layers on the opening inner wall and the first conducting layer in the opening of the etching blocking layer, and then forming a first coupling conducting layer embedded into the isolation medium layer; forming a supporting medium layer on the side wall of the opening; etching the first coupling conducting layer, the isolation medium layer, the first conducting layer and the coupling medium layer until the semiconductor substrate is exposed, and then forming two separated structure units; forming a source electrode; forming a first side wall layer; filling a second coupling conducting layer in the gap between the two separated structure units; forming a tunnel medium layer; forming a control gate electrode outside the tunnel medium layer; and forming a drain electrode. The structure enhances the programming capability of the memory.
Description
Technical field
The present invention relates to the semiconductor fabrication techniques field, be specifically related to a kind of nonvolatile memory and manufacture method thereof of gate-distribution embedding type floating gate.
Background technology
Nonvolatile memory (Non-volatile Memory, NVM) be a kind of memory cell with mos transistor structure, can repeatedly carry out depositing in of data because having, read, the characteristic such as erase, and the data that deposit in can not disappear after outage yet, therefore be widely used in personal computer and electronic equipment.Yet, along with semiconductor subassembly develops gradually towards miniaturization, the size of memory also reduces along with live width and dwindles, relatedly make source electrode in non-volatility memorizer significantly reduce the coupling efficiency of floating grid.
Usually, nonvolatile memory generally comprises source region, drain region, channel region, control gate and floating boom.Floating gate structure is MOS transistor and the topmost difference of common MOS transistor of non-volatile memory cells, it plays the effect of stored charge in this memory cell structure, make memory cell in the situation that outage still can keep institute's canned data, thereby make sort memory that non-volatile characteristics be arranged.At present, the floating gate structure of nonvolatile memory comprises folded grid or grid dividing structure, shown in accompanying drawing 1, is the structural representation of the nonvolatile memory of existing a kind of grid dividing structure, and described nonvolatile memory comprises: Semiconductor substrate 10; Be positioned at the construction unit of two separation on Semiconductor substrate 10, described construction unit comprises couplant layer 11, floating boom 12, spacer medium layer 13 and the supporting medium layer 14 be positioned at successively on Semiconductor substrate, and wherein said floating boom lateral surface is angular shape; Source electrode 17 in Semiconductor substrate 10 between the construction unit of two separation; Be positioned at couplant layer 11, the floating boom 12 of two separation, the first side wall layer 15 of spacer medium layer 13 madial wall; The coupling conducting shell 16 in the gap between the construction unit of two separation of filling; Be positioned on the construction unit lateral wall and described construction unit outer semiconductor substrate of two separation, be the tunnel dielectric layer 18 of L-type; Be positioned at the control grid 19 in the tunnel dielectric layer outside of L-type; Be positioned at the drain electrode 20 of controlling grid outer semiconductor substrate.
Along with diminishing of nonvolatile memory size, the size of floating boom is also dwindled thereupon, in the situation that other condition is constant, source electrode reduces the coupling area of floating boom, thereby affect the non-volatile memory cell programming ability, cause the non-volatile memory cells hydraulic performance decline.
Summary of the invention
The technical problem to be solved in the present invention is, a kind of nonvolatile memory and manufacture method thereof of gate-distribution embedding type floating gate is provided, to improve the program capability of nonvolatile memory.
The invention provides a kind of manufacture method of nonvolatile memory of gate-distribution embedding type floating gate, comprising:
Semiconductor substrate is provided and is positioned at the etching barrier layer on Semiconductor substrate, on described etching barrier layer, form opening;
Take etching barrier layer as mask, and the etching semiconductor substrate forms groove in Semiconductor substrate, at trench wall, forms the couplant layer, forms the first conducting shell that embeds described couplant layer;
In the opening of described etching barrier layer, deposition is positioned at the spacer medium layer on opening inwall and the first conducting shell successively, forms the first coupling conducting shell that embeds described spacer medium layer;
Sidewall formation at described opening is positioned at the supporting medium layer on the first coupling conducting shell;
Take described etching barrier layer and supporting medium layer as mask, etching the first coupling conducting shell, the spacer medium layer, the first conducting shell and couplant layer are to exposing channel bottom, what form two separation comprises supporting medium layer, the first coupling conducting shell, the spacer medium layer, the construction unit of the first conducting shell and couplant layer;
Take described etching barrier layer and supporting medium layer as mask, carry out the first Implantation in Semiconductor substrate, form source electrode;
Madial wall at the couplant layer of two separation, the first conducting shell, spacer medium layer and part the first coupling conducting shell forms the first side wall layer;
Fill the second coupling conducting shell in gap between the construction unit of two separation, the second coupling conducting shell and the first coupling conducting shell electrically contact;
Remove etching barrier layer;
Form tunnel dielectric layer on Semiconductor substrate outside the construction unit of two separation;
Formation control grid on described tunnel dielectric layer;
Carry out Implantation in the Semiconductor substrate in the control gate outside, form drain electrode.
The present invention also provides a kind of nonvolatile memory of gate-distribution embedding type floating gate, comprising:
Semiconductor substrate;
Embed couplant layer, the floating boom of two separation in Semiconductor substrate, and be positioned at successively spacer medium layer on floating boom, the first coupling conducting shell and supporting medium layer, described couplant layer, floating boom, spacer medium layer, the first coupling conducting shell forms two construction units that separate with supporting medium layer;
Source electrode in Semiconductor substrate between the construction unit of two separation;
Be positioned at the first side wall layer of couplant layer, floating boom, spacer medium layer and the part first coupling conducting shell madial wall of two separation;
Fill the gap between the construction unit of two separation, and the second coupling conducting shell electrically contacted with the first coupling conducting shell;
Be positioned at the tunnel dielectric layer on the construction unit outer semiconductor substrate of two separation;
Be positioned at the control grid in the tunnel dielectric layer outside;
Be positioned at the drain electrode of control gate outer semiconductor substrate.
Compared with prior art, nonvolatile memory of gate-distribution embedding type floating gate of the present invention and preparation method thereof increases the overlapping area of source electrode and floating boom by the first coupling conducting shell increased, can improve the electric charge coupling of source electrode and floating boom, thereby improve the program capability of this memory cell.
The accompanying drawing explanation
By the more specifically explanation of the preferred embodiments of the present invention shown in accompanying drawing, above-mentioned and other purpose of the present invention, Characteristics and advantages will be more clear.In whole accompanying drawings, identical Reference numeral is indicated identical part.Deliberately do not draw in proportion accompanying drawing, focus on illustrating purport of the present invention.In the accompanying drawings, for cheer and bright, layer and regional thickness have been amplified.
The structural representation that Fig. 1 is the nonvolatile memory of gate-distribution embedding type floating gate in prior art;
The cross section structure schematic diagram of each step of manufacture method of the nonvolatile memory that Fig. 2 to Figure 13 is gate-distribution embedding type floating gate of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention.Therefore the present invention is not subject to the restriction of following public concrete enforcement.
The present embodiment provides a kind of manufacture method of nonvolatile memory of gate-distribution embedding type floating gate, comprises the steps:
Step S1, provide Semiconductor substrate 100 and be positioned at the etching barrier layer 105 on Semiconductor substrate 100, on described etching barrier layer 105, forms opening; Shown in accompanying drawing 2, Semiconductor substrate 100 is provided, the material of described Semiconductor substrate 100 is silicon or the SiGe (SiGe) of monocrystalline, polycrystalline or non crystalline structure for example, can be also silicon-on-insulator (SOI) etc.In the present embodiment, in described Semiconductor substrate, be formed with for isolating the isolation structure of active area, described isolation structure is fleet plough groove isolation structure (STI) preferably.The nonvolatile memory of the described gate-distribution embedding type floating gate of the present embodiment is formed in two active areas between adjacent STI.
Continuation is with reference to accompanying drawing 2; etching barrier layer 105 as mask layer, protects the rete below it not to be etched for the etching technics subsequently, and its material is such as being silicon nitride layer etc.; its manufacture craft is for example chemical vapor deposition method, and thickness range is for example 2000 dust to 4000 dusts.
The technique that forms opening on described etching barrier layer 105 can be any prior art well known to those skilled in the art, for example: adopt spin coating proceeding to form photoresist layer on etching barrier layer 105, then adopt exposure, developing process is processed described photoresist layer, remove the photoresist on setting regions, form the photoresist opening, finally take photoresist as mask, the described etching barrier layer 105 of etching, transfer to the patterns of openings on photoresist on etching barrier layer 105.
Step S2, shown in accompanying drawing 3, take etching barrier layer 105 as mask, and etching semiconductor substrate 100, at the interior formation groove of Semiconductor substrate 100, forms couplant layer 101 at trench wall, forms the first conducting shell 102 that embeds described couplant layer; Because described couplant layer is positioned at the inwall of groove, therefore, the first conducting shell of formation fills up described groove and embeds described couplant layer 101.
The technique that the described Semiconductor substrate 100 of etching forms groove is for example dry etching, the degree of depth of the groove formed is slightly less than the thickness sum of couplant layer 102 and the first conducting shell 102, that is to say, the surface of the first conducting shell 102 is higher than Semiconductor substrate 100 dust to 400 dusts.
The manufacture craft of described couplant layer 101, such as being chemical vapour deposition (CVD) (CVD), plasma enhanced chemical vapor deposition (PECVD) technique or thermal oxidation method etc., is preferably thermal oxidation method.In the present embodiment, the thickness range of couplant layer 101 is 50 dust to 150 dusts.
The material of described the first conducting shell 102 is for example the polysilicon of polysilicon or doping metals impurity, and metal impurities at least comprise a kind of metal (such as titanium, tantalum, tungsten etc.) and metal silicide.The method that forms the first conducting shell 102 comprises chemical vapour deposition (CVD) (CVD), physical vapour deposition (PVD) (PVD), plasma enhanced chemical vapor deposition (PECVD) technique.In order to obtain electric property preferably, impurity particle in polycrystalline silicon material, for example N-shaped foreign matter of phosphor or p type impurity B usually.In the present embodiment, the thickness range of the first conducting shell 102 is 200 dust to 900 dusts.If the material of couplant layer 101 is high-k (high K) material, the material of the first conducting shell 102 can also be metal.
Usually, after the employing chemical vapor deposition method deposits described the first conducting shell 102, also will carry out CMP (Chemical Mechanical Polishing) process to described the first conducting shell 102, remove first conducting shell on groove top, and the upper surface that makes the first conducting shell 102 is slightly higher than the surface of Semiconductor substrate.
Step S3, shown in accompanying drawing 4, in the opening of described etching barrier layer 105, deposition is positioned at the spacer medium layer 103 on opening inwall and the first conducting shell 102 successively, form the first coupling conducting shell 104 that embeds described spacer medium layer 103, the thickness sum of spacer medium layer 103 and the first coupling conducting shell 104 is less than open height.
Described spacer medium layer 103, for by the first conducting shell 102 and the first coupling conducting shell 104 electric insulations, therefore, can be selected any insulating material, for example silica, silicon nitride, any one in silicon oxynitride or several combinations.The material of spacer medium layer 103 can also be high-k (high K) material, can reduce the leakage current of device, and described high dielectric constant material is hafnium oxide, zirconia and aluminium oxide preferably.Manufacture craft is for example chemical vapour deposition technique, and in the present embodiment, the thickness range of spacer medium layer 103 is 50 dust to 150 dusts.
It should be noted that, described spacer medium layer is positioned on the first conducting shell and the sidewall of opening both sides, as shown in Figure 4, and the upper surface of described the first coupling conducting shell and the upper surface level of spacer medium layer, that is to say, the first coupling conducting shell embeds in described spacer medium layer, the advantage of this structure is: 1) memory cell is being write fashionablely, and hot electron, in the face of floating boom (first coupling conducting shell) motion, more easily injects and writes; 2) effective raceway groove of floating boom is elongated, thereby has suppressed short-channel effect, thereby has created condition for making less memory cell; 3) height of memory cell in the vertical direction lowers, thereby helps the Wiring technique of back segment; 4) with conventional memory cell, compare, structural change is little, and the technique manufacture is simple, simplicity of design.
The first coupling conducting shell 104 is by the second coupling conducting shell and source electrode conducting, to enlarge the area of source region, its material is for example N-type or the polysilicon of P type doping or the polysilicon of doping metals impurity, and its doping type is identical with the doping type of Semiconductor substrate and the second coupling conducting shell in principle.Its manufacture craft is for example chemical vapor deposition method, and in the present embodiment, the thickness range of the first coupling conducting shell 104 is 600 dust to 1500 dusts.If the material of spacer medium layer 103 is high-k (high K) material, the material of the first coupling conducting shell 104 can also be metal.
In the present embodiment, one preferred embodiment for adopting chemical vapor deposition method at the first conducting shell and opening sidewalls deposition spacer medium layer, subsequently, adopt chemical vapor deposition method deposition the first coupling conducting shell on described spacer medium layer and in opening, by described the first coupling conducting shell and the spacer medium layer of CMP (Chemical Mechanical Polishing) process polishing, form the structure shown in accompanying drawing 4 subsequently.
Step S4, shown in accompanying drawing 5, form and be positioned at the supporting medium layer 106 on the first coupling conducting shell at the sidewall of described opening; Described supporting medium layer 106 is positioned at two sidewalls of opening, peripheral profile is arc, its formation technique that forms side wall in technique and semiconductor fabrication process is approximate, be for example: deposition of insulative material in described opening, then, adopt the described insulating material of plasma etching industrial etching, carry out chemical etching and physical bombardment in described plasma etch process simultaneously, remove the insulating material of opening mid portion, after etching technics completes, will form arc supporting medium layer 106 at two sidewalls of opening.
Described supporting medium layer 106 materials are silica, any one in silicon nitride or silicon oxynitride or several combinations.In the present embodiment, described supporting medium layer 106, the thickness sum of spacer medium layer 103 and the first coupling conducting shell 104 is approximately equal to the open height sum of the etching barrier layer formed in accompanying drawing 2.
Step S5, shown in accompanying drawing 6, take described etching barrier layer 105 and supporting medium layer 106 is mask, etching the first coupling conducting shell 104, spacer medium layer 103, the first conducting shell 102 and couplant layer 101 be to exposing channel bottom, and what form two separation comprises supporting medium layer 106, the first coupling conducting shell 104, the construction unit of spacer medium layer 103, the first conducting shell 102 and couplant layer 101;
Described etching technics is for example dry plasma etch or reactive ion etching, also can select wet-etching technology.According to the variation of film material, convert different etching agents in etching process, it is prior art well known to those skilled in the art, does not repeat them here.
Step S6, shown in accompanying drawing 7, take described etching barrier layer 105 and supporting medium layer 106 is mask, carries out the first Implantation in Semiconductor substrate 100, forms source electrode 107;
Described the first ion is for example the ion that comprises the 3rd major element boron ion for example, boron fluoride ion etc., it can also be the ion phosphonium ion for example that comprises the 5th major element, arsenic ion etc., according to the type of doping type and the described memory device of trap in Semiconductor substrate, can select different doping ions.Concrete injection technology also can be adjusted according to the needs of technological design, and therefore, this paper is not limited to arbitrary concrete numerical value or number range.
Step S7, shown in accompanying drawing 8, form the first side wall layer 108 at the madial wall of the couplant layer 101 of two separation, the first conducting shell 102, spacer medium layer 103 and part the first coupling conducting shell 104;
The second coupling conducting shell of described the first side wall layer 108 for isolating the first conducting shell 102 and forming subsequently, and isolated part the first coupling conducting shell 104 and the second coupling conducting shell, its material is silica, any one in silicon nitride or silicon oxynitride or several combinations.
The first side wall layer 108 is 200 dust to 500 dusts at the width range of orientation, to guarantee isolation performance, and the contact area between the area of the source electrode formed subsequently and the second coupling conducting shell and source electrode.Perpendicular to orientation, the thickness of the first side wall layer 108 is greater than couplant layer 101, the thickness sum of the first conducting shell 102 and spacer medium layer 103, but be less than couplant layer 101, the thickness sum of the first conducting shell 102, spacer medium layer 103 and the first coupling conducting shell 104, be coupled and produce and electrically contact between conducting shell with the second coupling conducting shell and first that guarantees to form subsequently.
Step S8, shown in accompanying drawing 9, fill the second coupling conducting shell 109, the second coupling conducting shells 109 and the first coupling conducting shell 104 and electrically contact in the gap between the construction unit of two separation;
Described the second coupling conducting shell 109 is electrically connected to the first coupling conducting shell 104 and source electrode conducting, to enlarge the area of source region, its material is for example N-type or the polysilicon of P type doping or the polysilicon of doping metals impurity, and its doping type is identical with the doping type of Semiconductor substrate and the first coupling conducting shell in principle.Its manufacture craft for example, at first adopting the polycrystalline silicon material of filling doping in the gap of chemical vapor deposition method between the construction unit of two separation, adopts the described polycrystalline silicon material of CMP PROCESS FOR TREATMENT, until the exposed portions serve supporting medium layer subsequently.
Step S9, shown in accompanying drawing 10, remove etching barrier layer 105; The technique of removing described etching barrier layer 105 is for example: adopt wet-etching technology to remove described etching barrier layer, the etching agent that described wet etching adopts is for example hot phosphoric acid.
Step S10, shown in accompanying drawing 11, form tunnel dielectric layer 111 on the Semiconductor substrate outside the construction unit of two separation;
Described tunnel dielectric layer and the couplant layer that is positioned at the construction unit lateral wall separated, the spacer medium layer is jointly for Semiconductor substrate and control gate, floating boom and control gate, and first insulation and the isolation between coupling conducting shell 104 and control gate, and as the tunnel oxidation layer of the nonvolatile memory of gate-distribution embedding type floating gate, to realize the programming operations such as read-write of memory.Its material is for example silica, and other can be used as the dielectric material of grid oxic horizon.Its thickness range is 80 dust to 200 dusts.
Description by step S2 and step S3 can be seen, while forming described couplant layer, the sidewall of the first conducting shell that made the couplant layer surround, when forming the spacer medium layer, the spacer medium layer has also surrounded the sidewall of the first coupling conducting shell, described spacer medium layer and couplant layer have realized controlling the isolation between grid and the first conducting shell and the first coupling conducting shell, therefore, in the technique that forms tunnel dielectric layer 111, only need on the Semiconductor substrate outside the construction unit of two separation, form tunnel dielectric layer 111, for isolated controlling grid and Semiconductor substrate (and source electrode wherein).
Step S11, shown in accompanying drawing 12, at the upper formation control grid 112 of described tunnel dielectric layer.The material of described control grid 112 is for example the polysilicon of polysilicon or doping metals impurity, and metal impurities at least comprise a kind of metal (such as titanium, tantalum, tungsten etc.) and metal silicide.The method of formation control grid 112 can be any prior art well known to those skilled in the art, for example at first adopt and comprise chemical vapour deposition (CVD) (CVD) or plasma enhanced chemical vapor deposition (PECVD) technique deposit spathic silicon on tunnel dielectric layer, adopt subsequently plasma etching industrial to remove part polysilicon, formation control grid.
Step S12 shown in accompanying drawing 13, carries out Implantation in the Semiconductor substrate in the control gate outside, forms drain electrode 113.The technique of described formation drain electrode can be any prior art well known to those skilled in the art, but the formation technique of reference source does not repeat them here.
The manufacture method of the nonvolatile memory of described gate-distribution embedding type floating gate is by increasing the first coupling conducting shell electrically contacted with the second coupling conducting shell, and be electrically connected to the source electrode in Semiconductor substrate by the second coupling conducting shell, thereby increased the coupling area between source electrode and floating boom, thereby increased the program capability of device.
Because the manufacture method of the described split-gate type nonvolatile storage of the present embodiment has increased the coupling area between source electrode and floating boom, therefore, its coupling capacitance increases, when memory cell is programmed, source electrode add high pressure (7-9V), pass through coupling capacitance, the voltage of floating boom also is enhanced (to 4-5V), the high pressure of floating boom has greatly increased the electronics moved in the raceway groove and has become the probability (electronics " drain electrode " arrives " source electrode ") that hot electron leaps to floating boom, and it is to have completed the process write that the raceway groove that electronics leaps to floating boom and makes the floating boom potential drop be low to moderate the floating boom below is closed.
Source coupled capacitor is larger, and the voltage can floating boom be coupled is higher, and the ability write is stronger, and in other words in the situation that keep the ability that originally write constant, source electrode can be less with the coupling area below floating boom, thereby can dwindle the area of memory cell.
Further, the nonvolatile memory of described gate-distribution embedding type floating gate, because floating gate structure is imbedded the Semiconductor substrate the inside, strengthened the distance of the motion of charge carrier between source electrode and drain electrode, thereby be conducive to increase the coverage of raceway groove, avoided the short-channel effect of the metal-oxide-semiconductor under the small size; Further again, under the design condition of certain channel length, the grid structure of this flush type is conducive to dwindle the size of memory unit, and is conducive to reduce the thickness of this memory construction vertical structure, further reduces the size of this memory cell on three-dimensional structure.
Embodiment 2
The present embodiment provides a kind of nonvolatile memory of gate-distribution embedding type floating gate, with reference to accompanying drawing 13, comprising: Semiconductor substrate 100; Embed couplant layer 101, the floating boom 102 of two separation in Semiconductor substrate 100, and be positioned at successively spacer medium layer 103 on floating boom, the first coupling conducting shell 104 and supporting medium layer 106, described couplant layer 101, floating boom 102, spacer medium layer 103, the first coupling conducting shell 104 form two construction units that separate with supporting medium layer 106; Source electrode 107 in Semiconductor substrate between the construction unit of two separation; Be positioned at the first side wall layer 108 of couplant layer, floating boom, spacer medium layer and the part first coupling conducting shell madial wall of two separation; Fill the gap between the construction unit of two separation, and the second coupling conducting shell 109 electrically contacted with the first coupling conducting shell 104; Be positioned at the tunnel dielectric layer 111 on the construction unit outer semiconductor substrate of two separation; Be positioned at the control grid 112 in the tunnel dielectric layer outside, be positioned at the drain electrode 113 of control gate outer semiconductor substrate.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that the claims in the present invention were defined.
Claims (8)
1. the manufacture method of the nonvolatile memory of a gate-distribution embedding type floating gate comprises:
Semiconductor substrate is provided and is positioned at the etching barrier layer on Semiconductor substrate, on described etching barrier layer, form opening;
Take etching barrier layer as mask, and the etching semiconductor substrate forms groove in Semiconductor substrate, at trench wall, forms the couplant layer, forms the first conducting shell that embeds described couplant layer;
In the opening of described etching barrier layer, deposition is positioned at the spacer medium layer on opening inwall and the first conducting shell successively, forms the first coupling conducting shell that embeds described spacer medium layer;
Sidewall formation at described opening is positioned at the supporting medium layer on the first coupling conducting shell;
Take described etching barrier layer and supporting medium layer as mask, etching the first coupling conducting shell, the spacer medium layer, the first conducting shell and couplant layer are to exposing channel bottom, what form two separation comprises supporting medium layer, the first coupling conducting shell, the spacer medium layer, the construction unit of the first conducting shell and couplant layer;
Take described etching barrier layer and supporting medium layer as mask, carry out the first Implantation in Semiconductor substrate, form source electrode;
Madial wall at the couplant layer of two separation, the first conducting shell, spacer medium layer and part the first coupling conducting shell forms the first side wall layer;
Fill the second coupling conducting shell in gap between the construction unit of two separation, the second coupling conducting shell and the first coupling conducting shell electrically contact;
Remove etching barrier layer;
Form tunnel dielectric layer on Semiconductor substrate outside the construction unit of two separation;
Formation control grid on described tunnel dielectric layer;
Carry out Implantation in the Semiconductor substrate in the control gate outside, form drain electrode;
Wherein, the material of described the first conducting shell, described the first coupling conducting shell and described the second coupling conducting shell is doped polycrystalline silicon.
2. the manufacture method of the nonvolatile memory of gate-distribution embedding type floating gate according to claim 1, is characterized in that, the thickness of described the first coupling conducting shell is 600 dust to 1500 dusts.
3. the manufacture method of the nonvolatile memory of gate-distribution embedding type floating gate according to claim 1, is characterized in that, the material of described floating boom and control gate is polysilicon.
4. the manufacture method of the nonvolatile memory of gate-distribution embedding type floating gate according to claim 1, is characterized in that, described couplant layer, and the spacer medium layer, the material of the first side wall layer and tunnel dielectric layer is silica.
5. the nonvolatile memory of a gate-distribution embedding type floating gate, is characterized in that, comprising:
Semiconductor substrate;
Embed couplant layer, the floating boom of two separation in Semiconductor substrate, and be positioned at successively spacer medium layer on floating boom, the first coupling conducting shell and supporting medium layer, described couplant layer, floating boom, spacer medium layer, the first coupling conducting shell forms two construction units that separate with supporting medium layer;
Source electrode in Semiconductor substrate between the construction unit of two separation;
Be positioned at the first side wall layer of couplant layer, floating boom, spacer medium layer and the part first coupling conducting shell madial wall of two separation;
Fill the gap between the construction unit of two separation, and the second coupling conducting shell electrically contacted with the first coupling conducting shell;
Be positioned at the tunnel dielectric layer on the construction unit outer semiconductor substrate of two separation;
Be positioned at the control grid in the tunnel dielectric layer outside;
Be positioned at the drain electrode of control gate outer semiconductor substrate;
Wherein, the material of described the first coupling conducting shell and described the second coupling conducting shell is doped polycrystalline silicon.
6. the nonvolatile memory of gate-distribution embedding type floating gate according to claim 5, is characterized in that, the thickness of described the first coupling conducting shell is 600 dust to 1500 dusts.
7. the nonvolatile memory of gate-distribution embedding type floating gate according to claim 5, is characterized in that, the material of described floating boom and control gate is polysilicon.
8. the nonvolatile memory of gate-distribution embedding type floating gate according to claim 5, is characterized in that, described couplant layer, and the spacer medium layer, the material of the first side wall layer and tunnel dielectric layer is silica.
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| CN102214659B (en) * | 2011-05-27 | 2016-04-13 | 上海华虹宏力半导体制造有限公司 | Nonvolatile memory and manufacture method thereof |
| US9929165B1 (en) * | 2016-09-28 | 2018-03-27 | Globalfoundries Singapore Pte. Ltd. | Method for producing integrated circuit memory cells with less dedicated lithographic steps |
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