CN102210021B - 能够表面安装的装置 - Google Patents
能够表面安装的装置 Download PDFInfo
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Abstract
提出了一种能够表面安装的装置(100),其具有安装侧(101)、与安装侧(101)对置的上侧(102)、电绝缘的支承板(1)、电器件(2)和壳体(3)。支承板(1)将所述装置(100)朝向安装侧(101)封闭。此外,支承板(1)具有与安装侧(101)对置的固定侧(103)。为了电接触所述器件(2),支承板(1)具有设置在固定侧(103)上的印制导线(4)、设置在安装侧(101)上的接触面(5),以及穿通部(6),其中接触面(5)分别借助穿通部(6)与印制导线(4)导电连接。所述器件(2)被壳体(3)包围,其中至少一个穿通部(6)设置在所述器件(2)之下。在支承板(1)的俯视图中,壳体(3)和支承板(1)彼此齐平地设置。此外,壳体(3)将所述装置(100)朝着上侧(102)封闭。
Description
本专利申请要求德国专利申请10 2008 057 174.1的优先权,其公开内容通过引用结合于此。
本发明涉及一种能够表面安装的装置,其具有:安装侧、与安装侧对置的上侧、电绝缘的支承板、电器件和壳体。
传统地,能够表面安装的装置具有支承板、设置在支承板上的电器件以及壳体,该壳体例如由模制材料构成。电器件的接触目前通常借助接合线以及通过在器件的下侧上的导电胶来进行,接合线从器件的上侧引导至支承板。在此,通常壳体的底面积小于支承板的底面积。由此,支承板在两个对置的侧上伸出壳体,以便在伸出的支承板的区域中将电引导装置(例如印制导线)引导至支承板的安装侧上,该安装侧与壳体对置地设置。然而这样构建的带有伸出壳体的支承板的装置不利地导致增大的位置消耗。
本发明所基于的任务是,提出一种能够表面安装的装置,其特别节省位置,尤其是具有小的装置大小和小的横向延伸。
该任务尤其是通过具有本发明一个实施例的特征的能够表面安装的装置来解决。能够表面安装的装置的有利的实施形式和优选的改进方案是本发明的优选实施例的主题。
根据本发明,设计了一种能够表面安装的装置,其具有安装侧、与安装侧对置的上侧、电绝缘的支承板、电器件和壳体。支承板将该装置朝向安装侧封闭,并且具有与安装侧对置的固定侧,在该固定侧上设置有印制导线用于电接触所述器件。在支承板的安装侧上设置有接触面。此外,支承板具有穿通部,其中接触面分别借助穿通部与印制导线导电连接。所述器件设置在支承板的固定侧上,并且被壳体包围。在支承板中的至少一个穿通部设置在所述器件之下。壳体设置在支承板的固定侧上并且将所述装置朝着上侧封闭。在支承板的俯视图中,壳体和支承板彼此齐平地设置。
从支承板的固定侧至支承板的安装侧的电引导装置(例如印制导线)由此通过穿通部(所谓的微通孔)引导。它们优选设置在所述器件之下。由此,有利地并不需要用于将印制导线引导至支承板的安装侧的、伸出的支承板区域。于是,可以有利地减少装置大小,尤其是装置的横向延伸以及装置的底面积。这尤其是对于包括比较大的器件的装置、和/或对于具有一定复杂性的、尤其是多个外部电连接部位的装置是有利的。
所述装置可以优选以安装侧设置在电路板上,其中该装置的接触面优选与电路板的连接部位导电连接,例如借助导电胶来连接。所述装置的电器件的电接触由此从电路板 的连接部位通过支承板的接触面和穿通部引导至支承板的固定侧上的印制导线。
在能够表面安装的装置的一个优选的扩展方案中,支承板的穿通部仅仅设置在所述器件之下。
由此,有利地进一步减小了装置大小,尤其是所述装置的横向延伸。节省位置的能够表面安装的装置有利地成为可能。
在能够表面安装的装置的另一个优选的扩展方案中,壳体将所述器件和印制导线向外完全地电绝缘。
有利的是,于是外部的电引导装置、例如相邻的电器件的电引导装置可以设置在壳体上或者壳体的侧面上,而在此并不产生所述装置、尤其是所述装置的电器件的短路。于是,包括多个电装置或者电器件的节省位置的布置有利地成为可能。
壳体优选由电绝缘的材料构成。特别优选地,壳体具有模制材料。
在该装置的另一优选的扩展方案中,该装置仅仅可以通过安装侧向外导电地接触。
特别地,该装置优选仅仅可以借助穿通部来导电地接触。
由于该装置仅仅可以通过安装侧借助穿通部来导电接触,并且该装置的上侧、尤其是该装置的壳体电绝缘地构建,可以有利地将该装置、尤其是电器件的短路的危险最小化。
特别优选地,该装置具有侧面,其中该装置的侧面和上侧向外完全电绝缘地构建。
特别地,该装置并不具有如下的电引导装置,尤其是印制导线和/或接合线:其一直达到该装置的侧面并且在那里可以向外电接触。有利地,于是该装置的侧面和/或上侧可能对于例如相邻电器件的例如外部电引导装置可用。于是能够有利地实现外部电器件的靠近装置的布置,由此可以实现多个电器件或者装置的节省位置的布置。
在一个优选的扩展方案中,在器件和支承板之间设置电绝缘的隔离层。
特别地,优选在支承板的固定侧上设置的印制导线完全或者部分地用电绝缘的隔离层覆盖。由此,在固定器件的区域中实现了在器件和印制导线之间的电绝缘。
优选地,电器件在背离支承板的上侧上与印制导线导电连接,尤其是借助接合线导电连接。尤其是各接合线从器件的上侧引导至支承板的各印制导线。在该情况中,器件的电接触由此仅仅从器件的上侧进行。电器件的其他单侧的电接触以及在电器件(例如 倒装芯片器件)中的与其关联的电引导装置对于本领域技术人员是已知的,并且因此这里不再进一步阐述。
在能够表面安装的装置的另一扩展方案中,所述器件设置在支承板的穿通部上,并且通过穿通部与接触面导电连接。
在该情况中,电器件的双侧接触是可能的。一个电接触部在器件的下侧上通过穿通部引导至接触面。而器件的第二电接触部可以从器件的上侧借助接合线分别引导至印制导线。
如果在该情况中在器件和支承板之间设置有电绝缘的隔离层,则在隔离层中设置开口,该开口尤其是包含导电材料并且将器件的下侧与支承板的穿通部、并且由此与接触面导电连接。
优选的是,器件借助粘合剂、导电胶或者导电焊剂来固定。
在所述装置的一个优选的扩展方案中,所述器件具有适于产生或者检测电磁辐射的有源层。
所述器件的有源层优选至少具有pn结、双异质结构、单量子阱结构(SQW,single quantum well)或者多量子阱结构(MQW,multi quantum well)用于产生辐射。在此,术语量子阱结构并不包含关于量子化的维度方面的含义。由此,其尤其是包括量子槽、量子线和量子点以及这些结构的任意组合。
特别优选的是,所述器件具有与支承板对置的辐射出射侧,在器件中产生的辐射可以通过该辐射出射侧离开器件。优选的是,器件的上侧是辐射出射侧。
优选的是,所述器件是半导体本体,特别优选为薄膜半导体本体。在本申请的范围中,将如下半导体本体视为薄膜半导体本体:在其制造期间,生长衬底被剥离,其中在生长衬底上例如外延地生长了包括薄膜半导体本体的半导体本体的半导体层序列。
半导体本体的层优选基于III/V化合物半导体材料。III/V化合物半导体材料具有至少一种来自第三主族的元素,例如Al、Ga、In,以及来自第五主族的元素,例如N、P、As。特别地,术语III/V化合物半导体材料包括二元、三元和四元化合物的族,其包含至少一种来自第三主族的元素和至少一种来自第五主族的元素,尤其是氮化物半导体和磷化物半导体。这种二元、三元和四元化合物此外例如可以具有一种或者多种掺杂材料以及附加的组成部分。
特别优选地,所述器件是发光二极管(LED)、红外发射二极管(IRED)、光敏晶体管、光电二极管或者光学集成电路(Opto-IC)。
如果所述器件主要设计用于检测辐射,例如作为光电二极管、光敏晶体管或者光学集成电路,则所述器件的层优选包含硅。
优选的是,壳体对于器件发射的或者要检测的辐射是透明的。由器件产生的或者要检测的辐射于是可以通过壳体耦合输出。特别地,壳体对于器件发射的或者要检测的辐射具有低的吸收系数。
可替选地,壳体可以对于在一个波长范围中的辐射是不能透射辐射的。在该情况中,壳体用于选择波长。在确定的、尤其是不希望的波长范围中的辐射于是可以从器件发射的或者要检测的辐射的波长范围中被选择性地滤除。壳体于是用作针对确定波长的滤波器。
在所述装置的一个优选的扩展方案中,多个电器件被设置在支承板的固定侧上,它们分别被壳体完全包围。
有利地,于是可以在制造方法期间产生多个装置。可以有利地实现能够表面安装的装置的批量生产。
特别地,于是制造多个装置,这些装置随后借助分割、例如通过在两个方向上的锯割来彼此分离。在该情况中,通过锯割产生所述装置的所有四个侧面。可替选地,为了分割,可以仅仅在一个方向上锯割,使得通过锯割仅仅产生所述装置的两个侧面。
特别地,对于所述装置,具有仅仅一个层的支承板以及具有多层结构的支承板是可能的。在所述装置的一个优选的扩展方案中,支承板具有多层结构。通过多层结构,可以将支承板的特性与所希望的要求匹配。例如,多层的支承板的特征在于改进的爬电强度、改进的高频特性或者更低的吸水性。
优选地,支承板包含基本材料,例如陶瓷或者环氧树脂,以及包含于其中的玻璃纤维织物。特别地,支承板优选是电绝缘的。
在一个优选的扩展方案中,支承板的穿通部分别具有导电材料。在此,穿通部可以部分地或者完全地用导电材料填充。导电材料例如是金属或者金属合金。
优选的是,支承板的穿通部包含导电的完全体(Vollkoerper),该完全体优选插入穿通部中。优选的是,完全体在此与穿通部的大小匹配,使得其在插入之后完全填满穿 通部。例如,完全体可以包含铜或者由铜构成。
作为另外的变形方案可能的是,穿通部用电绝缘材料填充和/或以电绝缘材料覆盖。特别地,穿通部可以借助电绝缘的隔离层来覆盖,隔离层设置在器件和支承板之间。
支承板的穿通部可以相应地特定于应用地构建。特别地,穿通部可以根据应用领域而包含导电的填充物质、电绝缘的填充物质和/或空气。
能够表面安装的装置的其他特征、优点、优选的扩展方案和合乎目的性从下面结合图1至5所阐述的实施例中得出。
其中:
图1示出了根据本发明的装置的一个实施例的示意图,
图2A至2C分别示出了在不同的制造阶段中的根据本发明的装置的示意图,
图3A至3C分别示出了根据本发明的装置的另一实施例的纵截面图,
图4示出了根据本发明的装置的另一实施例的示意性横截面图,并且
图5A、5B分别示出了传统的能够表面安装的装置的实施例的视图。
相同的或者作用相同的组成部分分别设置有相同的附图标记。所示的组成部分以及组成部分彼此之间的大小关系不能视为合乎比例。
在图5A和5B中分别示出了传统的能够表面安装的装置。特别地,在图5A中示出了传统的装置的横截面,并且在图5B中示出了图5A的实施例的装置的俯视图。该装置具有安装侧101、与安装侧101对置的上侧102、支承板1、电器件2和壳体3。
电器件2尤其是设置在支承板1上并且通过印制导线4导电连接。在此,印制导线4通过支承板1的侧面引导至装置的安装侧101上。特别地,支承板1并不具有用于电接触电器件2的穿通部。
电器件2被壳体3完全包围,其中壳体3为了电接触电器件2并未完全覆盖支承板1的固定侧103。特别地,支承板1具有其上没有设置壳体3的区域。壳体3的底面积相应地小于支承板1的底面积。
支承板1由此在两个对置的侧上伸出壳体3。借助支承板1的伸出的区域,将支承板1的固定侧103和安装侧101彼此导电连接,尤其是引导印制导线4。
借助安装侧101,可以将装置设置在电路板上(未示出),其中为了电接触电器件2,将支承板1的印制导线与电路板的连接部位导电连接。
通过支承板1的伸出区域,不利的是装置的大的位置要求是必需的。特别地,传统的装置的底面积由于支承板1的伸出区域而具有比根据本发明的装置(其例如在图1的实施例中示出)大得多的底面积。
在图1中示出了能够表面安装的装置100,其具有支承板1、电器件2和壳体3。
电器件2优选是发射辐射或者检测辐射的器件。优选地,该器件是发光二极管、红外发射二极管、光敏晶体管、光电二极管或者光学集成电路(Opto-IC)。
电器件2优选具有适于产生或者检测电磁辐射的有源层。器件2优选以薄膜结构来实施。特别地,器件2优选包括外延沉积的层,这些层形成器件2。器件2的层优选基于III/V化合物半导体材料。
器件2优选具有辐射出射侧,在有源层中产生的辐射在该辐射出射侧上从器件2出射。器件的辐射出射侧优选设置在与支承板对置的侧上。
特别地,器件2设置在支承板1的固定侧103上并且被壳体3完全包围。
能够表面安装的装置100具有安装侧101和上侧102。支承板1将装置100朝着安装侧101封闭。支承板1的固定侧103与安装侧101对置地设置。
为了电接触器件2,在支承板1的固定侧103上设置有印制导线4。此外,在安装侧101上设置有接触面(未示出)。支承板1此外具有穿通部,其中各接触面借助穿通部与印制导线4导电连接。在图1的实施例中,尤其是在器件2之下设置了三个穿通部(未示出)。
壳体3设置在支承板1的固定侧103上。壳体3将装置100朝着上侧102封闭。此外,壳体3和支承板1在支承板1的俯视图中彼此齐平地设置。
借助安装侧101可以将装置100设置在电路板上(未示出)。特别地,为了电接触器件2,可以将支承板1的接触面与电路板的连接部位导电连接。
通过将穿通部至少部分地设置在器件2之下,可以实现节省位置的装置。特别地,无需如传统的情况那样的伸出的支承板区域来实现至装置100的安装侧101的电接触引导。于是,可以有利地实现具有小的装置大小、尤其是小的横向延伸的能够表面安装的装置100。
壳体3优选对于器件2发射的或者要检测的辐射是透明的。可替选地,壳体3可以对于在所希望的波长范围中的辐射是不能透射辐射的。在该情况中,壳体2满足针对预先给定的波长范围的滤波功能。
在支承板1和器件2之间设置有电绝缘的隔离层7。电绝缘的隔离层7完全覆盖设置在支承板1中的穿通部。此外,隔离层7将器件2和支承板1彼此绝缘。隔离层7局部地设置在支承板1的印制导线4上。印制导线4的并未被隔离层7所覆盖的区域分别借助接合线41与器件2的上侧导电连接。
在图1的实施例中,电器件2由此仅仅在上侧导电接触。而器件2的下侧通过隔离层7与印制导线4电绝缘。
壳体3优选具有电绝缘的材料。优选的是,壳体3将器件2、印制导线4和接合线41向外完全隔离。特别地,装置100可以仅仅通过安装侧101向外导电接触。特别地,装置100可以仅仅借助设置在支承板1中的穿通部导电接触。
装置100优选具有侧面104,其中侧面104和上侧102向外完全电绝缘地构建。特别地,没有电连接部、尤其是印制导线4和/或接合线从器件2引导至侧面104之一上。由此可能的是,在装置100的壳体3上,尤其是在装置100旁或者装置100之上可以设置其他的电器件2或者装置100,而在此并不产生短路。于是,多个装置100和/或电器件2可以节省位置地并排设置,而装置100或者器件2的电引导装置并不彼此相交。
在图1的实施例中,电器件2通过三个接合线41分别与印制导线4导电连接。可替选地,器件2也可以从下侧通过支承板1的穿通部导电连接。为此,在隔离层7中设置有至少一个开口,该开口包含导电材料,例如金属或者金属合金。由此,支承板1的至少一个穿通部可以借助隔离层7的开口与器件2的下侧导电连接。
在图2A至2C中分别示出了在不同的制造阶段中的根据本发明的装置的示意图。图2A在视图中示出了支承板1。
支承板1具有安装侧101和固定侧103。在固定侧103上构建有印制导线4。此外,在支承板1中构建有穿通部6。穿通部6用导电材料、例如金属或者金属合金填充。此外,穿通部6分别在端部区域之下各设置有印制导线4。设置在穿通部6内的导电材料于是可以分别与印制导线4的端部区域直接导电连接。
在支承板1的安装侧101上设置有接触面(未示出)。接触面分别通过穿通部6与印制导线4导电连接。特别地,导电材料分别在穿通部6中与印制导线4以及与接触面导电连接,使得固定侧103的印制导线4分别与安装侧101的接触面导电连接。
图2B示出了在制造能够表面安装的装置时的下一方法步骤。在支承板1的部分区域上设置有电绝缘的隔离层7。特别地,在固定侧103上的支承板1的穿通部借助隔离层7来覆盖。
支承板1的印制导线4部分地被隔离层7覆盖。在该方法阶段中制造的能够表面安装的装置可以相应地分为两个部分区域。特别地,该装置具有如下部分区域:其在支承板1的固定侧103上借助隔离层7电绝缘地构建。此外,该装置具有第二部分区域,其中固定侧103具有印制导线4,其并未设置有电绝缘的隔离层7。在该部分区域中,装置由此可以通过印制导线4、穿通部和接触面来导电接触。
在图2C中示出的装置中,在电绝缘的隔离层7上施加电器件2。优选的是,电器件2借助粘合剂8或者焊剂固定在隔离层7上。
如在图1中所示的实施例中那样,电器件2优选是发射辐射或者检测辐射的器件。尤其是该器件优选为发光二极管、红外发射二极管、光敏晶体管、光电二极管或者光学集成电路。
为了器件2的电接触,分别由印制导线4将接合线41引导至器件2的上侧上的接触部位,该上侧与支承板1对置。
可替选地,电器件2可以直接设置在支承板1的印制导线4上,尤其是设置在支承板1的穿通部上(未示出)。在该情况中,优选的是在器件2和支承板1之间并未设置电绝缘的隔离层7。器件的另外的电接触部以及任何其他的电接触部可以优选通过器件的上侧借助接合线分别引导至与第一印制导线4电绝缘的其他印制导线4。
在下一方法步骤中,将壳体设置在支承板1的固定侧103上(未示出)。特别地,壳体设置为使得电器件2、接合线41和印制导线4完全地被壳体材料包围。该装置的上侧和侧面于是完全电绝缘地构建。该装置的电接触相应地仅仅通过安装侧101是可能的。
特别地,壳体将器件2和接合线41密封(未示出)。优选借助传递模塑工艺(Transfermoldprozess)来实现壳体的施加。壳体优选具有对于辐射透明或者对于确定的波长范围具有滤波作用的模制材料。在施加壳体之后,产生装置,如其例如在图1的实施例中示出的那样。
在图3A至3C中分别示出了根据本发明的装置的另一实施例的俯视图。特别地,在图3A中示出了该装置的安装侧101的俯视图。图3B示出了支承板1的固定侧103的俯视图。在图3C中示意性示出了能够表面安装的装置100的上侧102的示意性俯视图。
在支承板1的安装侧101上设置有接触面5。在图3A的实施例中,设置有四个通过间隔来彼此电绝缘的接触面5。接触面5至少部分地与集成在支承板1中的穿通部6交迭。在穿通部6之下分别设置有接触面5。穿通部6优选借助导电材料、例如金属或者金属合金来填充。于是,设置在支承板1的下侧上的接触面5可以与支承板1的固定侧上的印制导线导电连接。
接触面5以及在接触面5之间的间隔优选部分地借助电绝缘材料9来平面化。尤其是,在接触面5之间的区域完全借助电绝缘材料9来填充。接触面5优选仅仅部分地(尤其是在穿通部6的区域中)设置有电绝缘材料9。接触面5的部分区域优选并不具有电绝缘材料9,使得在部分区域中产生外部的电连接部位51。在图3A的实施例中,设置有四个彼此电绝缘的连接部位51。
连接部位51分别优选设置用于外部的接触。例如,电连接部位51设计为接地端子(Ground:GND)。另一电连接部位例如可以设计为用于供电电压(共集电极电压:VCC)的连接部位。另一连接部位例如设计用于SCL(单计算机逻辑)。在图3A的实施例中最后的连接部位例如可以作为用于SDA(智能数字助理)的连接部位。
接触面51优选具有在0.5mm到0.7mm的范围中的长度,尤其是0.6mm的长度。接触面51的宽度分别大约在0.4mm到0.5mm之间的范围中,并且尤其是优选为0.45mm。
接触面51分别具有中点,其在图3A中通过叉来表明。两个接触面51的中点例如以彼此之间1.1mm到1.4mm之间的距离来设置。
在图3B中示出了支承板1的固定侧103的俯视图。在图3B的实施例中,由于清楚的原因,并未示出电器件和壳体。
在支承板1的固定侧103上设置有印制导线4。优选的是,印制导线4具有在0.2mm到0.4mm之间的范围中的宽度dL,以及在0.4mm到0.5mm之间的范围中的彼此间的距离dA。例如印制导线4具有0.3mm的宽度dL以及0.467mm的彼此间的距离dA。
在印制导线4的部分区域之下分别设置有支承板1的穿通部6。印制导线4优选完全包围穿通部6。设置在穿通部6中的导电材料于是可以分别与印制导线4导电连接。穿通部6分别具有例如大约0.15mm的直径dD。
在支承板1的固定侧103的至少一个部分区域上设置有电绝缘的隔离层7。特别地,支承板1的穿通部6和印制导线4的部分区域被电绝缘的隔离层7覆盖。而印制导线4的其他部分区域并不具有电绝缘的隔离层7。在所述其他部分区域中,电器件可以例如借助接合线与印制导线4导电连接。
在图3C中示出了能够表面安装的装置的俯视图。相比于图3B的实施例,在电绝缘的层7上设置有电器件2,尤其是发光二极管、红外发射二极管、光敏晶体管、光电二极管或者光学集成电路。电器件2例如具有大约1.2mm的宽度dB和大约1mm的长度lB。此外,电器件2优选具有发射辐射的区域S,其具有中央区域Z。中央区域Z例如距电器件2的侧面以大约0.35mm的距离来设置。发射辐射的区域S例如具有大约0.16mm2的面积。
电器件2的接触部位优选分别借助接合线41与印制导线4导电连接。特别地,接合线41分别与支承板4的、其上并未设置电绝缘的隔离层7的部分区域导电连接。
电器件2优选设置在电绝缘的层7上。由此,在器件2的固定区域中,印制导线4与电器件2电绝缘。于是,可以避免器件2的短路。
该装置例如具有大约2±0.15mm2的底面积。
在图4中示出了能够表面安装的装置100的横截面,例如图1中的实施例的装置100的横截面。在支承板1的固定侧103上设置有电绝缘的隔离层7并且其上设置有电器件2。支承板1具有穿通部6,电引导装置、尤其是导电材料通过穿通部引导至设置在装置的安装侧101上的接触面。电器件2于是可以借助穿通部6在装置100的安装侧101上外部地电接触。特别地,装置100可以仅仅从安装侧101来电接触。
电器件2例如具有大约0.22mm的高度dH。装置100例如具有大约0.7±0.1mm的高度dV。
电器件2完全由壳体3成形,尤其是由壳体3包围。此外,接合线41完全被壳体3包围。壳体3尤其是与支承板1齐平地设置。特别地,壳体3的侧面线性地过渡到支承板1的侧面中。
在装置100的安装侧101上设置有接触面5,尤其是外部连接部位51和电绝缘材料9。通过电绝缘材料9,可以有利地将装置100朝着安装侧101平面化。此外,于是可以有利地避免装置100和/或电器件2的短路。通过连接部位51,该装置可以向外电接触。
借助上述实施例对根据本发明的装置的阐述不能视为将本发明局限于此。更确切地说,本发明包括任意新的特征和特征的任意组合,尤其是权利要求中的特征的任意组合,即使该特征或者该组合本身并未明确地在权利要求或者实施例中予以说明。
Claims (15)
1.一种能够表面安装的装置(100),其具有安装侧(101)、与安装侧(101)对置的上侧(102)、电绝缘的支承板(1)、电器件(2)和壳体(3),其中
-所述支承板(1)将所述装置(100)朝向安装侧(101)封闭,具有与安装侧(101)对置的固定侧(103),其中为了电接触所述器件(2),所述支承板(1)具有设置在固定侧(103)上的印制导线(4)、设置在安装侧(101)上的接触面(5)、以及穿通部(6),其中所述接触面(5)分别借助穿通部(6)与印制导线(4)导电连接,
-所述器件(2)设置在所述支承板(1)的固定侧(103)上,并且被壳体(3)包围,其中至少一个穿通部(6)设置在所述器件(2)之下,
-所述壳体(3)设置在支承板(1)的固定侧(103)上,使得在支承板(1)的俯视图中所述壳体(3)和所述支承板(1)彼此齐平地设置,并且壳体(3)将所述装置(100)朝着所述上侧(102)封闭,
-在所述器件(2)和所述支承板(1)之间设置有电绝缘的隔离层(7),在所述隔离层(7)中设置有至少一个开口,以及
-所述至少一个开口包含导电材料,使得所述支承板(1)的至少一个穿通部(6)借助所述隔离层(7)的所述至少一个开口与器件(2)导电连接。
2.根据权利要求1所述的能够表面安装的装置,其中所述穿通部(6)仅仅设置在所述器件(2)之下。
3.根据权利要求1所述的能够表面安装的装置,其中所述壳体(3)将所述器件(2)和印制导线向外完全地电绝缘。
4.根据权利要求1所述的能够表面安装的装置,其中所述装置(100)仅仅能够通过安装侧(101)向外导电地接触。
5.根据权利要求1所述的能够表面安装的装置,其中所述装置(100)仅仅能够借助穿通部(6)来导电地接触。
6.根据权利要求1所述的能够表面安装的装置,其中所述装置(100)具有侧面(104),并且所述侧面(104)和所述上侧(102)向外完全电绝缘地构建。
7.根据权利要求1所述的能够表面安装的装置,其中所述器件(2)设置在支承板(1)的穿通部(6)上,并且通过所述穿通部(6)与接触面(5)导电连接。
8.根据权利要求1至7中的一项所述的能够表面安装的装置,其中所述器件(2)借助粘合剂(8)来固定。
9.根据权利要求1至7中的一项所述的能够表面安装的装置,其中所述器件(2)具有适于产生或者检测电磁辐射的有源层。
10.根据权利要求1至7中的一项所述的能够表面安装的装置,其中所述器件(2)是发光二极管、红外发射二极管、光敏晶体管、光电二极管或者光学集成电路。
11.根据权利要求9所述的能够表面安装的装置,其中所述壳体(3)对于所述器件(2)发射的或者要检测的辐射是透明的。
12.根据权利要求10所述的能够表面安装的装置,其中所述壳体(3)对于所述器件(2)发射的或者要检测的辐射是透明的。
13.根据权利要求10所述的能够表面安装的装置,其中所述壳体(3)对于在一个波长范围中的辐射是不能透射辐射的。
14.根据权利要求1至7中的一项所述的能够表面安装的装置,其中多个电器件(2)被设置在支承板(1)的固定侧(103)上,所述电器件分别被壳体(3)包围。
15.根据权利要求1至7中的一项所述的能够表面安装的装置,其中所述支承板(1)具有多层结构。
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6531328B1 (en) * | 2001-10-11 | 2003-03-11 | Solidlite Corporation | Packaging of light-emitting diode |
US6890796B1 (en) * | 1997-07-16 | 2005-05-10 | Oki Electric Industry Co., Ltd. | Method of manufacturing a semiconductor package having semiconductor decice mounted thereon and elongate opening through which electodes and patterns are connected |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3117571A1 (de) | 1981-05-04 | 1982-11-18 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Lumineszenz-halbleiterbauelement |
JP3638771B2 (ja) * | 1997-12-22 | 2005-04-13 | 沖電気工業株式会社 | 半導体装置 |
US6661084B1 (en) * | 2000-05-16 | 2003-12-09 | Sandia Corporation | Single level microelectronic device package with an integral window |
US20040188696A1 (en) * | 2003-03-28 | 2004-09-30 | Gelcore, Llc | LED power package |
US7279724B2 (en) * | 2004-02-25 | 2007-10-09 | Philips Lumileds Lighting Company, Llc | Ceramic substrate for a light emitting diode where the substrate incorporates ESD protection |
JP2006066630A (ja) * | 2004-08-26 | 2006-03-09 | Kyocera Corp | 配線基板および電気装置並びに発光装置 |
US7329905B2 (en) * | 2004-06-30 | 2008-02-12 | Cree, Inc. | Chip-scale methods for packaging light emitting devices and chip-scale packaged light emitting devices |
JP2006128512A (ja) * | 2004-10-29 | 2006-05-18 | Ngk Spark Plug Co Ltd | 発光素子用セラミック基板 |
US7910940B2 (en) | 2005-08-05 | 2011-03-22 | Panasonic Corporation | Semiconductor light-emitting device |
DE102005059524A1 (de) | 2005-09-30 | 2007-04-05 | Osram Opto Semiconductors Gmbh | Gehäuse für ein elektromagnetische Strahlung emittierendes optoelektronisches Bauelement, Bauelement und Verfahren zum Herstellen eines Gehäuses oder eines Bauelements |
JP5038631B2 (ja) | 2006-02-03 | 2012-10-03 | 新光電気工業株式会社 | 発光装置 |
JP4833683B2 (ja) * | 2006-02-17 | 2011-12-07 | 株式会社 日立ディスプレイズ | 光源モジュールの製造方法及び液晶表示装置の製造方法 |
JP2008071955A (ja) | 2006-09-14 | 2008-03-27 | Nichia Chem Ind Ltd | 発光装置 |
US20080179618A1 (en) * | 2007-01-26 | 2008-07-31 | Ching-Tai Cheng | Ceramic led package |
JP2008258264A (ja) * | 2007-04-02 | 2008-10-23 | Citizen Electronics Co Ltd | 光源ユニット用発光ダイオードモジュールの構造 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6890796B1 (en) * | 1997-07-16 | 2005-05-10 | Oki Electric Industry Co., Ltd. | Method of manufacturing a semiconductor package having semiconductor decice mounted thereon and elongate opening through which electodes and patterns are connected |
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