CN102194939A - Gallium nitride based light-emitting diode (LED) epitaxial wafer and growth method thereof - Google Patents
Gallium nitride based light-emitting diode (LED) epitaxial wafer and growth method thereof Download PDFInfo
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- CN102194939A CN102194939A CN2010101284375A CN201010128437A CN102194939A CN 102194939 A CN102194939 A CN 102194939A CN 2010101284375 A CN2010101284375 A CN 2010101284375A CN 201010128437 A CN201010128437 A CN 201010128437A CN 102194939 A CN102194939 A CN 102194939A
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Abstract
The invention provides a gallium nitride based light-emitting diode (LED) epitaxial wafer and a growth method thereof. From down to up, the structure of the epitaxial wafer successively comprises a substrate, a gallium nitride based buffer layer, a non-doped gallium nitride layer, an n type gallium nitride layer, a multi-quantum well layer, a p type AlGaN layer, a p type gallium nitride layer and a contact layer. The epitaxial wafer is characterized in that the contact layer is an n type InxGa1-xN layer, or a p type InxGa1-xN layer, wherein x is a molar coefficient and is more than 0 and less than 1. The modulated doped contact layer epitaxial structure is obtained through adding an In component and a doped layer with gradually changed concentration, thereby relieving the impact of static electricity on a gallium nitride LED and improving the tolerance capability of the LED on the static electricity. According to a standard chip process, the chip with 300*300 mu m<2> is manufactured, and the electronic static discharge (ESD) yield of the chip in reverse 4000 V is above 90%.
Description
Technical field
The present invention the present invention relates to a kind of LED epitaxial wafer and growing method thereof, and particularly a kind of GaN-based LED epitaxial wafer and growing method thereof that improves its antistatic effect belongs to technical field of semiconductors.
Background technology
Gallium nitride-based material, comprise InGaN, GaN, AlGaN alloy, be direct gap semiconductor, and band gap is adjustable continuously from 1.8～6.2eV, be the preferred material of production high brightness blue, green glow and white light LEDs, be widely used in fields such as full-color large scale display, LCD backlight, signal lamp, illumination.
The general GaN LED device that adopts ITO as electrode, generally bad because ITO and pGaN directly contact, can cause current density inhomogeneous, local current densities is excessive.And the GaN sill is grown on the Sapphire Substrate mostly, because the lattice mismatch between GaN sill and the Sapphire Substrate is bigger, is about 13.5%, so can produce a large amount of dislocations and defective in epitaxial loayer, density of defects is up to 1 * 10
8～1 * 10
10/ cm
3Because the local current densities of p type electrode is too high, can make the electric charge of this position enter the pn interface of LED along the defective of epitaxial loayer.Simultaneously Sapphire Substrate is an insulating material, and the electrostatic charge that produces because of factors such as friction, induction, conduction is difficult to discharge from the substrate direction, when electric charge run up to a certain degree will take place the static release phenomenon (Electro Static Discharge, ESD).Event is that the GaN base LED chip of substrate belongs to electrostatic sensitivity device with the sapphire, and its antistatic effect is relatively poor.The anti-ESD ability of GaN base LED chip under Human Body Model's standard measured value usually less than ± 1000V (with reference to Chang, S.J. wait people 2003 at Electron Device Letters, IEEE Volume 24, the Improved ESD protection by combining InGaN-GaN MQW LEDswith GaN Schottky diodes that Issue 3 delivers).Some mechanism has introduced than complex devices manufacture method (Chinese patent publication number CN 1988119A) for the ESD that improves GaN base LED device, has improved the cost that device is made.
Static discharges and can very promptly take place with high intensity, and when discharging current was flowed through the PN junction of LED, the Joule heat of generation made local medium fusion between chip PN the two poles of the earth, causes PN junction short circuit or electric leakage, thereby causes sudden inefficacy of LED device or potentiality inefficacy.Sudden inefficacy causes the permanent inefficacy of LED, i.e. short circuit.Potentiality lost efficacy and then can make the performance parameter deterioration of LED, and for example leakage current strengthens, and general GaN base LED is subjected to behind the electrostatic damage formed hidden danger and there is no any method and can cure, and because the parameter deterioration causes vicious circle, finally causes permanent inefficacy.
Therefore, must in epitaxial process, introduce new structure with the damage of opposing ESD to device.The present invention is alleviated the impact of static to gallium nitride based LED by adopting the contact layer structure of modulation doping, improves the tolerance of LED to static from material growth aspect, has saved to improving the additional chip manufacturing cost of ESD of LED device.
Summary of the invention
The object of the present invention is to provide a kind of GaN-based LED epitaxial wafer structure and growing method thereof.By adopting the modulation doping contact layer structure, in the modulation doping contact layer, produce two-dimensional hole gas, make electric charge at first along the horizontal movement of modulation doping interface, thereby the impact of instantaneous pressure static has been played the effect of dispersion, buffering, reduce the destructive power of high-pressure electrostatic, thereby improved the antistatic effect of gallium nitride based LED device.
During technical scheme of the present invention:
A kind of GaN-based LED epitaxial wafer, its structure are followed successively by substrate, gallium nitrate based resilient coating, non-doped gallium nitride layer, n type gallium nitride layer, multiple quantum well layer, p type gallium aluminium nitrogen layer, p type gallium nitride layer and contact layer from bottom to up; This contact layer is n type In
xGa
1-xThe N layer perhaps is p type In
xGa
1-xThe N layer, wherein x is a mole coefficient, 0＜x＜1.
Described n type In
xGa
1-xThe N layer comprises the low-doped n type In of low In component
xGa
1-xThe highly doped n type In of N layer and high In ingredient
xGa
1-xThe N layer; Wherein: the low-doped n type In of described low In component
xGa
1-xThe N layer thickness is 1～5nm, selects for use Si to mix as the n type, and concentration is at le
-17Cm
-3～5e
-18Cm
-3, the scope of mole coefficient x is: 0.05≤x≤0.15; The highly doped n type In of described high In ingredient
xGa
1-xThe N layer thickness is 1～5nm, selects for use Si to mix as the n type, and concentration is at 5e
-18Cm
-3～2e
-19Cm
-3, the scope of mole coefficient x is: 0.1≤x≤0.25.
Described p type In
xGa
1-xThe N layer comprises the low-doped p type In of low In component
xGa
1-xThe highly doped p type In of N layer and high In ingredient
xGa
1-xThe N layer; Wherein: the low-doped p type In of low In component
xGa
1-xThe N layer thickness is 1～5nm, selects for use Mg to mix as the p type, and concentration is at le
-17Cm
-3～le
-19Cm
-3, the scope of mole coefficient x is: 0.05≤x≤0.15; The highly doped p type In of described high In ingredient
xGa
1-xThe N layer thickness is 1～5nm, selects for use Mg to mix as the p type, and concentration is at le
-19Cm
-3～5e
-20Cm
-3, the scope of mole coefficient x is: 0.1≤x≤0.25.
The present invention adopts metal-organic chemical vapor deposition equipment method (MOCVD, Metalorganic ChemicalVapor Deposition) growth, substrate is selected the sapphire in (0001) crystal orientation for use, and metal organic source and nitrogenous source are respectively trimethyl gallium (TMGa), trimethyl indium (TMIn), triethyl-gallium (TEGa), trimethyl aluminium (TMAl) and ammonia (NH
3), n type dopant is the H of 200ppm
2Silane (the SiH that carries
4), p type dopant is two luxuriant magnesium (Cp
2Mg).
The growing method of described GaN-based LED epitaxial wafer adopts the MOCVD method, carries out following growth step successively:
1) under 1050～1250 ℃ at H
2The high temperature purification Sapphire Substrate is 5～10 minutes in the environment;
2) be cooled to the gallium nitrate based resilient coating of low temperature of 530～560 ℃ of growth 20～35nm thickness;
3) be warming up to 1100～1200 ℃ the growth 1～2.5 μ m thickness non-doped gallium nitride layer;
4) the n type gallium nitride layer of growth 1.5～3 μ m thickness;
5) be cooled to 740～860 ℃, the multiple quantum well layer of the InGaN/GaN in 5～15 cycles of growth;
6) be warming up to 960～1080 ℃, the p type gallium aluminium nitrogen layer of growth 30～120nm thickness;
7) the p type gallium nitride layer of growth 150～400nm thickness;
8) be cooled to 740～860 ℃, the n type In of growth 2～10nm thickness
xGa
1-xN layer or p type In
xGa
1-xThe N layer is as contact layer.
Epitaxial wafer is made into 300 * 300 μ m according to standard chips technology
2Be the chip of transparency electrode with ITO.The test of the anti-ESD ability of chip with reference to GJB 548A-1996 " microelectronic component Test Methods And Procedures ", is adopted Human Body Model's standard (HBM, Human Body Model), to 300 * 300 μ m
2Chip by behind the ESD of reverse 4000V, test its leakage current under the 8V reverse voltage, failure criteria is 0.5 μ A, statistics reaches the yields of the standard compliant chip of reverse leakage current (Ir).
The invention has the advantages that: by adopting the low-doped n type In of low In component
xGa
1-xThe In of the highly doped n type of N layer and high In ingredient
xGa
1-xN layer, or the low-doped p type In of low In component
xGa
1-xThe In of the highly doped p type of N layer and high In ingredient
xGa
1-xThe contact layer that the N layer constitutes produces modulation-doped structure at the interface because of the concentration difference of mixing in the two-layer equation contact layer structure.The electric charge that the instantaneous pressure discharge that is caused by ESD is produced forms two-dimensional hole gas in modulation-doped structure, thereby is disperseed, the density of the immediate current that having reduced sparks produces, thereby reduced the destructive power of ESD, improved the antistatic effect of device device architecture.Press 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is more than 90%.
Description of drawings
Fig. 1: GaN-based LED epitaxial wafer structural representation schematic diagram.Wherein: 101 is substrate, and 102 is the gallium nitrate based resilient coating of low temperature, and 103 is non-doped gallium nitride layer, and 104 is gallium nitrate based n type layer, and 11 is multiple quantum well layer, and 105 is p type gallium aluminium nitrogen layer, and 106 is gallium nitride based p type layer, and 12 is contact layer.
Embodiment
Embodiment 1
1. the Sapphire Substrate in (0001) crystal orientation is put into reative cell, then at H
2Be warming up to 1050 ℃ in the environment, stablized 10 minutes, substrate is carried out high temperature purification.
2. be cooled to the gallium nitrate based resilient coating of low temperature of 530 ℃ of growth 20nm thickness.
3. be warming up to the non-doped gallium nitride of 1100 ℃ of growth 1 μ m thickness.
1100 ℃ the growth 1.5 μ m thickness n type gallium nitride.
5. at N
2The multiple quantum well layer in 10 cycles of growth in the environment, GaN builds layer: thickness is 20nm, and growth temperature is 850 ℃; InGaN trap layer: thickness is 2nm, and growth temperature is 810 ℃.
6. be warming up to the p type Al of 960 ℃ of growth 30nm thickness
0.15Ga
0.85The N layer.
7. at the p type gallium nitride of 940 ℃ of growth 150nm thickness.
8. at the low-doped p type In of 810 ℃ of growth 2nm thickness
0.1Ga
0.9The highly doped p type of N and 2nm In
0.2Ga
0.8The N contact electrode layer.
9. be cooled to room temperature, growth ending.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 95%.
Embodiment 2
The growth of employing mocvd method: except that the step 8, other step as shown in Example 1.And the 8th step was:
8. at the low-doped n type In of 810 ℃ of growth 2nm thickness
0.1Ga
0.9The highly doped n type of N and 2nm In
0.2Ga
0.8The N contact electrode layer.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 90%.
Embodiment 3
The growth of employing mocvd method.
1. the Sapphire Substrate in (0001) crystal orientation is put into reative cell, then at H
2Be warming up to 1050 ℃ in the environment, stablized 10 minutes, substrate is carried out high temperature purification.
2. be cooled to the gallium nitrate based resilient coating of low temperature of 530 ℃ of growth 20nm thickness.
3. be warming up to the non-doped gallium nitride of 1100 ℃ of growth 1.5 μ m thickness.
1100 ℃ the growth 2 μ m thickness n type gallium nitride.
5. at N
2The multiple quantum well layer in 5 cycles of growth in the environment, GaN builds layer: thickness is 20nm, and growth temperature is 850 ℃; InGaN trap layer: thickness is 1.6nm, and growth temperature is 810 ℃.
6. be warming up to the p type Al of 960 ℃ of growth 30nm thickness
0.15Ga
0.85The N layer.
7. at the p type gallium nitride of 940 ℃ of growth 150nm thickness.
8. at the low-doped p type In of 810 ℃ of growth 2nm thickness
0.05Ga
0.95The highly doped p type of N and 2nm In
0.1Ga
0.9The N contact electrode layer.
9. be cooled to room temperature, growth ending.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 92%.
Embodiment 4
The growth of employing mocvd method.
Except that the step 8, other step as shown in Example 3;
8. at the low-doped n type In of 810 ℃ of growth 2nm thickness
0.05Ga
0.95The highly doped n type of N and 2nm In
0.1Ga
0.95The N contact electrode layer.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 94%.
Embodiment 5
The growth of employing mocvd method.
Except that the step 8, other step as shown in Example 3;
8. at the low-doped p type In of 810 ℃ of growth 1nm thickness
0.15Ga
0.85The highly doped p type of N and 1nm In
0.25Ga
0.75The N contact electrode layer.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 95%.
Embodiment 6
The growth of employing mocvd method.
Except that the step 8, other step as shown in Example 4;
8. at the low-doped n type In of 810 ℃ of growth 1nm thickness
0.15Ga
0.85The highly doped n type of N and 1nm In
0.25Ga
0.75The N contact electrode layer
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 92%.
Embodiment 7
The growth of employing mocvd method.
Except that the step 8, other step as shown in Example 3;
8. at the low-doped p type In of 810 ℃ of growth 1nm thickness
0.1Ga
0.9The highly doped p type of N and 3nm In
0.2Ga
0.8The N contact electrode layer
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 96%.
Embodiment 8
The growth of employing mocvd method.
Except that the step 8, other step as shown in Example 4;
8. at the low-doped n type In of 810 ℃ of growth 1nm thickness
0.1Ga
0.9The highly doped n type of N and 3nm In
0.2Ga
0.8The N contact electrode layer.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 94%.
Embodiment 9
The growth of employing mocvd method.
Except that the step 8, other step as shown in Example 3;
8. at the low-doped p type In of 810 ℃ of growth 2nm thickness
0.15Ga
0.85The highly doped p type of N and 5nm In
0.25Ga
0.75The N contact electrode layer.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 99%.
Embodiment 10
The growth of employing mocvd method.
Except that the step 8, other step as shown in Example 4
8. at the low-doped n type In of 810 ℃ of growth 2nm thickness
0.15Ga
0.85The highly doped n type of N and 5nm In
0.25Ga
0.75The N contact electrode layer.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 95%.
Embodiment 11
The growth of employing mocvd method.
Except that the step 8, other step as shown in Example 3;
8. at the low-doped p type In of 810 ℃ of growth 5nm thickness
0.15Ga
0.85The highly doped p type of N and 1nm In
0.25Ga
0.75The N contact electrode layer.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 96%.
Embodiment 12
The growth of employing mocvd method.
Except that the step 8, other step as shown in Example 4;
8. at the low-doped n type In of 810 ℃ of growth 5nm thickness
0.15Ga
0.85The highly doped n type of N and 1nm In
0.25Ga
0.75The N contact electrode layer.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 96%.
Embodiment 13
The growth of employing mocvd method.
Except that the step 8, other step as shown in Example 3;
8. at the low-doped p type In of 760 ℃ of growth 1nm thickness
0.15Ga
0.85The highly doped p type of N and 1nm In
0.25Ga
0.75The N contact electrode layer.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 95%.
Embodiment 14
The growth of employing mocvd method.
Except that the step 8, other step as shown in Example 4:
8. at the low-doped n type In of 760 ℃ of growth 1nm thickness
0.15Ga
0.85The highly doped n type of N and 3nm In
0.25Ga
0.75The N contact electrode layer.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 94%.
Embodiment 15
The growth of employing mocvd method.
Except that the step 8, other step as shown in Example 4:
8. at the low-doped p type In of 760 ℃ of growth 2nm thickness
0.15Ga
0.85The highly doped p type of N and 2nm In
0.25Ga
0.75The N contact electrode layer.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 97%.
Embodiment 16
The growth of employing mocvd method.
Except that the step 8, other step as shown in Example 4:
8. at the low-doped n type In of 760 ℃ of growth 2nm thickness
0.15Ga
0.85The highly doped n type of N and 2nm In
0.25Ga
0.75The N contact electrode layer.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 94%.
Embodiment 17
The growth of employing mocvd method.
1. the Sapphire Substrate in (0001) crystal orientation is put into reative cell, then at H
2Be warming up to 1050 ℃ in the environment, stablized 10 minutes, substrate is carried out high temperature purification.
2. be cooled to the gallium nitrate based resilient coating of low temperature of 530 ℃ of growth 20nm thickness.
3. be warming up to the non-doped gallium nitride of 1180 ℃ of growth 1 μ m thickness.
1180 ℃ the growth 1.5 μ m thickness n type gallium nitride.
5. at N
2The multiple quantum well layer in 5 cycles of growth in the environment, GaN builds layer: thickness is 20nm, and growth temperature is 850 ℃; InGaN trap layer: thickness is 1.6nm, and growth temperature is 810 ℃.
6. be warming up to the p type Al of 1000 ℃ of growth 30nm thickness
0.15Ga
0.85The N layer.
7. at the p type gallium nitride of 950 ℃ of growth 150nm thickness.
8. at the low-doped p type In of 810 ℃ of growth 2nm thickness
0.1Ga
0.9The highly doped p type of N and 2nm In
0.2Ga
0.8The N contact electrode layer.
9. be cooled to room temperature, growth ending.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 97%.
Embodiment 18
The growth of employing mocvd method.
Except that the step 8, other step as shown in Example 17:
8. at the low-doped n type In of 810 ℃ of growth 2nm thickness
0.1Ga
0.9The highly doped n type of N and 2nm In
0.2Ga
0.8The N contact electrode layer.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 95%.
Embodiment 19
The growth of employing mocvd method.
1. the Sapphire Substrate in (0001) crystal orientation is put into reative cell, then at H
2Be warming up to 1050 ℃ in the environment, stablized 10 minutes, substrate is carried out high temperature purification.
2. be cooled to the gallium nitrate based resilient coating of low temperature of 530 ℃ of growth 20nm thickness.
3. be warming up to the non-doped gallium nitride of 1180 ℃ of growth 1 μ m thickness.
1180 ℃ the growth 1.5 μ m thickness n type gallium nitride.
5. at N
2The multiple quantum well layer in 15 cycles of growth in the environment, GaN builds layer: thickness is 20nm, and growth temperature is 850 ℃; InGaN trap layer: thickness is 1.6nm, and growth temperature is 810 ℃.
6. at the p type gallium nitride of 950 ℃ of growth 150nm thickness.
7. at the low-doped p type In of 810 ℃ of growth 2nm thickness
0.1Ga
0.9The highly doped p type of N and 2nm In
0.2Ga
0.8The N contact electrode layer.
8. be cooled to room temperature, growth ending.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 96%.
Embodiment 20
The growth of employing mocvd method.
Except that the step 7, other step as shown in Example 19
7. at the low-doped n type In of 810 ℃ of growth 2nm thickness
0.1Ga
0.9The highly doped n type of N and 2nm In
0.2Ga
0.8The N contact electrode layer.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 94%.
Embodiment 21
The growth of employing mocvd method.
1. the Sapphire Substrate in (0001) crystal orientation is put into reative cell, then at H
2Be warming up to 1050 ℃ in the environment, stablized 10 minutes, substrate is carried out high temperature purification.
2. be cooled to the gallium nitrate based resilient coating of low temperature of 530 ℃ of growth 20nm thickness.
3. be warming up to the non-doped gallium nitride of 1100 ℃ of growth 1 μ m thickness.
1100 ℃ the growth 1.5 μ m thickness n type gallium nitride.
5. at N
2The multiple quantum well layer in 15 cycles of growth in the environment, GaN builds layer: thickness is 20nm, and growth temperature is 760 ℃; InGaN trap layer: thickness is 1.6nm, and growth temperature is 760 ℃.
6. be warming up to the p-Al of 960 ℃ of growth 30nm thickness
0.15Ga
0.85The N layer
7. at the p type gallium nitride of 930 ℃ of growth 150nm thickness.
8. at the low-doped p type In of 760 ℃ of growth 2nm thickness
0.1Ga
0.9The highly doped p type of N and 2nm In
0.2Ga
0.8The N contact electrode layer.
9. be cooled to room temperature, growth ending.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 94%.
Embodiment 22
The growth of employing mocvd method.
Except that the step 8, other step is as shown in embodiment 21.
8. at the low-doped n type In of 760 ℃ of growth 2nm thickness
0.1Ga
0.9The highly doped n type of N and 2nm In
0.2Ga
0.8The N contact electrode layer.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 95%.
Embodiment 23
The growth of employing mocvd method.
1. the Sapphire Substrate in (0001) crystal orientation is put into reative cell, then at H
2Be warming up to 1050 ℃ in the environment, stablized 10 minutes, substrate is carried out high temperature purification.
2. be cooled to the gallium nitrate based resilient coating of low temperature of 530 ℃ of growth 20nm thickness.
3. be warming up to the non-doped gallium nitride of 1100 ℃ of growth 1 μ m thickness.
1100 ℃ the growth 1.5 μ m thickness n type gallium nitride.
5. at N
2The multiple quantum well layer in 10 cycles of growth in the environment, GaN builds layer: thickness is 20nm, and growth temperature is 860 ℃; InGaN trap layer: thickness is 2nm, and growth temperature is 760 ℃.
6. be warming up to the p-Al of 960 ℃ of growth 100nm thickness
0.15Ga
0.85The N layer.
7. at the p type gallium nitride of 930 ℃ of growth 150nm thickness.
8. at the low-doped p type In of 760 ℃ of growth 2nm thickness
0.1Ga
0.9The highly doped p type of N and 2nm In
0.2Ga
0.8The N contact electrode layer.
9. be cooled to room temperature, growth ending.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 92%.
Embodiment 24
The growth of employing mocvd method.
Except that the step 8, other step is as shown in embodiment 23.
8. at the low-doped n type In of 760 ℃ of growth 2nm thickness
0.1Ga
0.9The highly doped n type of N and 2nm In
0.2Ga
0.8The N contact electrode layer.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 94%.
Embodiment 25
The growth of employing mocvd method.
1. the Sapphire Substrate in (0001) crystal orientation is put into reative cell, then at H
2Be warming up to 1050 ℃ in the environment, stablized 10 minutes, substrate is carried out high temperature purification.
2. be cooled to the gallium nitrate based resilient coating of low temperature of 530 ℃ of growth 20nm thickness.
3. be warming up to the non-doped gallium nitride of 1100 ℃ of growth 1 μ m thickness.
1100 ℃ the growth 1.5 μ m thickness n type gallium nitride.
5. at N
2The multiple quantum well layer in 10 cycles of growth in the environment, GaN builds layer: thickness is 20nm, and growth temperature is 930 ℃; InGaN trap layer: thickness is 2nm, and growth temperature is 760 ℃.
6. be warming up to the p-Al of 960 ℃ of growth 100nm thickness
0.15Ga
0.85The N layer.
7. at the p type gallium nitride of 930 ℃ of growth 150nm thickness.
8. at the low-doped p type In of 760 ℃ of growth 2nm thickness
0.1Ga
0.9The highly doped p type of N and 2nm In
0.2Ga
0.8The N contact electrode layer.
9. be cooled to room temperature, growth ending.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 94%.
Embodiment 26
The growth of employing mocvd method.
Except that the step 8, other step is as shown in embodiment 25.
8. at the low-doped p type In of 760 ℃ of growth 1nm thickness
0.15Ga
0.85The highly doped p type of N and 2nm In
0.25Ga
0.75The N contact electrode layer.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 95%.
Embodiment 27
The growth of employing mocvd method.
Except that the step 8, other step is as shown in embodiment 25.
8. at the low-doped p type In of 760 ℃ of growth 1nm thickness
0.15Ga
0.85The highly doped p type of N and 3nm In
0.25Ga
0.75The N contact electrode layer.
Present embodiment is pressed 300 * 300 μ m that standard chips technology is made
2Be the chip of transparency electrode with ITO, the ESD yields of its reverse 4000V is 97%.
Claims (4)
1. GaN-based LED epitaxial wafer, its structure is followed successively by substrate, gallium nitrate based resilient coating, non-doped gallium nitride layer, n type gallium nitride layer, multiple quantum well layer, p type gallium aluminium nitrogen layer, p type gallium nitride layer and contact layer from bottom to up, it is characterized in that described contact layer is n type In
xGa
1-xThe N layer perhaps is p type In
xGa
1-xThe N layer, wherein x is a mole coefficient, 0＜x＜1.
2. GaN-based LED epitaxial wafer as claimed in claim 1 is characterized in that described n type In
xGa
1-xThe N layer comprises the low-doped n type In of low In component
xGa
1-xThe highly doped n type In of N layer and high In ingredient
xGa
1-xThe N layer;
Wherein, the low-doped n type In of described low In component
xGa
1-xThe N layer thickness is 1～5nm, selects for use Si to mix as the n type, and concentration is at 1e
-17Cm
-3～5e
-18Cm
-3, the scope of mole coefficient x is: 0.05≤x≤0.15;
The highly doped n type In of described high In ingredient
xGa
1-xThe N layer thickness is 1～5nm, selects for use Si to mix as the n type, and concentration is at 5e
-18Cm
-3～2e
-19Cm
-3, the scope of mole coefficient x is: 0.1≤x≤0.25.
3. GaN-based LED epitaxial wafer as claimed in claim 1 is characterized in that described p type In
xGa
1-xThe N layer comprises the low-doped p type In of low In component
xGa
1-xThe highly doped p type In of N layer and high In ingredient
xGa
1-xThe N layer;
Wherein, the low-doped p type In of low In component
xGa
1-xThe N layer thickness is 1～5nm, selects for use Mg to mix as the p type, and concentration is at 1e
-17Cm
-3～1e
-19Cm
-3, the scope of mole coefficient x is: 0.05≤x≤0.15;
The highly doped p type In of described high In ingredient
xGa
1-xThe N layer thickness is 1～5nm, selects for use Mg to mix as the p type, and concentration is at 1e
-19Cm
-3～5e
-20Cm
-3, the scope of mole coefficient x is: 0.1≤x≤0.25.
4. as the growing method of any described GaN-based LED epitaxial wafer of claim 1～3, adopt the MOCVD method, carry out following growth step successively:
1) under 1050～1250 ℃ at H
2The high temperature purification Sapphire Substrate is 5～10 minutes in the environment;
2) be cooled to the gallium nitrate based resilient coating of low temperature of 530～560 ℃ of growth 20～35nm thickness;
3) be warming up to 1100～1200 ℃ the growth 1～2.5 μ m thickness non-doped gallium nitride layer;
4) the n type gallium nitride layer of growth 1.5～3 μ m thickness;
5) be cooled to 740～860 ℃, the multiple quantum well layer of the InGaN/GaN in 5～15 cycles of growth;
6) be warming up to 960～1080 ℃, the p type gallium aluminium nitrogen layer of growth 30～120nm thickness;
7) the p type gallium nitride layer of growth 150～400nm thickness;
8) be cooled to 740～860 ℃, the n type In of growth 2～10nm thickness
xGa
1-xN layer or p type In
xGa
1-xThe N layer is as contact layer.
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| CN105161583A (en) * | 2015-06-24 | 2015-12-16 | 广西盛和电子科技股份有限公司 | GaN-based UV semiconductor LED and manufacturing method thereof |
| CN105977355A (en) * | 2016-05-09 | 2016-09-28 | 华灿光电股份有限公司 | LED epitaxial wafer and preparation method thereof |
| CN109037401A (en) * | 2018-06-21 | 2018-12-18 | 中国工程物理研究院电子工程研究所 | A kind of preparation method of gallium nitride base horizontal nano column core-shell structure array LED |
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