CN102194939B - A kind of GaN-based LED epitaxial wafer and growing method thereof - Google Patents

A kind of GaN-based LED epitaxial wafer and growing method thereof Download PDF

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CN102194939B
CN102194939B CN201010128437.5A CN201010128437A CN102194939B CN 102194939 B CN102194939 B CN 102194939B CN 201010128437 A CN201010128437 A CN 201010128437A CN 102194939 B CN102194939 B CN 102194939B
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type
growth
shell
thickness
gallium nitride
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CN102194939A (en
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王东盛
刘俊
关秋云
周德保
肖志国
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Dalian Meiming Epitaxial Wafer Technology Co Ltd
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Dalian Meiming Epitaxial Wafer Technology Co Ltd
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Abstract

A kind of GaN-based LED epitaxial wafer and growing method thereof, its structure sequentially consists of substrate, nitridation gallio cushion, undoped gallium nitride layer, n-type gallium nitride layer, multiple quantum well layer, p-type gallium nitride layer, p-type gallium nitride layer and contact layer, it is characterised in that described contact layer is N-shaped InxGa1‑xN shell, or be p-type InxGa1‑xN shell, wherein x is mole coefficient, 0 ＜ x ＜ 1.Obtain modulation doping contact layer epitaxial structure by adding the doped layer of In component and concentration gradient in contact layer, alleviate the electrostatic impact to gallium nitride based LED, improve the LED tolerance to electrostatic.It is fabricated to 300 × 300 μm according to standard chips technique2Chip, the ESD yields of its reverse 4000V is more than 90%.

Description

A kind of GaN-based LED epitaxial wafer and growing method thereof
Technical field
Invention relates to a kind of LED and growing method thereof, improves its antistatic energy particularly to one The GaN-based LED epitaxial wafer of power and growing method thereof, belong to technical field of semiconductors.
Background technology
Gallium nitride-based material, including InGaN, GaN, AlGaN alloy, for direct band-gap semicondictor, and band gap from 1.8～ 6.2eV continuously adjustabe, is to produce high brightness blue, green glow and the preferred material of white light LEDs, is widely used in full-color giant-screen and shows Show, LCD backlight, signal lights, the field such as illumination.
General employing ITO, as the GaN LED component of electrode, because ITO with pGaN directly contacts the worst, can cause Electric current density is uneven, and local current densities is excessive.And GaN base material grows on a sapphire substrate mostly, due to GaN base Lattice mismatch between material and Sapphire Substrate is relatively big, and about 13.5%, so substantial amounts of position can be produced in the epitaxial layer Mistake and defect, the density of defect is up to 1 × 108～1 × 1010/cm3.Because the local current densities of p-type electrode is too high, can make The electric charge of this position is along the pn-junction district of the defect entrance LED of epitaxial layer.Sapphire Substrate is insulant simultaneously, because rubbing, The factors such as sensing, conduction and the electrostatic charge that produces is difficult to discharge from substrate direction, when charge accumulated will be sent out to a certain extent Raw Electro-static Driven Comb phenomenon (Electro Static Discharge, ESD).Therefore the GaN base LED chip with sapphire as substrate belongs to In electrostatic sensitivity device, its antistatic effect is poor.Anti-ESD ability measured value under Human Body Model's standard of GaN base LED chip Typically smaller than ± 1000V is (with reference to Chang, S.J. et al. 2003 at Electron Device Letters, IEEE Volume The Improved ESD protection by combining InGaN-GaN MQW LEDswith that 24, Issue 3 deliver GaN Schottky diodes).Some mechanism introduces more complicated device system to improve the ESD of GaN base LED component Make method (China Patent Publication No. CN 1988119A), improve the cost that device manufactures.
Electro-static Driven Comb rapidly can occur with high intensity, when discharge current flows through the PN junction of LED, and the joule of generation Heat makes between chip PN the two poles of the earth local medium melt, and causes PN junction short circuit or electric leakage, thus cause LED component unexpected loss or Latent failure.Unexpected loss causes the eventual failure of LED, i.e. short circuit.Latent failure then can make the performance parameter of LED Deterioration, such as leakage current strengthen, and general GaN base LED be there is no any method by the hidden danger formed after electrostatic damage and can cure, And because parameter degradations causes vicious cycle, ultimately result in eventual failure.
Therefore, it is necessary to introduce new structure during extension to resist the ESD damage to device.The present invention is by using The contact layer structure of modulation doping, alleviates the electrostatic impact to gallium nitride based LED, improves LED to electrostatic in terms of Material growth Tolerance, save as improving the ESD of LED component and additional chip manufacturing cost.
Summary of the invention
It is an object of the invention to provide a kind of GaN-based LED epitaxial wafer structure and growing method thereof.Adjusted by employing Doped contact layers structure processed, produces two-dimensional hole gas in modulation doping contact layer, makes electric charge first along modulation doping interface Horizontal movement, thus the impact to instantaneous pressure electrostatic serves dispersion, the effect of buffering, reduces the destruction of high-pressure electrostatic Power, thus improve the antistatic effect of gallium nitride based LED device.
During technical scheme:
A kind of GaN-based LED epitaxial wafer, its structure sequentially consists of substrate, nitridation gallio cushion, undoped Gallium nitride layer, n-type gallium nitride layer, multiple quantum well layer, p-type gallium nitride layer, p-type gallium nitride layer and contact layer；This contact layer is N-shaped InxGa1-xN shell, or be p-type InxGa1-xN shell, wherein x is mole coefficient, 0 ＜ x ＜ 1.
Described N-shaped InxGa1-xN shell includes low-doped n-type In of low In componentxGa1-xN shell and high In ingredient highly doped N-shaped InxGa1-xN shell；Wherein: low-doped n-type In of described low In componentxGa1-xN shell thickness is 1～5nm, selects Si as N-shaped Doping, concentration is at le-17cm-3～5e-18cm-3, mole coefficient x is in the range of 0.05≤x≤0.15；The height of described high In ingredient Doping N-shaped InxGa1-xN shell thickness is 1～5nm, selects Si to adulterate as N-shaped, and concentration is at 5e-18cm-3～2e-19cm-3, mole it is Number x are in the range of 0.1≤x≤0.25.
Described p-type InxGa1-xN shell includes low doped p-type In of low In componentxGa1-xN shell and high In ingredient highly doped P-type InxGa1-xN shell；Wherein: low doped p-type In of low In componentxGa1-xN shell thickness is 1～5nm, selects Mg to mix as p-type Miscellaneous, concentration is at le-17cm-3～le-19cm-3, mole coefficient x is in the range of 0.05≤x≤0.15；The height of described high In ingredient is mixed Miscellaneous p-type InxGa1-xN shell thickness is 1～5nm, selects Mg to adulterate as p-type, and concentration is at le-19cm-3～5e-20cm-3, mole coefficient X is in the range of 0.1≤x≤0.25.
The present invention uses metal-organic chemical vapor deposition equipment method (MOCVD, Metalorganic ChemicalVapor Deposition) growth, the sapphire in substrate selection (0001) crystal orientation, metal organic source and nitrogen source are trimethyl gallium respectively (TMGa), trimethyl indium (TMIn), triethyl-gallium (TEGa), trimethyl aluminium (TMAl) and ammonia (NH3), n-type dopant is The H of 200ppm2Silane (the SiH carried4), p-type dopant is two cyclopentadienyl magnesium (Cp2Mg)。
The growing method of described GaN-based LED epitaxial wafer, uses MOCVD method, carries out following growth step successively:
1) at H at 1050～1250 DEG C2High temperature purification Sapphire Substrate 5～10 minutes in environment；
2) the low temperature nitride gallio cushion of 530～560 DEG C of growth 20～35nm thickness it is cooled to；
3) the undoped gallium nitride layer of 1100～1200 DEG C of growth 1～2.5 μ m thick it is warming up to；
4) n-type gallium nitride layer of 1.5～3 μ m thick is grown；
5) 740～860 DEG C it are cooled to, the multiple quantum well layer of the InGaN/GaN in 5～15 cycles of growth；
6) 960～1080 DEG C it are warming up to, the p-type gallium nitride layer of growth 30～120nm thickness；
7) the p-type gallium nitride layer of 150～400nm thickness is grown；
8) 740～860 DEG C it are cooled to, the N-shaped In of growth 2～10nm thicknessxGa1-xN shell or p-type InxGa1-xN shell conduct Contact layer.
Epitaxial wafer is fabricated to 300 × 300 μm according to standard chips technique2The chip with ITO as transparency electrode.To core The test of sheet anti-ESD ability, with reference to GJB 548A-1996 " microelectronic component Test Methods And Procedures ", uses Human Body Model's standard (HBM, Human Body Model), to 300 × 300 μm2Chip by, after the ESD of reverse 4000V, testing it reverse at 8V Leakage current under voltage, failure criteria is 0.5 μ A, and statistics reaches the yields of reverse leakage current (Ir) standard compliant chip.
It is an advantage of the current invention that: by using low-doped n-type In of low In componentxGa1-xN shell and the height of high In ingredient The In of doping N-shapedxGa1-xN shell, or low doped p-type In of low In componentxGa1-xThe highly-doped p-type of N shell and high In ingredient InxGa1-xThe contact layer that N shell is constituted, produces modulation because of the concentration difference of doping in two-layer equation contact layer structure and mixes at interface Miscellaneous structure., ESD the produced electric charge of instantaneous pressure electric discharge caused forms two-dimensional hole gas in modulation-doped structure, from And disperseed, reduce the density of the immediate current produced that sparks, thus reduce the ESD destructive power to device architecture, Improve the antistatic effect of device.300 × 300 μm made by standard chips technique2The core with ITO as transparency electrode Sheet, the ESD yields of its reverse 4000V is more than 90%.
Accompanying drawing explanation
Fig. 1: GaN-based LED epitaxial wafer structural representation schematic diagram.Wherein: 101 is substrate, 102 is low temperature nitride gallium Base cushion, 103 is undoped gallium nitride layer, and 104 is nitridation gallio n-layer, and 11 is multiple quantum well layer, and 105 is p-type aluminum gallium nitride Layer, 106 is gallium nitride based p type layer, and 12 is contact layer.
Detailed description of the invention
Embodiment 1
1. the Sapphire Substrate in (0001) crystal orientation is put in reative cell, then at H2Environment is warming up to 1050 DEG C, surely Fixed 10 minutes, substrate is carried out high temperature purification.
2. it is cooled to the low temperature nitride gallio cushion of 530 DEG C of growth 20nm thickness.
3. it is warming up to the undoped gallium nitride of 1100 DEG C of growth 1 μ m thick.
4. at the N-shaped gallium nitride of 1100 DEG C of growth 1.5 μ m thick.
5. at N2Growing the multiple quantum well layer in 10 cycles in environment, GaN barrier layer: thickness is 20nm, growth temperature is 850 ℃；InGaN well layer: thickness is 2nm, growth temperature is 810 DEG C.
6. it is warming up to p-type Al of 960 DEG C of growth 30nm thickness0.15Ga0.85N shell.
7. at the p-type gallium nitride of 940 DEG C of growth 150nm thickness.
8. in low doped p-type In of 810 DEG C of growth 2nm thickness0.1Ga0.9N and 2nm highly-doped p-type In0.2Ga0.8N electrode connects Contact layer.
9. being cooled to room temperature, growth terminates.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 95%.
Embodiment 2
Employing mocvd method grows: in addition to step 8, other step is as shown in Example 1.And the 8th step is:
8. in low-doped n-type In of 810 DEG C of growth 2nm thickness0.1Ga0.9N and 2nm doped n-type In0.2Ga0.8N electrode connects Contact layer.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 90%.
Embodiment 3
Employing mocvd method grows.
1. the Sapphire Substrate in (0001) crystal orientation is put in reative cell, then at H2Environment is warming up to 1050 DEG C, surely Fixed 10 minutes, substrate is carried out high temperature purification.
2. it is cooled to the low temperature nitride gallio cushion of 530 DEG C of growth 20nm thickness.
3. it is warming up to the undoped gallium nitride of 1100 DEG C of growth 1.5 μ m thick.
4. at the N-shaped gallium nitride of 1100 DEG C of growth 2 μ m thick.
5. at N2Growing the multiple quantum well layer in 5 cycles in environment, GaN barrier layer: thickness is 20nm, growth temperature is 850 ℃；InGaN well layer: thickness is 1.6nm, growth temperature is 810 DEG C.
6. it is warming up to p-type Al of 960 DEG C of growth 30nm thickness0.15Ga0.85N shell.
7. at the p-type gallium nitride of 940 DEG C of growth 150nm thickness.
8. in low doped p-type In of 810 DEG C of growth 2nm thickness0.05Ga0.95N and 2nm highly-doped p-type In0.1Ga0.9N electrode Contact layer.
9. being cooled to room temperature, growth terminates.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 92%.
Embodiment 4
Employing mocvd method grows.
In addition to step 8, other step is as shown in Example 3；
8. in low-doped n-type In of 810 DEG C of growth 2nm thickness0.05Ga0.95N and 2nm doped n-type In0.1Ga0.95N electrode Contact layer.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 94%.
Embodiment 5
Employing mocvd method grows.
In addition to step 8, other step is as shown in Example 3；
8. in low doped p-type In of 810 DEG C of growth 1nm thickness0.15Ga0.85N and 1nm highly-doped p-type In0.25Ga0.75N electricity Pole contact layer.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 95%.
Embodiment 6
Employing mocvd method grows.
In addition to step 8, other step is as shown in Example 4；
8. in low-doped n-type In of 810 DEG C of growth 1nm thickness0.15Ga0.85N and 1nm doped n-type In0.25Ga0.75N electricity Pole contact layer
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 92%.
Embodiment 7
Employing mocvd method grows.
In addition to step 8, other step is as shown in Example 3；
8. in low doped p-type In of 810 DEG C of growth 1nm thickness0.1Ga0.9N and 3nm highly-doped p-type In0.2Ga0.8N electrode connects Contact layer
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 96%.
Embodiment 8
Employing mocvd method grows.
In addition to step 8, other step is as shown in Example 4；
8. in low-doped n-type In of 810 DEG C of growth 1nm thickness0.1Ga0.9N and 3nm doped n-type In0.2Ga0.8N electrode connects Contact layer.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 94%.
Embodiment 9
Employing mocvd method grows.
In addition to step 8, other step is as shown in Example 3；
8. in low doped p-type In of 810 DEG C of growth 2nm thickness0.15Ga0.85N and 5nm highly-doped p-type In0.25Ga0.75N electricity Pole contact layer.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 99%.
Embodiment 10
Employing mocvd method grows.
In addition to step 8, other step is as shown in Example 4
8. in low-doped n-type In of 810 DEG C of growth 2nm thickness0.15Ga0.85N and 5nm doped n-type In0.25Ga0.75N electricity Pole contact layer.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 95%.
Embodiment 11
Employing mocvd method grows.
In addition to step 8, other step is as shown in Example 3；
8. in low doped p-type In of 810 DEG C of growth 5nm thickness0.15Ga0.85N and 1nm highly-doped p-type In0.25Ga0.75N electricity Pole contact layer.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 96%.
Embodiment 12
Employing mocvd method grows.
In addition to step 8, other step is as shown in Example 4；
8. in low-doped n-type In of 810 DEG C of growth 5nm thickness0.15Ga0.85N and 1nm doped n-type In0.25Ga0.75N electricity Pole contact layer.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 96%.
Embodiment 13
Employing mocvd method grows.
In addition to step 8, other step is as shown in Example 3；
8. in low doped p-type In of 760 DEG C of growth 1nm thickness0.15Ga0.85N and 1nm highly-doped p-type In0.25Ga0.75N electricity Pole contact layer.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 95%.
Embodiment 14
Employing mocvd method grows.
In addition to step 8, other step as shown in Example 4:
8. in low-doped n-type In of 760 DEG C of growth 1nm thickness0.15Ga0.85N and 3nm doped n-type In0.25Ga0.75N electricity Pole contact layer.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 94%.
Embodiment 15
Employing mocvd method grows.
In addition to step 8, other step as shown in Example 4:
8. in low doped p-type In of 760 DEG C of growth 2nm thickness0.15Ga0.85N and 2nm highly-doped p-type In0.25Ga0.75N electricity Pole contact layer.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 97%.
Embodiment 16
Employing mocvd method grows.
In addition to step 8, other step as shown in Example 4:
8. in low-doped n-type In of 760 DEG C of growth 2nm thickness0.15Ga0.85N and 2nm doped n-type In0.25Ga0.75N electricity Pole contact layer.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 94%.
Embodiment 17
Employing mocvd method grows.
1. the Sapphire Substrate in (0001) crystal orientation is put in reative cell, then at H2Environment is warming up to 1050 DEG C, surely Fixed 10 minutes, substrate is carried out high temperature purification.
2. it is cooled to the low temperature nitride gallio cushion of 530 DEG C of growth 20nm thickness.
3. it is warming up to the undoped gallium nitride of 1180 DEG C of growth 1 μ m thick.
4. at the N-shaped gallium nitride of 1180 DEG C of growth 1.5 μ m thick.
5. at N2Growing the multiple quantum well layer in 5 cycles in environment, GaN barrier layer: thickness is 20nm, growth temperature is 850 ℃；InGaN well layer: thickness is 1.6nm, growth temperature is 810 DEG C.
6. it is warming up to p-type Al of 1000 DEG C of growth 30nm thickness0.15Ga0.85N shell.
7. at the p-type gallium nitride of 950 DEG C of growth 150nm thickness.
8. in low doped p-type In of 810 DEG C of growth 2nm thickness0.1Ga0.9N and 2nm highly-doped p-type In0.2Ga0.8N electrode connects Contact layer.
9. being cooled to room temperature, growth terminates.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 97%.
Embodiment 18
Employing mocvd method grows.
In addition to step 8, other step as shown in Example 17:
8. in low-doped n-type In of 810 DEG C of growth 2nm thickness0.1Ga0.9N and 2nm doped n-type In0.2Ga0.8N electrode connects Contact layer.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 95%.
Embodiment 19
Employing mocvd method grows.
1. the Sapphire Substrate in (0001) crystal orientation is put in reative cell, then at H2Environment is warming up to 1050 DEG C, surely Fixed 10 minutes, substrate is carried out high temperature purification.
2. it is cooled to the low temperature nitride gallio cushion of 530 DEG C of growth 20nm thickness.
3. it is warming up to the undoped gallium nitride of 1180 DEG C of growth 1 μ m thick.
4. at the N-shaped gallium nitride of 1180 DEG C of growth 1.5 μ m thick.
5. at N2Growing the multiple quantum well layer in 15 cycles in environment, GaN barrier layer: thickness is 20nm, growth temperature is 850 ℃；InGaN well layer: thickness is 1.6nm, growth temperature is 810 DEG C.
6. at the p-type gallium nitride of 950 DEG C of growth 150nm thickness.
7. in low doped p-type In of 810 DEG C of growth 2nm thickness0.1Ga0.9N and 2nm highly-doped p-type In0.2Ga0.8N electrode connects Contact layer.
8. being cooled to room temperature, growth terminates.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 96%.
Embodiment 20
Employing mocvd method grows.
In addition to step 7, other step is as shown in Example 19
7. in low-doped n-type In of 810 DEG C of growth 2nm thickness0.1Ga0.9N and 2nm doped n-type In0.2Ga0.8N electrode connects Contact layer.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 94%.
Embodiment 21
Employing mocvd method grows.
1. the Sapphire Substrate in (0001) crystal orientation is put in reative cell, then at H2Environment is warming up to 1050 DEG C, surely Fixed 10 minutes, substrate is carried out high temperature purification.
2. it is cooled to the low temperature nitride gallio cushion of 530 DEG C of growth 20nm thickness.
3. it is warming up to the undoped gallium nitride of 1100 DEG C of growth 1 μ m thick.
4. at the N-shaped gallium nitride of 1100 DEG C of growth 1.5 μ m thick.
5. at N2Growing the multiple quantum well layer in 15 cycles in environment, GaN barrier layer: thickness is 20nm, growth temperature is 760 ℃；InGaN well layer: thickness is 1.6nm, growth temperature is 760 DEG C.
6. it is warming up to the p-Al of 960 DEG C of growth 30nm thickness0.15Ga0.85N shell
7. at the p-type gallium nitride of 930 DEG C of growth 150nm thickness.
8. in low doped p-type In of 760 DEG C of growth 2nm thickness0.1Ga0.9N and 2nm highly-doped p-type In0.2Ga0.8N electrode connects Contact layer.
9. being cooled to room temperature, growth terminates.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 94%.
Embodiment 22
Employing mocvd method grows.
In addition to step 8, other step is as shown in embodiment 21.
8. in low-doped n-type In of 760 DEG C of growth 2nm thickness0.1Ga0.9N and 2nm doped n-type In0.2Ga0.8N electrode connects Contact layer.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 95%.
Embodiment 23
Employing mocvd method grows.
1. the Sapphire Substrate in (0001) crystal orientation is put in reative cell, then at H2Environment is warming up to 1050 DEG C, surely Fixed 10 minutes, substrate is carried out high temperature purification.
2. it is cooled to the low temperature nitride gallio cushion of 530 DEG C of growth 20nm thickness.
3. it is warming up to the undoped gallium nitride of 1100 DEG C of growth 1 μ m thick.
4. at the N-shaped gallium nitride of 1100 DEG C of growth 1.5 μ m thick.
5. at N2Growing the multiple quantum well layer in 10 cycles in environment, GaN barrier layer: thickness is 20nm, growth temperature is 860 ℃；InGaN well layer: thickness is 2nm, growth temperature is 760 DEG C.
6. it is warming up to the p-Al of 960 DEG C of growth 100nm thickness0.15Ga0.85N shell.
7. at the p-type gallium nitride of 930 DEG C of growth 150nm thickness.
8. in low doped p-type In of 760 DEG C of growth 2nm thickness0.1Ga0.9N and 2nm highly-doped p-type In0.2Ga0.8N electrode connects Contact layer.
9. being cooled to room temperature, growth terminates.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 92%.
Embodiment 24
Employing mocvd method grows.
In addition to step 8, other step is as shown in embodiment 23.
8. in low-doped n-type In of 760 DEG C of growth 2nm thickness0.1Ga0.9N and 2nm doped n-type In0.2Ga0.8N electrode connects Contact layer.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 94%.
Embodiment 25
Employing mocvd method grows.
1. the Sapphire Substrate in (0001) crystal orientation is put in reative cell, then at H2Environment is warming up to 1050 DEG C, surely Fixed 10 minutes, substrate is carried out high temperature purification.
2. it is cooled to the low temperature nitride gallio cushion of 530 DEG C of growth 20nm thickness.
3. it is warming up to the undoped gallium nitride of 1100 DEG C of growth 1 μ m thick.
4. at the N-shaped gallium nitride of 1100 DEG C of growth 1.5 μ m thick.
5. at N2Growing the multiple quantum well layer in 10 cycles in environment, GaN barrier layer: thickness is 20nm, growth temperature is 930 ℃；InGaN well layer: thickness is 2nm, growth temperature is 760 DEG C.
6. it is warming up to the p-Al of 960 DEG C of growth 100nm thickness0.15Ga0.85N shell.
7. at the p-type gallium nitride of 930 DEG C of growth 150nm thickness.
8. in low doped p-type In of 760 DEG C of growth 2nm thickness0.1Ga0.9N and 2nm highly-doped p-type In0.2Ga0.8N electrode connects Contact layer.
9. being cooled to room temperature, growth terminates.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 94%.
Embodiment 26
Employing mocvd method grows.
In addition to step 8, other step is as shown in embodiment 25.
8. in low doped p-type In of 760 DEG C of growth 1nm thickness0.15Ga0.85N and 2nm highly-doped p-type In0.25Ga0.75N electricity Pole contact layer.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 95%.
Embodiment 27
Employing mocvd method grows.
In addition to step 8, other step is as shown in embodiment 25.
8. in low doped p-type In of 760 DEG C of growth 1nm thickness0.15Ga0.85N and 3nm highly-doped p-type In0.25Ga0.75N electricity Pole contact layer.
The present embodiment presses 300 × 300 μm that standard chips technique makes2The chip with ITO as transparency electrode, it is reverse The ESD yields of 4000V is 97%.

Claims (2)

1. a GaN-based LED epitaxial wafer, its structure sequentially consists of substrate, nitridation gallio cushion, undoped nitrogen Changing gallium layer, n-type gallium nitride layer, multiple quantum well layer, p-type gallium nitride layer, p-type gallium nitride layer and contact layer, described contact layer is N-shaped InxGa1-xN shell or be p-type InxGa1-xN shell；It is characterized in that described N-shaped InxGa1-xN shell includes the low miscellaneous n of low In component Type InxGa1-xThe height miscellaneous N-shaped In of N shell and high In ingredientxGa1-xN shell；Wherein, the low miscellaneous N-shaped of described low In component InxGa1-xN shell thickness is 1～5nm, selects Si to adulterate as N-shaped, and concentration is at 1e-17cm-3～5e-18cm-3, the model of mole coefficient x Enclose for 0.05≤x≤0.15；The height miscellaneous N-shaped In of described high In ingredientxGa1-xN shell thickness is 1～5nm, selects Si as n Type adulterates, and concentration is at 5e-18cm-3～2e-19cm-3, mole coefficient x is in the range of 0.1≤x≤0.25.
2. GaN-based LED epitaxial wafer as claimed in claim 1, it is characterised in that described p-type InxGa1-xN shell includes low In Low miscellaneous p-type In of componentxGa1-xMiscellaneous p-type In of height of N shell and high In ingredientxGa1-xN shell；Wherein, low In component is low miscellaneous P-type InxGa1-xN shell thickness is 1～5nm, selects Mg to adulterate as p-type, and concentration is at 1e-17cm-3～1e-19cm-3, mole coefficient x In the range of: 0.05≤x≤0.15；Miscellaneous p-type In of height of described high In ingredientxGa1-xN shell thickness is 1～5nm, selects Mg to make Adulterating for p-type, concentration is at 1e-19cm-3～5e-20cm-3, mole coefficient x is in the range of 0.1≤x≤0.25.
CN201010128437.5A 2010-03-16 A kind of GaN-based LED epitaxial wafer and growing method thereof Expired - Fee Related CN102194939B (en)

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CN101071836A (en) * 2007-04-10 2007-11-14 何清华 Epitaxial wafer growth method for improving galliumnitride base LED chip antistatic capability
CN101299449A (en) * 2008-06-20 2008-11-05 华南师范大学 GaN-based LED epitaxial wafer and preparation method thereof
CN101431141A (en) * 2007-09-14 2009-05-13 夏普株式会社 Nitride semiconductor light-emitting device
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CN101656288A (en) * 2005-07-06 2010-02-24 Lg伊诺特有限公司 Nitride semiconductor led
CN101071836A (en) * 2007-04-10 2007-11-14 何清华 Epitaxial wafer growth method for improving galliumnitride base LED chip antistatic capability
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