CN102194702A - Method for forming micro-spacing circuit tracing line - Google Patents
Method for forming micro-spacing circuit tracing line Download PDFInfo
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- CN102194702A CN102194702A CN 201010136397 CN201010136397A CN102194702A CN 102194702 A CN102194702 A CN 102194702A CN 201010136397 CN201010136397 CN 201010136397 CN 201010136397 A CN201010136397 A CN 201010136397A CN 102194702 A CN102194702 A CN 102194702A
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- heterosphere
- conductive metal
- metal layer
- circuit trace
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Abstract
The invention discloses a method for forming a micro-spacing circuit tracing line, comprising the following steps of: taking an insulating substrate; arranging a conductive metal layer on the substrate; then, wholly or partly arranging a heterogeneity layer on the upper surface of the conductive metal layer, wherein the etching rate of the heterogeneity layer is less than that of the conductive metal layer; next, forming a circuit tracing line pattern mask layer on the heterogeneity layer; then, performing wet etching; and finally, removing the mask layer and the heterogeneity layer, and then forming the micro-spacing circuit tracing line having high etching factors.
Description
Technical field
The present invention is relevant with the technology of printed circuit board (PCB) (PCB), particularly about a kind of on printed circuit board (PCB) the method for the little spacing of moulding (fine-pitch) circuit trace.
Background technology
The semiconductor integrated circuit element normally comes bearing semiconductor chip or other electron component with printed circuit board (PCB) or base plate for packaging, must arrange on described circuit board or the substrate that therefore circuit trace connects chip or electronic component forms electrically conducting.And up to now, described circuit trace major part all is to form with etching technique, and in all known etching techniques, wet etching is adopted the earliest, because this method economy is convenient, is therefore still adopted by most of dealer now.So-called wet etching, generally be meant on the plate face of an insulated substrate and arrange a conductive layer in advance, partially conductive laminar surface at desire formation circuit trace covers an etch stop layer then, the remaining conductive layer that will not have an etch stop layer with the etching solution of strong acid or highly basic again that continues is removed, and desired circuit trace like this promptly takes shape on this substrate.
As everyone knows, the employed etching solution of aforesaid wet etching is owing to have iso etch capabilities, and the phenomenon that therefore has lateral erosion (UnderCut) in downward etching process takes place.In more detail, if with copper be conductive layer and etching solution when being FeCl3, etched zone, except the part that faces down, etching solution also can be attacked the copper face of circuit both sides, thereby causes the etching defect as shape such as the mushroom.
The industry major part is with a kind of pointer of etching factor (Etch Factor) as etching quality at present, on behalf of the spacing of circuit trace, the value height of etching factor can dwindle, and that is to say that high etching factor (Etch Fact) can make little spacing of circuit trace or ultra micro spacingization.See also Fig. 1, so-called etching factor is meant 1/F, and F=(D1-D2)/2H, when etching factor was little, it was representing the top (D2) of circuit trace little, bottom (D1) is big, the phenomenon that is to say lateral erosion (UnderCut) is very serious, and described situation can make the interval of two adjacent circuit traces reduce and electron transfer (migration) takes place, simultaneously, because the section of circuit trace is not complete rectangle, therefore also can't arrange meticulous circuit trace.
In order to solve this kind disappearance, United States Patent (USP) the 5th, 545, the way that is proposed for No. 466 is the additional copper lamination of one granular (granular) between copper foil layer and insulated substrate, disclose according to this patent case, it is limited that this kind way is improved effect, only can make etching factor (Etch Factor) be increased to 4.
Summary of the invention
The base this, a kind ofly can be really arrange on circuit substrate that the method for little interval circuit trace still remains to be suggested, that is to say main purpose of the present invention be to provide a kind of on printed circuit board (PCB) or base plate for packaging the method for the little interval circuit trace of moulding, this method has and is high etching factor (Etch Factor than existing methods.
Another object of the present invention is that a kind of little interval circuit trace method of forming is being provided, and it still can have high etching factor under suitable traditional etching solution.
A further object of the present invention is then providing a kind of little interval circuit trace method of forming, and it can shorten etching period.
Be the purpose of taking off before reaching, a kind of little interval circuit trace method of forming provided by the present invention comprises takes an insulated substrate, arranges a conductive metal layer on this substrate.In the whole of a upper surface of this conductive metal layer or partly arrange a heterosphere, the rate of etch of this heterosphere is less than this conductive metal layer then.Continue it, on this heterosphere, form a circuit trace pattern cover curtain layer, then carry out Wet-type etching again, remove this cover curtain layer and this heterosphere at last again, can form little interval circuit trace with high etching factor.
Be the purpose of taking off before reaching, a kind of little interval circuit trace method of forming provided by the present invention comprises following step: take an insulated substrate; Prepare a base material, this base material includes a conductive metal layer and a heterosphere of arranging thereon, and the rate of etch of this heterosphere is arranged in this base material on this substrate in the mode of this conductive metal layer in the face of this substrate upper face less than this conductive metal layer; On the heterosphere of this base material, form a circuit trace pattern cover curtain layer; Use etching solution that this heterosphere and conductive metal layer are carried out etching; And remove this cover curtain layer and this heterosphere.
Be the purpose of taking off before reaching, a kind of little interval circuit trace method of forming provided by the present invention comprises following step: take an insulated substrate; On this substrate, arrange a conductive metal layer; Arrange a heterosphere in the upper surface of this conductive metal layer, the rate of etch of this heterosphere is less than this conductive metal layer; On this heterosphere, form a circuit trace pattern cover curtain layer; Need the heterosphere on the etching position to remove this conductive metal layer upper surface; Use etching solution to need etched position to carry out etching to this conductive metal layer; And remove this cover curtain layer and this heterosphere.
Be the purpose of taking off before reaching, a kind of little interval circuit trace method of forming provided by the present invention comprises following step: take an insulated substrate; On this substrate, arrange a conductive metal layer; On this conductive metal layer, form a circuit trace pattern cover curtain layer; Do not need in this conductive metal layer to arrange a heterosphere on the surface at etched position, the rate of etch of this heterosphere is less than this conductive metal layer; Remove this cover curtain layer; Carry out etching with etching solution; And remove this heterosphere.
Another feature of little interval circuit trace method of forming of the present invention is after can be earlier this heterosphere and this conductive metal layer being made a basic material, to be arranged on the substrate again.
The another feature of little interval circuit trace method of forming of the present invention is all to arrange this heterosphere in the surface of this conductive metal layer, the heterosphere on the palpus etching position is removed after this circuit trace pattern cover curtain layer forms then again, and etch process again continues.
A feature again of little interval circuit trace method of forming of the present invention is after the circuit trace pattern cover curtain layer is formed at the surface of conductive metal layer, heterosphere being arranged in this conductive metal layer does not need on the surface at etching position again, then this cover curtain layer is removed, and then the following etch process that continues.
Little interval circuit trace method of forming of the present invention again again a feature be to make the thickness of the heterosphere of being taken less than conductive metal layer, for example when the thickness of this conductive metal layer was 8 μ m, the thickness of this heterosphere was about 0.4～1.2 μ m.
Description of drawings
Fig. 1 is used for illustrating the schematic diagram how etching factor (Etch Factor) calculates;
Fig. 2 is the cross sectional view after arranging metal conducting layer and heterosphere on the substrate in the preferred embodiment of the little interval circuit trace of the present invention method of forming;
Fig. 3 is for arranging the schematic diagram that carries out wet etch process in the circuit trace pattern cover curtain layer in the preferred embodiment of the little interval circuit trace of the present invention method of forming;
Fig. 4 is the section photo with a circuit trace of available circuit trace method of forming institute moulding;
Fig. 5 is the circuit trace section photo with the preferred embodiment institute moulding of the little interval circuit trace of the present invention method of forming;
Fig. 6 is in the preferred embodiment again of the little interval circuit trace of the present invention method of forming, the cross sectional view after arranging metal conducting layer and cover curtain layer on the substrate;
Fig. 7 is arranged in the lip-deep schematic diagram that this conductive metal layer does not need the etching position in the preferred embodiment again of the little interval circuit trace of the present invention method of forming with heterosphere; And
Fig. 8 will carry out the schematic diagram of etch process in the preferred embodiment again of the little interval circuit trace of the present invention method of forming after the cover curtain layer removal.
[main element symbol description]
Heterosphere 30
Iron chloride (FeCl3) etching solution 50
Copper metal conducting layer 62
Circuit trace pattern cover curtain layer 64
Do not need the surface 66 at etching position
Heterosphere 70
Embodiment
Below for an embodiment and conjunction with figs. little interval circuit trace method of forming of the present invention is described further now, it must be appreciated that this just is used for illustrating, can not be used for limiting claim of the present invention, wherein:
At first see also Fig. 2 to Fig. 5, a kind of little interval circuit trace method of forming of the present invention at first takes one to gather the insulated substrate 10 that inferior acyl ammonium is made when implementing, arrange that at substrate 10 thickness is about the copper metal conducting layer 20 of 7.97 μ m then; Continue it, be about the heterosphere 30 of 0.792 μ m in conductive layer 20 upper surface plating, chemistry or sputter one thickness, in present embodiment, heterosphere 30 can select for use nickel metal or tin metal to prepare.What must one carry at this is that copper metal conducting layer 20 also can be prepared into a base material in advance with heterosphere 30 and then is arranged on the substrate 10.
Then, be coated with a photoresist layer (not showing on the figure) in heterosphere 30 upper surfaces, this photoresist layer is exposed and developing process and form a circuit trace pattern cover curtain layer 40, the formation of this kind cover curtain layer 40 is owing to be that therefore well-known technology does not describe in detail at this place again.
Follow again, 15～45 degree for example Celsius under a specified temp, take 50 pairs of copper metal conducting layers of iron chloride (FeCl3) etching solution 20 and carry out etching with heterosphere 30, at last, after the circuit trace moulding, the step that continues is to divest cover curtain layer 40, and then removes heterosphere 30 with suitable etchant.
From the above; the little interval circuit trace of the present invention method of forming is when carrying out etching with traditional FeCl3 etching solution; for the heterosphere made from nickel metal or tin metal 30; its rate of etch is slow with the rate of etch of the metal conductive layer 20 of copper; so the copper face that will make both sides, etched place is subjected to the protection of heterosphere 30; in other words, so-called lateral erosion (UnderCut) phenomenon will be lowered greatly.Thus, etching solution is concentrated attacked positive part, and shorten etching period, the top (D2) of circuit trace and bottom (D1) stand out be reduced, and improve etching factor (Etch Factor).
Shown in Fig. 5 photo, its D 1 of the circuit trace of present embodiment institute moulding is 8.4 μ m, and D2 is 7.29 μ m, H (thickness of main stor(e)y 12) 7.97 μ m, and data can be calculated etching factor (Etch Factor) and are about 14.4 thus.And as with traditional Copper Foil during as conductive layer, the circuit trace of its moulding as shown in Figure 4, D1 is 14.14 μ m, D2 is 7.41 μ m, H (thickness of main stor(e)y 12) 7.09 μ m, data can be calculated its etching factor (Etch Factor) and are about 2.2 thus.
The aforementioned method for making of the present invention also can be removed the heterosphere 30 on the palpus etching position after this circuit trace pattern cover curtain layer 40 is formed at the surface of heterosphere 30 on the implementation again, and following etch process then continues.
Please consult Fig. 6 to Fig. 8 again, an embodiment again of method for making of the present invention takes an insulated substrate 60 earlier, arranges the copper metal conducting layer 62 of one deck tool predetermined thickness then at substrate 60; Continue it, form a circuit trace pattern cover curtain layer 64 in conductive metal layer 62 upper surfaces.Then, then do not need to arrange on the surface 66 at etching position a heterosphere 70 at conductive metal layer 62, then circuit trace pattern cover curtain layer 64 is removed, last again with the etching solution 80 of hydrogen peroxide the mixings sulfuric acid following etch process that continues, same also can forming like this has little interval circuit trace of high etching factor.
Claims (18)
1. little interval circuit trace method of forming is characterized in that, comprises following step:
Take an insulated substrate;
On this substrate, arrange a conductive metal layer;
Arrange a heterosphere in the whole of this conductive metal layer upper surface or part, the rate of etch of this heterosphere is less than this conductive metal layer;
On this heterosphere, form a circuit trace pattern cover curtain layer;
Use etching solution that this heterosphere and conductive metal layer are carried out etching; And
Remove this cover curtain layer and this heterosphere.
2. little interval circuit trace method of forming as claimed in claim 1 is characterized in that this conductive metal layer includes the copper metal.
3. little interval circuit trace method of forming as claimed in claim 1 is characterized in that, in this conductive metal layer include copper alloy.
4. as claim 2,3 described little interval circuit trace methods of forming, it is characterized in that this heterosphere includes nickel (Ni) metal.
5. as claim 2,3 described little interval circuit trace methods of forming, it is characterized in that this heterosphere includes tin (Sn) metal.
6. little interval circuit trace method of forming as claimed in claim 1 is characterized in that the thickness of this heterosphere is less than this conductive metal layer.
7. little interval circuit trace method of forming as claimed in claim 4 is characterized in that this heterosphere is to be arranged on this conductive metal layer with plating, chemistry or sputtering method.
8. little interval circuit trace method of forming as claimed in claim 4 is characterized in that this etching solution is iron chloride (FeCl3).
9. little interval circuit trace method of forming is characterized in that, comprises following step:
Take an insulated substrate;
Prepare a base material, this base material includes a conductive metal layer and a heterosphere of arranging thereon, and the rate of etch of this heterosphere is arranged in this base material on this substrate in the mode of this conductive metal layer in the face of this substrate upper face less than this conductive metal layer;
On the heterosphere of this base material, form a circuit trace pattern cover curtain layer;
Use etching solution that this heterosphere and conductive metal layer are carried out etching; And
Remove this cover curtain layer and this heterosphere.
10. little interval circuit trace method of forming as claimed in claim 9 is characterized in that this conductive metal layer includes the copper metal.
11. little interval circuit trace method of forming as claimed in claim 9 is characterized in that this conductive metal layer includes copper alloy.
12., it is characterized in that this heterosphere includes nickel (Ni) metal as claim 10,11 described little interval circuit trace methods of forming.
13. little interval circuit trace method of forming as claimed in claim 12 is characterized in that employed etching solution is iron chloride (FeCl3).
14., it is characterized in that this heterosphere includes tin (Sn) metal as claim 10,11 described little interval circuit trace methods of forming.
15. little interval circuit trace method of forming as claimed in claim 9 is characterized in that the thickness of this heterosphere is less than this conductive metal layer.
16. little interval circuit trace method of forming is characterized in that, comprises following step:
Take an insulated substrate;
On this substrate, arrange a conductive metal layer;
Arrange a heterosphere in the upper surface of this conductive metal layer, the rate of etch of this heterosphere is less than this conductive metal layer;
On this heterosphere, form a circuit trace pattern cover curtain layer;
Need the heterosphere on the etching position to remove this conductive metal layer upper surface;
Use etching solution to need etched position to carry out etching to this conductive metal layer; And
Remove this cover curtain layer and this heterosphere.
17. little interval circuit trace method of forming is characterized in that, comprises following step:
Take an insulated substrate;
On this substrate, arrange a conductive metal layer;
On this conductive metal layer, form a circuit trace pattern cover curtain layer;
Do not need in this conductive metal layer to arrange a heterosphere on the surface at etched position, the rate of etch of this heterosphere is less than this conductive metal layer;
Remove this cover curtain layer;
Carry out etching with etching solution; And
Remove this heterosphere.
18. little interval circuit trace method of forming as claimed in claim 17 is characterized in that employed etching solution includes hydrogen peroxide and sulfuric acid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010136397 CN102194702A (en) | 2010-03-12 | 2010-03-12 | Method for forming micro-spacing circuit tracing line |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010136397 CN102194702A (en) | 2010-03-12 | 2010-03-12 | Method for forming micro-spacing circuit tracing line |
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| Publication Number | Publication Date |
|---|---|
| CN102194702A true CN102194702A (en) | 2011-09-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010136397 Pending CN102194702A (en) | 2010-03-12 | 2010-03-12 | Method for forming micro-spacing circuit tracing line |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102678604A (en) * | 2012-04-19 | 2012-09-19 | 台达电子企业管理（上海）有限公司 | Radiating fan and metal etching method for base of radiating fan |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02109392A (en) * | 1988-10-18 | 1990-04-23 | Mitsubishi Electric Corp | Circuit-pattern forming method |
| JPH0681172A (en) * | 1992-09-01 | 1994-03-22 | Hitachi Cable Ltd | Formation of fine pattern |
| JP2007180172A (en) * | 2005-12-27 | 2007-07-12 | Mec Kk | Manufacturing method of board |
| CN102111956A (en) * | 2009-12-29 | 2011-06-29 | 旭德科技股份有限公司 | Base material for printed circuit board |
-
2010
- 2010-03-12 CN CN 201010136397 patent/CN102194702A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02109392A (en) * | 1988-10-18 | 1990-04-23 | Mitsubishi Electric Corp | Circuit-pattern forming method |
| JPH0681172A (en) * | 1992-09-01 | 1994-03-22 | Hitachi Cable Ltd | Formation of fine pattern |
| JP2007180172A (en) * | 2005-12-27 | 2007-07-12 | Mec Kk | Manufacturing method of board |
| CN102111956A (en) * | 2009-12-29 | 2011-06-29 | 旭德科技股份有限公司 | Base material for printed circuit board |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102678604A (en) * | 2012-04-19 | 2012-09-19 | 台达电子企业管理（上海）有限公司 | Radiating fan and metal etching method for base of radiating fan |
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Application publication date: 20110921 |