JPH02109392A - Circuit-pattern forming method - Google Patents
Circuit-pattern forming methodInfo
- Publication number
- JPH02109392A JPH02109392A JP26227688A JP26227688A JPH02109392A JP H02109392 A JPH02109392 A JP H02109392A JP 26227688 A JP26227688 A JP 26227688A JP 26227688 A JP26227688 A JP 26227688A JP H02109392 A JPH02109392 A JP H02109392A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- pattern
- plating
- metal
- circuit pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000007747 plating Methods 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000004020 conductor Substances 0.000 claims abstract description 25
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 17
- 229910052802 copper Inorganic materials 0.000 abstract description 11
- 239000010949 copper Substances 0.000 abstract description 11
- 238000005530 etching Methods 0.000 abstract description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 6
- 239000011889 copper foil Substances 0.000 abstract description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 4
- 239000010931 gold Substances 0.000 abstract description 4
- 229910052737 gold Inorganic materials 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 229910052759 nickel Inorganic materials 0.000 abstract description 3
- 229910052718 tin Inorganic materials 0.000 abstract description 3
- 239000011135 tin Substances 0.000 abstract description 3
- 229910021578 Iron(III) chloride Inorganic materials 0.000 abstract description 2
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000007788 liquid Substances 0.000 abstract 2
- 229910000978 Pb alloy Inorganic materials 0.000 abstract 1
- 229910001128 Sn alloy Inorganic materials 0.000 abstract 1
- 230000003213 activating effect Effects 0.000 abstract 1
- 230000000873 masking effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 229910001174 tin-lead alloy Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000001994 activation Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002120 nanofilm Substances 0.000 description 1
- 238000005554 pickling Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
Landscapes
- Engineering & Computer Science (AREA)
- Metallurgy (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はプリントＢｅｇ、基板などの絶縁基板上に回
路パターンを形成する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming a circuit pattern on an insulating substrate such as a printed circuit board or a substrate.
従来のサブトラクト法における回路パターンの形成方法
は、銅箔を張り付けた基板、あるいは全面に無電解銅め
っきを施したプラスチックまたはセラミック製の絶縁基
板を用いて、回路パターン状に形成された感光性高分子
膜をマスクとして、不要部分の導体部分をエツチング除
去し５導体回路を形成していた。The conventional method of forming circuit patterns using the subtract method uses a substrate covered with copper foil, or an insulating substrate made of plastic or ceramic with electroless copper plating applied to the entire surface. Using the molecular film as a mask, unnecessary conductor parts were removed by etching to form a five-conductor circuit.
第４図はたとえば機能成膜プロセス技術、 ｐ１４５（
通板、二瓶編、広信社発行、１９８７年６Ｊ］）に示さ
れた従来の回路パターンの形成方法を示す工程図、第５
図（Ａ）〜（Ｅ）はその各工程における断面図である。Figure 4 shows, for example, functional film formation process technology, p145 (
Process diagram showing the conventional circuit pattern formation method shown in Tsuita, Nihei, ed., published by Koshinsha, 1987, 6J], No. 5
Figures (A) to (E) are cross-sectional views at each step.
図において、（１）は絶縁基板、（２）は絶縁基板（１
）の」二に形成された銅箔または無電解銅めっき膜等の
導体層である。In the figure, (1) is an insulating substrate, (2) is an insulating substrate (1
) is a conductor layer made of copper foil or electroless copper plating film.
回路パターンの形成方法は、第５図（Ａ）に示すように
たとえば銅箔を張り付けて導体層（２）を形成した絶縁
基板（１）の上に、（Ｂ）に示すようにレジス１へ塗布
により感光性のレジスｌ−１１１（３ａ）を形成し、回
路パターンを描いであるフィルムを介して紫外光線で露
光したのち、現像を行って、（Ｃ）に示すようにレジス
トパターン（３ｂ）を形成し、回路部分以外の導体層（
２）を露出させる。その後、（Ｄ）に示すように露出し
た導体層（２）を銅パターンエツチングによって溶解除
去し、導体回路パターン（４）を形成し、（Ｅ）に示す
ようにレジストパターン（３ｂ）を剥離する。The method for forming the circuit pattern is as shown in FIG. 5(A), for example, by pasting copper foil onto an insulating substrate (1) on which a conductor layer (2) is formed, and then placing it on a resist 1 as shown in FIG. 5(B). A photosensitive resist 1-111 (3a) is formed by coating, and a circuit pattern is drawn through the film and exposed to ultraviolet light, followed by development to form a resist pattern (3b) as shown in (C). , and the conductor layer other than the circuit part (
2) Expose. Thereafter, as shown in (D), the exposed conductor layer (2) is dissolved and removed by copper pattern etching to form a conductor circuit pattern (4), and the resist pattern (3b) is peeled off as shown in (E). .
しかるに従来の回路パターンの形成方法では、レジスト
膜形成工程および露光工程は乾式加工であり、現像およ
びエツチング工程は湿式加工であるというように、異質
の加工工程を必要とし、またこのために工程数が増える
要因ともなっている。However, conventional circuit pattern formation methods require different processing steps, such as dry processing for resist film formation and exposure, and wet processing for development and etching. It is also a factor in the increase.
この発明はかかる問題点を解決するためのもので、レー
ザを利用したパターン形成法を用いることにより、全工
程を湿式法に統一した形式で、連続的かつ直接的にプリ
ント配線板やｌｌＩｃなどの回路パターンを形成する方
法を提供するものである。This invention is intended to solve this problem, and by using a pattern forming method using a laser, the entire process is unified to a wet method, and printed wiring boards, llc, etc. can be continuously and directly formed. A method for forming a circuit pattern is provided.
この発明の回路パターンの形成方法は、導体層を形成し
た基板に対して、めっき液中でレーザを照射して金属回
路パターンを描画形成し、この金属回路パターンをマス
クとして、不要導体層部分をエツチング除去する方法で
ある。The circuit pattern forming method of the present invention involves drawing and forming a metal circuit pattern by irradiating a substrate on which a conductor layer is formed with a laser in a plating solution, and using this metal circuit pattern as a mask, unnecessary conductor layer parts are removed. This is a method of removing by etching.
本発明においては、導体層を形成した基板に対して、め
っき液中でレーザを照射して金属回路パターンを描画形
成し、この金属回路パターンをマスクとして、不要導体
層部分をエツチング除去することにより、全工程は湿式
法により連続的に絶縁基板」二にパターン形成を行うこ
とができる。In the present invention, a metal circuit pattern is formed by irradiating a laser in a plating solution onto a substrate on which a conductor layer has been formed, and unnecessary conductor layer portions are etched away using this metal circuit pattern as a mask. The whole process can be carried out continuously to form a pattern on the insulating substrate by a wet method.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図はこの発明の一実施例を示す工程図、第２図（Ａ
）〜（Ｄ）はその各工程における断面図であり。Fig. 1 is a process diagram showing an embodiment of the present invention, Fig. 2 (A
) to (D) are cross-sectional views in each step.
第４図および第５図と同一符号は同一または相当部分を
示す。The same reference numerals as in FIGS. 4 and 5 indicate the same or corresponding parts.
回路パターンの形成方法は、第２図（Ａ）に示すように
、銅箔を張り付け、あるいは全面に無電解銅めっきを施
して導体層（２）を形成したプラスチックまたはセラミ
ック製の絶縁基板（１）を、脱脂・洗浄および酸洗・活
性化後めっき液中に浸漬し、（Ｂ）に示すようにレーザ
めっきによって回路パターン状に金属マスクパターン（
３）を析出させる。As shown in Figure 2 (A), the circuit pattern is formed on a plastic or ceramic insulating substrate (1) on which a conductor layer (2) is formed by pasting copper foil or electroless copper plating on the entire surface. ) is immersed in a plating solution after degreasing, cleaning, pickling, and activation, and as shown in (B), a metal mask pattern (
3) is precipitated.
このとき描画される金属マスクパターン（３）は金また
は錫鉛合金などが望ましい、金属マスクパターン（３）
を描画したのち、銅のエツチング液中に浸漬し、（Ｃ）
に示すように金属マスクパターン（３）が析出している
部分以外の導体層（２）をエツチング除去することによ
って、導体回路パターン（４）を形成する。導体回路パ
ターン（４）上のレーザめっきによって析出した金属マ
スクパターン（３）は、後で溶解除去してもよいし、そ
のまま残しておいてもよい。The metal mask pattern (3) drawn at this time is preferably gold or a tin-lead alloy.
After drawing, immerse it in copper etching solution and (C)
As shown in FIG. 3, a conductor circuit pattern (4) is formed by etching away the conductor layer (2) other than the portion where the metal mask pattern (3) is deposited. The metal mask pattern (3) deposited by laser plating on the conductor circuit pattern (4) may be dissolved and removed later, or may be left as is.
本発明に係わる導体回路パターン（４）の金属とマスク
のための金属マスクパターン（３）の金属は。The metal of the conductor circuit pattern (4) and the metal of the metal mask pattern (3) for the mask according to the present invention are as follows.
金属マスクパターン（３）の金属が溶解せず、導体回路
パターン（４）の金属のみ溶解するエツチング方法があ
る場合は、上述した組合せでなくてもさしつかえないが
、導体回路パターン（４）の金属が銅で、金属マスクパ
ターン（３）の金属が金、ニッケル、錫、錫鉛合金など
であることが望ましい。If there is an etching method that does not dissolve the metal of the metal mask pattern (3) but only dissolves the metal of the conductor circuit pattern (4), the combination described above does not have to be used, but the metal of the conductor circuit pattern (4) It is desirable that the metal mask pattern (3) is made of copper, and the metal of the metal mask pattern (3) is gold, nickel, tin, tin-lead alloy, or the like.
第３図は実施例におけるレーザめっき装置の概略を示す
構成図である６図において、（５）はレーザ装置、（６
）は光学装置、（７）は石英製のガラス窓（７ａ）を有
するめっきセル、（８）はめっき液タンク（９）からめ
っき液を循環するためのポンプ、 （１，０）はめっき
電源、（１１）は対極、 （１２）はＣＡＤ、（１３）
はコントローラーである。めっき液はめっきタンク（９
）よりポンプ（８）によってめっきセル（７）に供給さ
れる。レーザ光は石英製のガラス窓（７８）を通して、
めっきセル（７）の底部に設置された基板（１）に集光
照射されるようになっている。めっきのための電流はめ
っき電源（１０）より供給される。またこのときの対極
（ＩＩ）と基板（１）との間の電圧は、基板（１）上に
めっきが析出せず、かつレーザ照射によりめっき反応が
誘起可能な表面電位となるように設定されている。なお
、ここでは電気めっきの場合を取り上げたが、無電解め
っきによって金属マスクパターン（３）を描画する場合
は、電源（１０）及び対極（１１）はなくても差し支え
ない、めっき液はその種類によって異なるが、タンク（
９）内の温度管理装置によって温度管理されている。管
理される駄度はめっき液によって異なるが、電気めっき
の場合一般に室温以下の温度に制御されるのが望ましい
。FIG. 3 is a configuration diagram showing an outline of the laser plating apparatus in the example. In FIG. 6, (5) is the laser device, (6)
) is an optical device, (7) is a plating cell with a quartz glass window (7a), (8) is a pump for circulating the plating solution from the plating solution tank (9), and (1,0) is the plating power source. , (11) is the opposite, (12) is CAD, (13)
is the controller. The plating solution is stored in the plating tank (9
) is supplied to the plating cell (7) by a pump (8). The laser beam passes through a quartz glass window (78),
The condensed light is irradiated onto the substrate (1) installed at the bottom of the plating cell (7). Current for plating is supplied from a plating power source (10). Further, the voltage between the counter electrode (II) and the substrate (1) at this time is set so that no plating is deposited on the substrate (1) and the surface potential is such that a plating reaction can be induced by laser irradiation. ing. Although the case of electroplating has been taken up here, when drawing the metal mask pattern (3) by electroless plating, there is no problem even if the power supply (10) and counter electrode (11) are not used, and the type of plating solution is Depending on the tank (
The temperature is controlled by the temperature control device in 9). The degree of spoilage that is controlled varies depending on the plating solution, but in the case of electroplating, it is generally desirable to control the temperature to below room temperature.
以下、レーザめっきのプロセスを順を追って説明する。The laser plating process will be explained step by step below.
銅箔を張りつけた基板、あるいは全面に無電解鋼めっき
を施したプラスチックまたはセラミック等の絶縁基板（
１）を脱脂、酸洗を行い、活性化処理を行う。次に、め
っきセル（７）の底部に設置し、めっき液を基板表面に
流す。次にレーザビームが基板（１）の表面に照射され
る。照射された部分では、局部的な加熱により電気化学
的な平衡のずれを引き起こし、またイオン供給などが増
大するため、照射された部分のみに金属が析出する。A board covered with copper foil, or an insulating board made of plastic or ceramic with electroless steel plating on the entire surface (
1) is degreased, pickled, and activated. Next, it is installed at the bottom of the plating cell (7), and the plating solution is flowed onto the surface of the substrate. Next, a laser beam is irradiated onto the surface of the substrate (1). In the irradiated area, local heating causes a shift in electrochemical equilibrium, and the supply of ions increases, so metal is deposited only in the irradiated area.
レーザビームはコントローラ（１３）によってＣＡＤ（
１２）のデータに従って走査され１回路パターンを描画
する。形成される金属マスクパターン（３）の金属は、
めっき液によって任意に選択できるが、金、ニッケル、
錫、錫鉛合金など銅のエツチング溶液に犯されないもの
であることが望ましい。The laser beam is controlled by the controller (13) using CAD (
12) to draw one circuit pattern. The metal of the metal mask pattern (3) to be formed is
It can be selected arbitrarily depending on the plating solution, but gold, nickel,
It is desirable that the material be made of tin, tin-lead alloy, etc., which is not affected by copper etching solutions.
次に回路パターンが描画された基板（１）は塩化第２鉄
溶液中へ浸漬、または同溶液のシャワー中に曝す。金属
マスクパターン（３）が形成されていない部分の銅は同
溶液中に溶解し、レーザビームで描画したパターン部分
のみが残る。この後、金属マスクパターン（３）を溶解
液で除去すれば導体回路パターン（４）のみが残る。金
属マスクパターン（３）は、溶解除去してもよいし、そ
のまま残しても１回路の機能上は差し支えない。Next, the substrate (1) on which the circuit pattern has been drawn is immersed in a ferric chloride solution or exposed to a shower of the same solution. The copper in the area where the metal mask pattern (3) is not formed is dissolved in the same solution, leaving only the patterned area drawn by the laser beam. Thereafter, if the metal mask pattern (3) is removed with a solution, only the conductor circuit pattern (4) remains. The metal mask pattern (3) may be removed by dissolving it, or may be left as is without any problem in terms of the functionality of one circuit.
本発明によれば、従来の感光性エツチングレジストによ
る回路マスクパターン形成法を、レーザめっき法を用い
た金属マスクパターン直接形成法にすることによって、
レジスト材料の省略、工程の短縮、工程の種類を湿式法
に統一できること等のほかに、レーザで直接描画するの
で回路変更が容易に行えるなどの効果がある。According to the present invention, by changing the conventional method of forming a circuit mask pattern using a photosensitive etching resist to a method of directly forming a metal mask pattern using a laser plating method,
In addition to eliminating the need for resist materials, shortening the process, and unifying the type of process to a wet method, it also has advantages such as the ability to easily change circuits because it draws directly with a laser.
第１図はこの発明の一実施例による回路パターンの形成
方法を示す工程図、第２図（Ａ）〜（Ｄ）はその各工程
における断面図、第３図はこの発明の一実施例における
レーザめっき装置を示す構成図。
第４図は従来の回路パターンの形成方法を示す工程図、
第５図（Ａ）〜（Ｅ）はその各工程における断面図であ
る。
各図中、同一符号は同一または相当部分を示し、（１）
は絶縁基板、（２）は導体層、（３）は金属マスクパタ
ーン、（４）は導体回路パターン、（５）はレーザ装置
、（６）は光学装置、（７）はめっきセル、（９）はめ
っき液タンク、 （ｉｏ）はめっきｆｆ１ｇ、 （１１
）は対極である。
第３図FIG. 1 is a process diagram showing a method for forming a circuit pattern according to an embodiment of the present invention, FIGS. 2A to 2D are cross-sectional views in each step, and FIG. FIG. 1 is a configuration diagram showing a laser plating apparatus. FIG. 4 is a process diagram showing a conventional method of forming a circuit pattern.
FIGS. 5A to 5E are cross-sectional views at each step. In each figure, the same reference numerals indicate the same or corresponding parts, (1)
is an insulating substrate, (2) is a conductor layer, (3) is a metal mask pattern, (4) is a conductor circuit pattern, (5) is a laser device, (6) is an optical device, (7) is a plating cell, (9 ) is the plating solution tank, (io) is the plating ff1g, (11
) is the opposite. Figure 3
Claims (1)
ーザを照射して金属回路パターンを描画形成し、この金
属回路パターンをマスクとして、不要導体層部分をエッ
チング除去することを特徴とする回路パターンの形成方
法。(1) The substrate on which the conductor layer has been formed is irradiated with a laser in a plating solution to draw and form a metal circuit pattern, and using this metal circuit pattern as a mask, unnecessary conductor layer portions are etched away. A method for forming circuit patterns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26227688A JPH02109392A (en) | 1988-10-18 | 1988-10-18 | Circuit-pattern forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26227688A JPH02109392A (en) | 1988-10-18 | 1988-10-18 | Circuit-pattern forming method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02109392A true JPH02109392A (en) | 1990-04-23 |
Family
ID=17373547
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26227688A Pending JPH02109392A (en) | 1988-10-18 | 1988-10-18 | Circuit-pattern forming method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02109392A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194702A (en) * | 2010-03-12 | 2011-09-21 | 旭德科技股份有限公司 | Method for forming micro-spacing circuit tracing line |
| CN106061125A (en) * | 2016-06-20 | 2016-10-26 | 河源西普电子有限公司 | Electroplating device for flexible printed circuit board |
-
1988
- 1988-10-18 JP JP26227688A patent/JPH02109392A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194702A (en) * | 2010-03-12 | 2011-09-21 | 旭德科技股份有限公司 | Method for forming micro-spacing circuit tracing line |
| CN106061125A (en) * | 2016-06-20 | 2016-10-26 | 河源西普电子有限公司 | Electroplating device for flexible printed circuit board |
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