US20130068517A1 - Substrate structure and method for manufacturing the same - Google Patents
Substrate structure and method for manufacturing the same Download PDFInfo
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- US20130068517A1 US20130068517A1 US13/673,868 US201213673868A US2013068517A1 US 20130068517 A1 US20130068517 A1 US 20130068517A1 US 201213673868 A US201213673868 A US 201213673868A US 2013068517 A1 US2013068517 A1 US 2013068517A1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0352—Differences between the conductors of different layers of a multilayer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/025—Abrading, e.g. grinding or sand blasting
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
- H05K3/045—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by making a conductive layer having a relief pattern, followed by abrading of the raised portions
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Definitions
- the invention relates in general to a substrate structure and a method for manufacturing the same, and more particularly to a substrate structure with a substrate whose two surfaces has different structures and a method for manufacturing the same.
- the design of the circuit board is gradually directed towards ultrafine lines.
- the invention is directed to a substrate structure and a method for manufacturing the same.
- the invention has the advantages of thin thickness and low manufacturing cost.
- a method for manufacturing a substrate structure includes the following steps.
- a substrate is provided, wherein the substrate has a patterned first metal layer, a patterned second metal layer and a through hole.
- a first dielectric layer and a second dielectric layer are formed at a first surface and a second surface of the substrate respectively, wherein the second surface is opposite to the first surface.
- the first dielectric layer and the second dielectric layer are patterned.
- a first trace layer is formed at a surface of the patterned first dielectric layer, wherein the first trace layer is embedded into the patterned first dielectric layer and is substantially coplanar with the first dielectric layer.
- a second trace layer is formed on a surface of the second dielectric layer.
- a substrate structure including a substrate, a first dielectric layer, a second dielectric layer, a first trace layer and a second dielectric layer is further provided.
- the substrate has a patterned first metal layer, a patterned second metal layer and a through hole.
- the through hole is electrically connected to the first metal layer and the second metal layer.
- the first dielectric layer is disposed at a first surface of the substrate.
- the second dielectric layer is disposed at a second surface of the substrate. The first surface is opposite to the second surface.
- the first trace layer is embedded into the first dielectric layer and is coplanar with the first dielectric layer.
- the second trace layer is disposed on a surface of the second dielectric layer.
- FIG. 1 shows a substrate structure according to a preferred embodiment of the present invention.
- FIG. 2 shows a flowchart of a first method for manufacturing the substrate structure in FIG. 1 .
- FIGS. 3A-3F show the steps of the first method in FIG. 2 for manufacturing the substrate structure.
- FIG. 4 shows a flowchart of a third method for manufacturing the substrate structure in FIG. 1 .
- FIGS. 5A-5G show the steps of the third method in FIG. 4 for manufacturing the substrate structure.
- the substrate structure 100 includes a substrate 110 , a first dielectric layer 121 , a second dielectric layer 122 , a first trace layer 131 and a second trace layer 132 .
- the substrate 110 has a patterned first metal layer 111 , a patterned second metal layer 112 and a through hole 113 .
- the through hole 113 is electrically connected to the first metal layer 111 and the second metal layer 112 .
- the first dielectric layer 121 is disposed at a first surface 110 s 1 of the substrate 110
- the second dielectric layer 122 is disposed at a second surface 110 s 2 of the substrate 110 .
- the first surface 110 s 1 is opposite to the second surface 110 s 2 .
- the first trace layer 131 is embedded into the first dielectric layer 121 and is coplanar with the first dielectric layer 121 .
- the second trace layer 132 is disposed on a surface 122 s of the second dielectric layer 122 .
- the first trace layer 131 has ultrafine lines for being electrically connected to a chip.
- the first trace layer 131 herein is electrically connected to the chip by flip chip technology with tin balls or Cu pillars.
- the trace pitch of the ultrafine lines ranges from 6 to 30 micrometers, and the thickness of the trace of the ultrafine lines ranges from 5 to 15 micrometers, for example.
- the second trace layer 132 with the thickness ranging from 12 to 20 micrometers is disposed at the surface of the second dielectric layer 122 , for example.
- the first dielectric layer 121 needs to have certain thickness dl so that the first trace layer 131 and the trace layer at the first surface 110 s 1 are separated by a certain interval to avoid short-circuiting.
- the thickness d 2 of the second dielectric layer 122 can be designed to be smaller than the thickness d 1 of the first dielectric layer 121 so as to reduce the overall thickness of the substrate structure 100 .
- the thickness dl of the first dielectric layer 121 can be designed to be larger than the thickness d 2 of the second dielectric layer 122 by about 10-20 micrometers.
- the substrate structure 100 may further include a first seed layer 141 and a second seed layer 142 used as conductive layers for electroplating.
- the first seed layer 141 is disposed between the first dielectric layer 121 and the first trace layer 131
- the second seed layer 142 is disposed between the second dielectric layer 122 and the second trace layer 132 .
- the first seed layer 141 and the second seed layer 142 can be made of electroless copper (E'less Cu), for example.
- the substrate structure 100 may further include a number of tin balls disposed on the second trace layer 132 for being electrically connected to the exterior.
- the substrate structure 100 of the present embodiment of the invention have the trace layers with different structures disposed at the first surface 110 s 1 and the second surface 110 s 2 of the substrate 110 . Therefore, the overall thickness of the substrate 110 is thinner.
- the substrate structure 100 can be manufactured by the following three manufacturing methods elaborated below.
- FIG. 1 a flowchart of a first method for manufacturing the substrate structure in FIG. 1 is shown, and the steps of the first method in FIG. 2 for manufacturing the substrate structure are shown in FIGS. 3A-3F .
- the first method for manufacturing the substrate structure 100 includes the following steps.
- the substrate 110 is provided.
- the substrate 110 has the patterned first metal layer 111 , the patterned second metal layer 112 and the through hole 113 , as indicated in FIG. 3A .
- the through hole 113 is electrically connected to the first metal layer 111 and the second metal layer 112 .
- the substrate 110 of the present embodiment has the first metal layer 111 , the second metal layer 112 and the through hole 113
- the substrate 110 can be a substrate (not illustrated) having more than two metal layers.
- the first dielectric layer 121 and the second dielectric layer 122 are formed at the first surface 110 s 1 and the second surface 110 s 2 of the substrate 110 as indicated in FIG. 3B , wherein the first surface 110 s 1 is opposite to the second surface 110 s 2 .
- the first dielectric layer 121 and the second dielectric layer 122 are, for example, formed by way of vacuum lamination in the step S 203 .
- the first dielectric layer 121 and the second dielectric layer 122 are patterned, as indicated in FIG. 3C .
- the first dielectric layer 121 is, for example, patterned by excimer laser so as to form patterns corresponding to the ultrafine lines of the first trace layer 131 , and is patterned by UV-YAG laser so as to form a pattern corresponding to a via 121 h of the first dielectric layer 121 .
- the patterned second dielectric layer 122 is, for example, patterned by UV-YAG laser so as to form a pattern corresponding to a via 122 h of the second dielectric layer 122 .
- the third metal layer 131 a is formed at the surface 121 s of the patterned first dielectric layer 121
- the fourth metal layer 132 a is formed on the surface 122 s of the patterned second dielectric layer 122 , as indicated in FIG. 3D .
- the thickness d 12 of the fourth metal layer 132 a formed on the surface 122 s of the second dielectric layer 122 is preferably larger than the thickness d 11 of the third metal layer 131 a formed on the surface 121 s of the first dielectric layer 121 .
- the thickness of the third metal layer 131 a is reduced, and the thickness of the fourth metal layer 132 a is reduced, so that the remained third metal layer 131 a is embedded into the patterned first dielectric layer 121 to from the first trace layer 131 , as indicated in FIG. 3E .
- the part of the third metal layer 131 a that is higher than the first dielectric layer 121 needs to be reduced, so that only the part of the third metal layer 131 a that is embedded into the first dielectric layer 121 is left.
- the part of the third metal layer 131 a that is reduced and the part of the fourth metal layer 132 a that is reduced are denoted by dotted lines.
- the thickness of the third metal layer 131 a and the thickness of the fourth metal layer 132 a are, for example, reduced by the same manufacturing process.
- the thickness of the third metal layer 131 a is, for example, reduced by way of etching or grinding
- the thickness of the fourth metal layer 132 a is, for example, reduced by way of etching or grinding.
- the thickness of the reduced third metal layer 131 a is substantially equal to the thickness of the reduced fourth metal layer 132 a.
- the fourth metal layer 132 a is patterned so as to form the second trace layer 132 on the surface 122 s of the second dielectric layer 122 , as indicated in FIG. 3F .
- the method of the present embodiment of the invention can further include forming a number of tin balls on the second trace layer 132 .
- the method for manufacturing the substrate structure 100 further includes forming the first seed layer 141 and the second seed layer 142 (as indicated in FIG. 1 ) on the surface 121 s of the patterned first dielectric layer 121 and the surface 122 s of the patterned second dielectric layer 122 in FIG. 3C , respectively.
- the method for manufacturing the substrate structure 100 further includes removing the part of the second seed layer 142 exposed from the second trace layer 132 on the surface 122 s of the second dielectric layer 122 so as to avoid short-circuiting.
- the removing step can be performed by way of etching or downstream pretreatment.
- the method for manufacturing the substrate structure 100 further includes the step of desmearing the surface 121 s of the patterned first dielectric layer 121 and desmearing the surface 122 s of the patterned second dielectric layer 122 .
- the desmearing step can be performed by way of etching. The desmearing step removes the smear located on the bottom of the through hole and coarsens the surfaces of the dielectric layers so as to facilitate subsequent processing.
- the method for manufacturing the substrate structure 100 uses the excimer laser only when the first dielectric layer 121 is patterned. Using the excimer laser is very costly. Compared with the method for manufacturing a substrate structure that the excimer laser is used twice for patterning two dielectric layers, the method for manufacturing the substrate structure 100 effectively reduces manufacturing cost. Besides, as only the part of the third metal layer 131 a that is higher than the first dielectric layer 121 needs to be completely reduced and the thickness of the second dielectric layer 122 can be thinner than the thickness of the first dielectric layer 121 , the cost for manufacturing the substrate structure 100 of the present embodiment of the invention can be further reduced.
- the second method for manufacturing the substrate structure 100 is disclosed below.
- the second manufacturing method differs from the first manufacturing method in that the second method for manufacturing the substrate structure 100 changes the thicknesses of the third metal layer and the fourth metal layer. More specifically, compared with the first method for manufacturing the substrate structure 100 , in the second method for manufacturing the substrate structure 100 , the thickness of the fourth metal layer is not smaller than the thickness of the third metal layer. However, the difference between the thicknesses of the third metal layer and the fourth metal layer formed in the second manufacturing method is smaller than the difference between the thicknesses of the third metal layer 131 a and the fourth metal layer 132 a according to the first manufacturing method in FIG. 2 . Moreover, the third metal layer undergoes a larger thickness reduction than the fourth metal layer.
- the thickness of the third metal layer is reduced by way of etching and grinding, but the thickness of the fourth metal layer is reduced by way of etching only.
- the substrate structure 100 in FIG. 1 is manufactured on the basis of the design of the thicknesses of the third metal layer and the fourth metal layer and the steps similar to those shown in FIG. 3A-FIG . 3 F.
- the second manufacturing method provides the same advantages as those of the first manufacturing method.
- the substrate structure 100 can also be manufactured according to the steps indicated in FIG. 4 and FIGS. 5A-5G in addition to the above two manufacturing methods. Referring to FIG. 4 and FIGS. 5A-5G , a flowchart of a third method for manufacturing the substrate structure in FIG. 1 is shown, and the steps of the third method in FIG. 4 for manufacturing the substrate structure are shown.
- the third method for manufacturing the substrate structure 100 includes the following steps.
- the steps S 201 ′to S 205 ′ in FIG. 4 are similar to the steps S 201 to S 205 in FIG. 2 .
- the substrate 110 is provided (as indicated in FIG. 5A ).
- the first dielectric layer 121 and the second dielectric layer 122 are formed (as indicated in FIG. 5B ).
- the first dielectric layer 121 and the second dielectric layer 122 are patterned (as indicated in FIG. 5C ).
- the photoresist layer 150 is formed on the surface 122 s of the patterned second dielectric layer 122 . Specifically, the photoresist layer 150 is formed on a seed layer (not shown) previously formed on the the surface 122 s of the patterned second dielectric layer 122 .
- the photoresist layer 150 is patterned, as indicated in FIG. 5D .
- the third metal layer 131 a ′ is formed at the surface 121 s of the patterned first dielectric layer 121 , and the fourth metal layer 132 a ′ is formed on the surface 122 s of the patterned second dielectric layer 122 (specifically, the seed layer 142 (not shown)) which is not covered by the patterned photoresist layer 150 as indicated in FIG. 5E .
- the thickness d 22 of the formed fourth metal layer 132 a ′ can be substantially equal to the thickness d 21 of the formed third metal layer 131 a′.
- the thickness of the third metal layer 131 a ′ is reduced, so that the remained third metal layer 131 a ′ is embedded into the patterned first dielectric layer 121 to form the first trace layer 131 as indicated in FIG. 5F .
- the part of the reduced third metal layer 131 a ′ is denoted by dotted lines.
- the thickness of the third metal layer 131 a ′ is, for example, reduced by way of etching and grinding.
- the patterned photoresist layer 150 is removed so as to form the second trace layer 132 as indicated in FIG. 5G .
- the method of the present embodiment of the invention can further include forming a number of tin balls on the second trace layer 132 .
- the third manufacturing method can provides the same advantages as those of the first manufacturing method.
- the first trace layer is embedded into the first dielectric layer
- the second trace layer is disposed on the second dielectric layer.
- the trace layer disposed at the bottom surface of the substrate is normally used as a grounding layer or a direct current bias layer and can achieve the desired function without ultrafine lines.
- ordinary trace layer (such as the second trace layer 132 ) can be used as the grounding layer or the direct current bias layer. Therefore, on the premise that the product requirements are satisfied, the embodiments of the present invention have the advantages of low cost and strong competitiveness in the market.
Abstract
A method for manufacturing a substrate structure is provided. The method includes the following steps. A substrate is provided. The substrate has a patterned first metal layer, a pattern second metal layer and a through hole. After that, a first dielectric layer and a second dielectric layer are formed at a first surface and a second surface of the substrate, respectively. The second surface is opposite to the first surface. Then, the first dielectric layer and the second dielectric layer are patterned. After that, a first trace layer is formed at a surface of the patterned first dielectric layer. The first trace layer is embedded into the patterned first dielectric layer and is coplanar with the first dielectric layer. Then, a second trace layer is formed on a surface of the second dielectric layer.
Description
- This application is a divisional application of co-pending U.S. application Ser. No. 12/720,238, filed Mar. 9, 2010, which claims the benefit of Taiwan application Serial No. 098129881, filed Sep. 4, 2009. These related applications are incorporated herein by reference.
- 1. Field of the Invention
- The invention relates in general to a substrate structure and a method for manufacturing the same, and more particularly to a substrate structure with a substrate whose two surfaces has different structures and a method for manufacturing the same.
- 2. Description of the Related Art
- In response to the current trend in slimness, lightweight and compactness of electronic products, the design of the circuit board is gradually directed towards ultrafine lines.
- Currently, the circuit board whose top surface and bottom surface both have a trace layer with ultrafine lines is provided. However, two ultrafine line processes have to be performed so as to obtain such a circuit board, so that the cost is extremely high. Thus, how to reduce the cost for manufacturing the circuit board having the trace layers with the ultrafine lines has become one of the imminent issues to the manufacturers.
- The invention is directed to a substrate structure and a method for manufacturing the same. The invention has the advantages of thin thickness and low manufacturing cost.
- According to the present invention, a method for manufacturing a substrate structure is provided. The method includes the following steps. A substrate is provided, wherein the substrate has a patterned first metal layer, a patterned second metal layer and a through hole. Next, a first dielectric layer and a second dielectric layer are formed at a first surface and a second surface of the substrate respectively, wherein the second surface is opposite to the first surface. Then, the first dielectric layer and the second dielectric layer are patterned. After that, a first trace layer is formed at a surface of the patterned first dielectric layer, wherein the first trace layer is embedded into the patterned first dielectric layer and is substantially coplanar with the first dielectric layer. Then, a second trace layer is formed on a surface of the second dielectric layer.
- According to the present invention, a substrate structure including a substrate, a first dielectric layer, a second dielectric layer, a first trace layer and a second dielectric layer is further provided. The substrate has a patterned first metal layer, a patterned second metal layer and a through hole. The through hole is electrically connected to the first metal layer and the second metal layer. The first dielectric layer is disposed at a first surface of the substrate. The second dielectric layer is disposed at a second surface of the substrate. The first surface is opposite to the second surface. The first trace layer is embedded into the first dielectric layer and is coplanar with the first dielectric layer. The second trace layer is disposed on a surface of the second dielectric layer.
- The invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
-
FIG. 1 shows a substrate structure according to a preferred embodiment of the present invention. -
FIG. 2 shows a flowchart of a first method for manufacturing the substrate structure inFIG. 1 . -
FIGS. 3A-3F show the steps of the first method inFIG. 2 for manufacturing the substrate structure. -
FIG. 4 shows a flowchart of a third method for manufacturing the substrate structure inFIG. 1 . -
FIGS. 5A-5G show the steps of the third method inFIG. 4 for manufacturing the substrate structure. - Referring to
FIG. 1 , a substrate structure according to a preferred embodiment of the present invention is shown. Thesubstrate structure 100 includes asubstrate 110, a firstdielectric layer 121, a seconddielectric layer 122, afirst trace layer 131 and asecond trace layer 132. - The
substrate 110 has a patternedfirst metal layer 111, a patternedsecond metal layer 112 and a throughhole 113. The throughhole 113 is electrically connected to thefirst metal layer 111 and thesecond metal layer 112. The firstdielectric layer 121 is disposed at a first surface 110 s 1 of thesubstrate 110, and the seconddielectric layer 122 is disposed at a second surface 110 s 2 of thesubstrate 110. The first surface 110 s 1 is opposite to the second surface 110 s 2. Thefirst trace layer 131 is embedded into the firstdielectric layer 121 and is coplanar with the firstdielectric layer 121. Thesecond trace layer 132 is disposed on asurface 122 s of the seconddielectric layer 122. - The
substrate structure 100 of the present embodiment of the invention is further elaborated below. In the present embodiment of the invention, thefirst trace layer 131 has ultrafine lines for being electrically connected to a chip. Thefirst trace layer 131 herein is electrically connected to the chip by flip chip technology with tin balls or Cu pillars. The trace pitch of the ultrafine lines ranges from 6 to 30 micrometers, and the thickness of the trace of the ultrafine lines ranges from 5 to 15 micrometers, for example. Besides, thesecond trace layer 132 with the thickness ranging from 12 to 20 micrometers is disposed at the surface of the seconddielectric layer 122, for example. As thefirst trace layer 131 is embedded into the firstdielectric layer 121, the firstdielectric layer 121 needs to have certain thickness dl so that thefirst trace layer 131 and the trace layer at the first surface 110 s 1 are separated by a certain interval to avoid short-circuiting. As thesecond trace layer 132 is not embedded into the seconddielectric layer 122, the thickness d2 of the seconddielectric layer 122 can be designed to be smaller than the thickness d1 of the firstdielectric layer 121 so as to reduce the overall thickness of thesubstrate structure 100. The thickness dl of the firstdielectric layer 121 can be designed to be larger than the thickness d2 of the seconddielectric layer 122 by about 10-20 micrometers. - In the present embodiment of the invention, let the
first trace layer 131 and thesecond trace layer 132 be formed by way of electroplating as an example. Thesubstrate structure 100 may further include afirst seed layer 141 and asecond seed layer 142 used as conductive layers for electroplating. Thefirst seed layer 141 is disposed between the firstdielectric layer 121 and thefirst trace layer 131, and thesecond seed layer 142 is disposed between the seconddielectric layer 122 and thesecond trace layer 132. Thefirst seed layer 141 and thesecond seed layer 142 can be made of electroless copper (E'less Cu), for example. Moreover, thesubstrate structure 100 may further include a number of tin balls disposed on thesecond trace layer 132 for being electrically connected to the exterior. - Under the presupposition of providing the same functions, compared with the substrate structure whose top surface and bottom surface both have a trace layer with ultrafine lines embedded into the dielectric layer, the
substrate structure 100 of the present embodiment of the invention have the trace layers with different structures disposed at the first surface 110 s 1 and the second surface 110 s 2 of thesubstrate 110. Therefore, the overall thickness of thesubstrate 110 is thinner. - In the present embodiment of the invention, the
substrate structure 100 can be manufactured by the following three manufacturing methods elaborated below. - Referring t both
FIG. 2 andFIGS. 3A-3F , a flowchart of a first method for manufacturing the substrate structure inFIG. 1 is shown, and the steps of the first method inFIG. 2 for manufacturing the substrate structure are shown inFIGS. 3A-3F . The first method for manufacturing thesubstrate structure 100 includes the following steps. - In the step S201, the
substrate 110 is provided. Thesubstrate 110 has the patternedfirst metal layer 111, the patternedsecond metal layer 112 and the throughhole 113, as indicated inFIG. 3A . In the present embodiment of the invention, the throughhole 113 is electrically connected to thefirst metal layer 111 and thesecond metal layer 112. Although thesubstrate 110 of the present embodiment has thefirst metal layer 111, thesecond metal layer 112 and the throughhole 113, thesubstrate 110 can be a substrate (not illustrated) having more than two metal layers. - Then, in the step S203, the
first dielectric layer 121 and thesecond dielectric layer 122 are formed at the first surface 110 s 1 and the second surface 110 s 2 of thesubstrate 110 as indicated inFIG. 3B , wherein the first surface 110 s 1 is opposite to the second surface 110 s 2. Thefirst dielectric layer 121 and thesecond dielectric layer 122 are, for example, formed by way of vacuum lamination in the step S203. - After that, in the step S205, the
first dielectric layer 121 and thesecond dielectric layer 122 are patterned, as indicated inFIG. 3C . Thefirst dielectric layer 121 is, for example, patterned by excimer laser so as to form patterns corresponding to the ultrafine lines of thefirst trace layer 131, and is patterned by UV-YAG laser so as to form a pattern corresponding to a via 121 h of thefirst dielectric layer 121. Besides, the patterned seconddielectric layer 122 is, for example, patterned by UV-YAG laser so as to form a pattern corresponding to a via 122 h of thesecond dielectric layer 122. - Next, in the step S207, the
third metal layer 131 a is formed at thesurface 121 s of the patterned firstdielectric layer 121, and thefourth metal layer 132 a is formed on thesurface 122 s of the patterned seconddielectric layer 122, as indicated inFIG. 3D . In the present embodiment of the invention, the thickness d12 of thefourth metal layer 132 a formed on thesurface 122 s of thesecond dielectric layer 122 is preferably larger than the thickness d11 of thethird metal layer 131 a formed on thesurface 121 s of thefirst dielectric layer 121. - Then, in the step S209, the thickness of the
third metal layer 131 a is reduced, and the thickness of thefourth metal layer 132 a is reduced, so that the remainedthird metal layer 131 a is embedded into the patterned firstdielectric layer 121 to from thefirst trace layer 131, as indicated inFIG. 3E . In the present embodiment, the part of thethird metal layer 131 a that is higher than thefirst dielectric layer 121 needs to be reduced, so that only the part of thethird metal layer 131 a that is embedded into thefirst dielectric layer 121 is left. As indicated inFIG. 3E , the part of thethird metal layer 131 a that is reduced and the part of thefourth metal layer 132 a that is reduced are denoted by dotted lines. The thickness of thethird metal layer 131 a and the thickness of thefourth metal layer 132 a are, for example, reduced by the same manufacturing process. In the step S209, the thickness of thethird metal layer 131 a is, for example, reduced by way of etching or grinding, and the thickness of thefourth metal layer 132 a is, for example, reduced by way of etching or grinding. In the present embodiment of the invention, the thickness of the reducedthird metal layer 131 a is substantially equal to the thickness of the reducedfourth metal layer 132 a. - After that, in the step S211, the
fourth metal layer 132 a is patterned so as to form thesecond trace layer 132 on thesurface 122 s of thesecond dielectric layer 122, as indicated inFIG. 3F . - In order to provide the electrical connection to the exterior, the method of the present embodiment of the invention can further include forming a number of tin balls on the
second trace layer 132. - Let the
third metal layer 131 a and thefourth metal layer 132 a are formed by way of electroplating so as to be a part of thefirst trace layer 131 and thesecond trace layer 132 respectively in the method of the present embodiment of the invention as an example. In order to provide conductive layers for electroplating, before the step S207, the method for manufacturing thesubstrate structure 100 further includes forming thefirst seed layer 141 and the second seed layer 142 (as indicated inFIG. 1 ) on thesurface 121 s of the patterned firstdielectric layer 121 and thesurface 122 s of the patterned seconddielectric layer 122 inFIG. 3C , respectively. Preferably, after the step S211, the method for manufacturing thesubstrate structure 100 further includes removing the part of thesecond seed layer 142 exposed from thesecond trace layer 132 on thesurface 122 s of thesecond dielectric layer 122 so as to avoid short-circuiting. The removing step can be performed by way of etching or downstream pretreatment. - Besides, in order to effectively remove the smear remained on the
surface 121 s of thefirst dielectric layer 121 and thesurface 122 s of thesecond dielectric layer 122, before the step of forming thefirst seed layer 141 and thesecond seed layer 142, the method for manufacturing thesubstrate structure 100 further includes the step of desmearing thesurface 121 s of the patterned firstdielectric layer 121 and desmearing thesurface 122 s of the patterned seconddielectric layer 122. The desmearing step can be performed by way of etching. The desmearing step removes the smear located on the bottom of the through hole and coarsens the surfaces of the dielectric layers so as to facilitate subsequent processing. - The method for manufacturing the
substrate structure 100 uses the excimer laser only when thefirst dielectric layer 121 is patterned. Using the excimer laser is very costly. Compared with the method for manufacturing a substrate structure that the excimer laser is used twice for patterning two dielectric layers, the method for manufacturing thesubstrate structure 100 effectively reduces manufacturing cost. Besides, as only the part of thethird metal layer 131 a that is higher than thefirst dielectric layer 121 needs to be completely reduced and the thickness of thesecond dielectric layer 122 can be thinner than the thickness of thefirst dielectric layer 121, the cost for manufacturing thesubstrate structure 100 of the present embodiment of the invention can be further reduced. - The second method for manufacturing the
substrate structure 100 is disclosed below. The second manufacturing method differs from the first manufacturing method in that the second method for manufacturing thesubstrate structure 100 changes the thicknesses of the third metal layer and the fourth metal layer. More specifically, compared with the first method for manufacturing thesubstrate structure 100, in the second method for manufacturing thesubstrate structure 100, the thickness of the fourth metal layer is not smaller than the thickness of the third metal layer. However, the difference between the thicknesses of the third metal layer and the fourth metal layer formed in the second manufacturing method is smaller than the difference between the thicknesses of thethird metal layer 131 a and thefourth metal layer 132 a according to the first manufacturing method inFIG. 2 . Moreover, the third metal layer undergoes a larger thickness reduction than the fourth metal layer. - For example, in the second manufacturing method, the thickness of the third metal layer is reduced by way of etching and grinding, but the thickness of the fourth metal layer is reduced by way of etching only. Thus, the
substrate structure 100 inFIG. 1 is manufactured on the basis of the design of the thicknesses of the third metal layer and the fourth metal layer and the steps similar to those shown inFIG. 3A-FIG . 3F. The second manufacturing method provides the same advantages as those of the first manufacturing method. - The
substrate structure 100 can also be manufactured according to the steps indicated inFIG. 4 andFIGS. 5A-5G in addition to the above two manufacturing methods. Referring toFIG. 4 andFIGS. 5A-5G , a flowchart of a third method for manufacturing the substrate structure inFIG. 1 is shown, and the steps of the third method inFIG. 4 for manufacturing the substrate structure are shown. The third method for manufacturing thesubstrate structure 100 includes the following steps. - Compare to the steps in
FIG. 2 , the steps S201′to S205′ inFIG. 4 are similar to the steps S201 to S205 inFIG. 2 . In the step S201′, thesubstrate 110 is provided (as indicated inFIG. 5A ). In the step 203′, thefirst dielectric layer 121 and thesecond dielectric layer 122 are formed (as indicated inFIG. 5B ). In the step S205′, thefirst dielectric layer 121 and thesecond dielectric layer 122 are patterned (as indicated inFIG. 5C ). - Next, in the step S206 a′, the
photoresist layer 150 is formed on thesurface 122 s of the patterned seconddielectric layer 122. Specifically, thephotoresist layer 150 is formed on a seed layer (not shown) previously formed on the thesurface 122 s of the patterned seconddielectric layer 122. - Then, in the step S206 b′, the
photoresist layer 150 is patterned, as indicated inFIG. 5D . - After that, in the step S207′, the
third metal layer 131 a′ is formed at thesurface 121 s of the patterned firstdielectric layer 121, and thefourth metal layer 132 a′ is formed on thesurface 122 s of the patterned second dielectric layer 122 (specifically, the seed layer 142 (not shown)) which is not covered by the patternedphotoresist layer 150 as indicated inFIG. 5E . In the present embodiment of the invention, the thickness d22 of the formedfourth metal layer 132 a′can be substantially equal to the thickness d21 of the formedthird metal layer 131 a′. - Then, in the step S209′, the thickness of the
third metal layer 131 a′ is reduced, so that the remainedthird metal layer 131 a′ is embedded into the patterned firstdielectric layer 121 to form thefirst trace layer 131 as indicated inFIG. 5F . The part of the reducedthird metal layer 131 a′ is denoted by dotted lines. In the step S207′, the thickness of thethird metal layer 131 a′ is, for example, reduced by way of etching and grinding. - After that, in the step S211′, the patterned
photoresist layer 150 is removed so as to form thesecond trace layer 132 as indicated inFIG. 5G . - In order to provide the electrical connection to the exterior, the method of the present embodiment of the invention can further include forming a number of tin balls on the
second trace layer 132. - Other steps such as the step of desmearing the
first dielectric layer 121 and thesecond dielectric layer 122 and the step of forming thefirst seed layer 141 and thesecond seed layer 142 can be performed according to the requirements during the manufacturing process, and are not repeatedly described herein. The third manufacturing method can provides the same advantages as those of the first manufacturing method. - According to the substrate structure and the method for manufacturing the same disclosed in the above embodiments of the invention, the first trace layer is embedded into the first dielectric layer, and the second trace layer is disposed on the second dielectric layer. Compared with the substrate structure whose top surface and bottom surface both have a trace layer with the ultrafine lines embedded into the dielectric layer, the overall thickness of the substrate structure of the embodiments of the invention is thinner, and the manufacturing cost is lower. Besides, the trace layer disposed at the bottom surface of the substrate is normally used as a grounding layer or a direct current bias layer and can achieve the desired function without ultrafine lines. In the embodiments of the present invention, ordinary trace layer (such as the second trace layer 132) can be used as the grounding layer or the direct current bias layer. Therefore, on the premise that the product requirements are satisfied, the embodiments of the present invention have the advantages of low cost and strong competitiveness in the market.
- While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
Claims (6)
1. A substrate structure, comprising:
a substrate having a patterned first metal layer, a patterned second metal layer and a through hole, wherein the through hole is electrically connected to the first metal layer and the second metal layer;
a first dielectric layer disposed at a first surface of the substrate;
a second dielectric layer disposed at a second surface of the substrate, wherein the first surface is opposite to the second surface;
a first trace layer embedded into the first dielectric layer and substantially coplanar with the first dielectric layer; and
a second trace layer disposed on a surface of the second dielectric layer.
2. The substrate structure according to claim 1 , wherein, the second trace layer with the thickness ranging from 12 to 20 micrometers is disposed at the surface of the second dielectric layer.
3. The substrate structure according to claim 1 , wherein the thickness of the first dielectric layer is larger than the thickness of the second dielectric layer.
4. The substrate structure according to claim 1 , wherein, the thickness of the first dielectric layer is larger than the thickness of the second dielectric layer by 10-20 micrometers.
5. The substrate structure according to claim 1 , wherein, the first trace layer has ultrafine lines whose trace pitch ranges from 6 to 30 micrometers.
6. The substrate structure according to claim 1 , wherein, the first trace layer has ultrafine lines, and the thickness of the trace of the ultrafine lines ranges from 5 to 15 micrometers.
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US15/177,295 US10631406B2 (en) | 2009-09-04 | 2016-06-08 | Substrate structure and method for manufacturing the same |
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US13/673,868 US20130068517A1 (en) | 2009-09-04 | 2012-11-09 | Substrate structure and method for manufacturing the same |
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US15/177,295 Active 2032-02-07 US10631406B2 (en) | 2009-09-04 | 2016-06-08 | Substrate structure and method for manufacturing the same |
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KR101532388B1 (en) * | 2012-10-12 | 2015-07-01 | 주식회사 잉크테크 | Method for manufacturing precision PCB forming circuit pattern and connecting the circuit pattern through via-hole |
US9609751B2 (en) * | 2014-04-11 | 2017-03-28 | Qualcomm Incorporated | Package substrate comprising surface interconnect and cavity comprising electroless fill |
EP3373714B1 (en) * | 2017-03-08 | 2023-08-23 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Hybrid component carrier and method for manufacturing the same |
US11798871B2 (en) | 2020-08-21 | 2023-10-24 | Nxp Usa, Inc. | Device package substrate structure and method therefor |
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Also Published As
Publication number | Publication date |
---|---|
US10631406B2 (en) | 2020-04-21 |
US20160286645A1 (en) | 2016-09-29 |
TW201110839A (en) | 2011-03-16 |
US8322032B2 (en) | 2012-12-04 |
US20110056739A1 (en) | 2011-03-10 |
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