CN102169868A - On-chip integrated inductor - Google Patents
On-chip integrated inductor Download PDFInfo
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- CN102169868A CN102169868A CN 201110042201 CN201110042201A CN102169868A CN 102169868 A CN102169868 A CN 102169868A CN 201110042201 CN201110042201 CN 201110042201 CN 201110042201 A CN201110042201 A CN 201110042201A CN 102169868 A CN102169868 A CN 102169868A
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Abstract
The invention provides an on-chip integrated inductor, comprising inductive coil, metal layer, isolation layer; A metal layer is provide between two adjacent inductive coils; An isolation layer is arranged between the inductive coil and the metal layer; Looking the adjacent two inductive coils in a down direction, The two coils are offset to each other and not superposed; The inductive coil and the metal layer are connected through perforations. The invention provided on-chip inductors reduces parasitic capacitance between perforation wires, Which improving quality factors, And expanding frequency bandwidth of inductance, Without increasing the chip area.
Description
Technical field
The invention belongs to microelectronics technology, relate in particular to a kind of and go up integrated inductor.
Background technology
At present, the integrated circuit direction that trends towards high frequency, low-power consumption develops.Integrated inductor is widely used in the circuit such as voltage controlled oscillator, low noise amplifier, frequency mixer on the sheet.The performance of integrated inductor plays key effect to circuit on the sheet.The performance parameter of integrated inductor mainly contains quality factor and frequency bandwidth, and the quality factor of inductance and the size of frequency bandwidth play a crucial factor to the raising of circuit performance.
Substrate loss, wire coil dead resistance, coil parasitic capacitance all can reduce the quality factor and the frequency bandwidth of integrated inductor.The reason of substrate loss is that substrate resistance is lower, and substrate and inductor layer are on-insulated, and when having electric current to flow through in the inductance coil, electric current can produce magnetic field, thereby produces reciprocal induced current, causes energy loss.Because wire coil resistance is non-vanishing, can produce ohmic loss and eddy current loss simultaneously when high-frequency current flows through coil.Can form the parasitic capacitance of similar capacity plate antenna between wire coil, influence inductance performance.
In the prior art, integrated inductor is made up of substrate, each layer metal and metal interlevel separator medium on the sheet, is divided into individual layer and multilayer overlaying structure usually.The shortcoming of individual layer inductance is that shared chip area is bigger, and inductance coil utilizes metal level to form the snail structure around mode.The multilayer overlaying structure, its lower floor's inductance coil is positioned under the inductance coil of upper strata, and different layers inductance coil spacing is less.Parasitic capacitance between coil and metal interlevel are apart from being inversely proportional to, and spacing is more little, and parasitic capacitance is big more, and the increase of parasitic capacitance between coil has reduced the quality factor and the frequency bandwidth of integrated inductor.In the tradition laminated inductance structure, lower floor's inductance coil be positioned at upper coil under, can produce bigger parasitic capacitance, thereby reduce induction quality factor Q and frequency bandwidth.
The present invention is intended to overcome the above-mentioned defective of integrated inductor on the sheet, and integrated inductor on a kind of sheet of new construction is provided, and reduces the parasitic capacitance of inductance coil, thereby improves the quality factor and the bandwidth of integrated inductor on the sheet.
Summary of the invention
The objective of the invention is to propose a kind of and go up integrated inductor, adopt interlayer, the adjacent layer structure that do not overlap, reduce the parasitic capacitance of inductance coil, thereby improve the quality factor and the bandwidth of integrated inductor on the sheet.
The invention provides a kind of and go up integrated inductor, comprise inductance coil, metal level, separator.Be provided with one deck metal level at least between the adjacent two layers inductance coil; Be provided with separator between inductance coil and the metal level; The adjacent two layers inductance coil looks up from the side of overlooking, and skew does not overlap mutually.Connect by perforation between inductance coil, the metal level.
Wherein, be provided with two-layer above metal level between the adjacent two layers inductance coil, between adjacent metal, be provided with separator.
Wherein, the area of metal level is less than the area of inductance coil.Offset distance between the adjacent two layers inductance coil is greater than the width of inductance coil.
Among the present invention, be 1 ~ 2 circle with the coil number of the inductance coil of one deck.Inductance coil comprises inner ring and outer ring, and inner ring (I) is identical with the direction of current flow of outer ring.
The present invention adopts not overlay structure of interlayer, adjacent layer, and is simultaneously bigger than normal in order to remedy the inductance area that interlayer causes, and can be multi-turn with a layer inductance.
Integrated inductor on the sheet of the present invention does not have the existence of parasitic capacitance between it is two-layer up and down, and widen owing to spacing between the adjacent two-layer inductance coil, so parasitic capacitance is reduced.Lower floor's inductance coil is not under the inductance coil of upper strata, and adjacent two layers inductance coil distance is at least greater than the inductance coil width, and therefore overlap capacitance and side direction electric capacity are less between neighbouring double layer of metal coil.Non-conterminous up and down inductance coil can be overlapping, because its spacing of being separated by is bigger, its parasitic capacitance value descends more, also can not cause too big inductance performance loss even therefore overlap.
Integrated inductor has reduced the parasitic capacitance between inductance leads on the sheet of the present invention, under the prerequisite that does not increase chip area, has improved the quality factor of inductance, has expanded the frequency bandwidth of inductance.
Description of drawings
Fig. 1 has the standard integrated circuit interconnection line schematic diagram of eight layers of structure for the present invention;
Fig. 2 is the structure chart that utilizes integrated inductor on the sheet that eight layers of metal connecting line realize;
The neighbouring two-layer inductance coil vertical view of Fig. 3 embodiment of the invention;
The profile of integrated inductor on the sheet of Fig. 4 embodiment of the invention;
The vertical view of integrated inductor on the sheet of Fig. 5 embodiment of the invention;
The profile of integrated inductor on the sheet of Fig. 6 another embodiment of the present invention;
The vertical view of integrated inductor on the sheet of Fig. 7 another embodiment of the present invention.
Embodiment
Further elaborate the present invention below in conjunction with drawings and Examples.Following examples are not limitation of the present invention.Under the spirit and scope that do not deviate from inventive concept, variation and advantage that those skilled in the art can expect all are included among the present invention.
Embodiment 1:
As shown in Figure 1, integrated inductor on the sheet of present embodiment is respectively one to eight layer of structure from the bottom to top.Its metal level 1,3,5,7 is separately positioned on first and third, five, seven layer, and inductance coil 2,4,6,8 is separately positioned on second, four, six, eight layer, adjacent is equipped with separator 9 between two-layer, realizes the electrical isolation between two-layer up and down.
Fig. 2 is the structure chart that utilizes integrated inductor on the sheet that standard integrated circuit interconnection line schematic diagram shown in Figure 1 realizes.Among Fig. 2, be provided with layer of metal layer 3,5,7 and separator 12,13,14 between the adjacent two layers inductance coil 2,4,6,8.Be connected by perforation a, b, c, d, e, f between inductance coil 2,4,6,8 and the metal level 3,5,7.
Wherein, the area of metal level 3,5,7 is less than the area of inductance coil 2,4,6,8. Metal level 3,5,7 plays the effect of being electrically connected, and its area is less, and and adjacent electrical potential difference between two-layer up and down can ignore, therefore and do not have the existence of parasitic capacitance between the two-layer up and down inductance coil 2,4,6,8.And widen owing to spacing between the adjacent nearest two- layer inductance coil 2,4,6,8, so parasitic capacitance is reduced.
Every layer of inductance coil 2,4,6,8 comprises two circle wire coils in the present embodiment.Wherein, the coil number with the inductance coil of one deck can be 1 ~ 2 circle.
Fig. 3 is the vertical view of neighbouring two- layer inductance coil 6,8, and inductance coil 6,8 does not overlap, do not have parallel overlapping from vertical direction, square crossing is only arranged, and inductance coil 6 is not under inductance coil 8.Non-conterminous up and down inductance coil can be overlapping, can be overlapping as inductance coil 8 and inductance coil 4.Be divided into inner ring (I) and outer ring (O) with one deck inductance coil, inner ring (I) is identical with outer ring (O) direction of current flow.Mutual inductance effect is: have electric current to flow through in two sections conductors, when two sections conductors are close, mutual inductance effect can take place.Go up integrated inductor for of the present invention and utilize mutual inductance effect, can improve the inductance value of unit are inductance.Go up integrated inductor than existing, the inductance value of integrated inductor unit are is bigger on the sheet of the present invention, can realize bigger inductance value with short coil.The resistance of metallic conductor is directly proportional with length, is inversely proportional to cross-sectional area, and shortening inductance coil length can reduce the resistance value in the inductance, thereby reduces the ohmic loss of inductance, improves the quality factor of inductance, improves the performance of inductance.
In the present embodiment, the offset distance u between the adjacent two layers inductance coil 6,8 is 2 microns, and the width w of inductance coil is 8 microns.
Wherein, the offset distance between the adjacent two layers inductance coil 6,8 can be 1 ~ 10 micron, and the width w of inductance coil can be 5 ~ 15 microns.
Fig. 4 is the profile of integrated inductor on the present embodiment sheet, as seen from Figure 4, inductance coil 8 links to each other with metal level 7 by perforation f, metal level 7 links to each other with inductance coil 6 by perforation e, inductance coil 6 links to each other with metal level 5 by perforation d, metal level 5 links to each other with inductance coil 4 by perforation c, and inductance coil 4 links to each other with metal level 3 by perforation b, and metal level 3 links to each other with inductance coil 2 by perforation a.16 to 28 is separator.15 is substrate.
Wherein, metal level 7 plays the effect that connects inductance coil 8 and inductance coil 6, and metal level 5 plays the effect that connects inductance coil 6 and inductance coil 4, and metal level 3 plays the effect that connects inductance coil 4 and inductance coil 2.
Fig. 5 is the vertical view of integrated inductor on the present embodiment sheet.Inductance coil 8 links to each other with inductance coil 6 by tie point 33, and tie point 33 connects inductance coil 8, perforation f, metal level 7, perforation e and inductance coil 6; Inductance coil 6 links to each other with inductance coil 4 by tie point 32, and tie point 32 connects inductance coil 6, perforation d, metal level 5, perforation c and inductance coil 4; Inductance coil 4 links to each other with inductance coil 2 by tie point 31, and tie point 31 connects inductance coil 4, perforation b, metal level 3, perforation a and inductance coil 2; Inductance coil 2 is connected to metal level 3 by tie point 30, and tie point 30 connects inductance coil 14, perforation a, metal level 12.Coil is outer to be connected to inductance coil 8 by tie point 29 to metal level 3 by being drawn out in the coil, and tie point 29 connects metal level 3, perforation b, inductance coil 4, perforation c, metal level 5, perforation d, inductance coil 6, perforation e, metal level 7 and inductance coil 8.
Embodiment 2:
Fig. 6 is the profile of integrated inductor on the present embodiment sheet.In the present embodiment, be provided with two metal layers between adjacent two-layer inductance coil, inductance coil 102,105,108 is positioned at the second layer, layer 5 and the 8th layer.Inductance coil 108 links to each other with metal level 107 by perforation f, metal level 107 links to each other with metal level 106 by perforation e, metal level 106 links to each other with inductance coil 105 by perforation d, inductance coil 105 links to each other with metal level 104 by perforation c, metal level 104 links to each other with metal level 103 by perforation b, and metal level 103 links to each other with inductance coil 102 by perforation a.16 to 28 is separator, and 15 is substrate.
Fig. 7 is the vertical view of integrated inductor on this example sheet, and inductance coil 108 links to each other with inductance coil 105 by tie point 35, and tie point 35 connects inductance coil 108, perforation f, metal level 107, perforation e, metal level 106, perforation d and inductance coil 105; Inductance coil 105 links to each other with inductance coil 102 by tie point 34, and tie point 34 connects inductance coil 105, perforation c, metal level 104, perforation b, metal level 103, perforation a and inductance coil 102.
Integrated inductor is realized inductance in the structure perpendicular to chip direction design different layers on the sheet of the present invention.Metal interconnection line as integrated technique has eight layers, and then inductance coil can be positioned at the 8th, six, four, two layer, or on the 8th, five, two layer, and the like, as long as satisfy between the neighbouring two-layer inductance coil layer of metal layer is set at least.On the sheet of the present invention the structure of integrated inductor aspect the number of plies without limits.
Integrated inductor is a stereochemical structure on the sheet of the present invention, supports three layers at least, and inductance coil is implemented in ground floor and the 3rd layer, and the metal level of the second layer of being separated by between upper strata inductance coil and the lower floor's inductance coil is provided with separator at inductance coil and metal level.
Integrated inductor on the sheet of the present invention adopts sandwich construction, and distance reduces parasitic capacitance between the different layers inductance coil by increasing, and improves induction quality factor and frequency bandwidth.Two-layer up and down adjacent inductance coil does not have parallel overlapping at vertical view, square crossing is only arranged.Because lower floor's inductance coil is under the inductance coil of upper strata, and the adjacent two layers inductance coil apart from u at least greater than inductance coil width w, therefore overlap capacitance and side direction electric capacity are less between neighbouring double layer of metal coil.Non-conterminous up and down inductance coil can be overlapping, because its spacing of being separated by is bigger, its parasitic capacitance value descends more, also can not cause too big inductance performance loss even therefore overlap.
Integrated inductor also can adopt polygon inductance coils such as octagon, ten hexagons on the sheet of the present invention, adopts the polygon inductance coil can improve inductance performance to a certain extent.Adopt that integrated inductor can reduce to make the used silicon area of inductance on the sheet of the present invention, under area identical, adopt the multilayer inductor structure can improve the inductance value of inductance, under the equal area, can obtain the frequency bandwidth and the induction quality factor Q value of bigger inductance value and broad.
Being preferred embodiment of the present invention only in sum, is not to be used for limiting practical range of the present invention.Be that all equivalences of doing according to the content of the present patent application claim change and modification, all should belong to technology category of the present invention.
Claims (6)
1. integrated inductor on the sheet is characterized in that, comprises inductance coil, metal level, separator; Be provided with one deck metal level at least between the adjacent two layers inductance coil; Be provided with separator between described inductance coil and the metal level; The adjacent two layers inductance coil looks up from the side of overlooking, and skew does not overlap mutually; Connect by perforation between described inductance coil, the metal level.
2. go up integrated inductor for as claimed in claim 1, it is characterized in that, be provided with two-layer above described metal level between the described adjacent two layers inductance coil, between adjacent metal, be provided with described separator.
3. go up integrated inductor, it is characterized in that the area of described metal level is less than the area of inductance coil for as claimed in claim 1.
4. go up integrated inductor, it is characterized in that the offset distance (u) between the described adjacent two layers inductance coil is greater than the width (w) of inductance coil for as claimed in claim 1.
5. going up integrated inductor for as claimed in claim 1, it is characterized in that, is 1 ~ 2 circle with the coil number of the inductance coil of one deck.
6. go up integrated inductor for as claimed in claim 1, it is characterized in that, described inductance coil comprises inner ring (I) and outer ring (O), and described inner ring (I) is identical with the direction of current flow of outer ring (O).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100422014A CN102169868B (en) | 2011-02-22 | 2011-02-22 | On-chip integrated inductor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100422014A CN102169868B (en) | 2011-02-22 | 2011-02-22 | On-chip integrated inductor |
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| CN102169868A true CN102169868A (en) | 2011-08-31 |
| CN102169868B CN102169868B (en) | 2012-11-14 |
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| CN2011100422014A Expired - Fee Related CN102169868B (en) | 2011-02-22 | 2011-02-22 | On-chip integrated inductor |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104681537A (en) * | 2015-01-06 | 2015-06-03 | 武汉新芯集成电路制造有限公司 | Transformer in three-dimensional stacked package chip and preparation method for transformer |
| CN109216316A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | Stacked spirals inductance |
| US20190057803A1 (en) * | 2016-05-19 | 2019-02-21 | Murata Manufacturing Co., Ltd. | Multilayer substrate and a manufacturing method of the multilayer substrate |
| CN109638000A (en) * | 2019-01-29 | 2019-04-16 | 安徽安努奇科技有限公司 | A kind of integrated inductance structure and integrated circuit |
| US10283257B2 (en) * | 2016-01-08 | 2019-05-07 | Qualcomm Incorporated | Skewed co-spiral inductor structure |
| CN113871136A (en) * | 2021-08-24 | 2021-12-31 | 锐石创芯（深圳）科技有限公司 | Coupler and radio frequency front end module |
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| US20080272875A1 (en) * | 2005-08-04 | 2008-11-06 | Daquan Huang | "Interleaved Three-Dimensional On-Chip Differential Inductors and Transformers |
| CN101335289A (en) * | 2007-06-26 | 2008-12-31 | 联发科技股份有限公司 | Integrated inductor |
| KR20090098131A (en) * | 2008-03-13 | 2009-09-17 | 레이디오펄스 주식회사 | Multi inductor with minimized layout area and high frequency integrated circuit having the same |
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2011
- 2011-02-22 CN CN2011100422014A patent/CN102169868B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080272875A1 (en) * | 2005-08-04 | 2008-11-06 | Daquan Huang | "Interleaved Three-Dimensional On-Chip Differential Inductors and Transformers |
| CN101335289A (en) * | 2007-06-26 | 2008-12-31 | 联发科技股份有限公司 | Integrated inductor |
| KR20090098131A (en) * | 2008-03-13 | 2009-09-17 | 레이디오펄스 주식회사 | Multi inductor with minimized layout area and high frequency integrated circuit having the same |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104681537A (en) * | 2015-01-06 | 2015-06-03 | 武汉新芯集成电路制造有限公司 | Transformer in three-dimensional stacked package chip and preparation method for transformer |
| CN104681537B (en) * | 2015-01-06 | 2017-07-11 | 武汉新芯集成电路制造有限公司 | Transformer in three-dimensional stacked encapsulation chip and preparation method thereof |
| US10283257B2 (en) * | 2016-01-08 | 2019-05-07 | Qualcomm Incorporated | Skewed co-spiral inductor structure |
| US20190057803A1 (en) * | 2016-05-19 | 2019-02-21 | Murata Manufacturing Co., Ltd. | Multilayer substrate and a manufacturing method of the multilayer substrate |
| US11923123B2 (en) * | 2016-05-19 | 2024-03-05 | Murata Manufacturing Co., Ltd. | Multilayer substrate and a manufacturing method of the multilayer substrate |
| CN109216316A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | Stacked spirals inductance |
| CN109216316B (en) * | 2017-07-03 | 2020-09-08 | 无锡华润上华科技有限公司 | Stacked spiral inductor |
| CN109638000A (en) * | 2019-01-29 | 2019-04-16 | 安徽安努奇科技有限公司 | A kind of integrated inductance structure and integrated circuit |
| CN113871136A (en) * | 2021-08-24 | 2021-12-31 | 锐石创芯（深圳）科技有限公司 | Coupler and radio frequency front end module |
| CN113871136B (en) * | 2021-08-24 | 2022-07-26 | 锐石创芯(深圳)科技股份有限公司 | Coupler and radio frequency front end module |
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| Publication number | Publication date |
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| CN102169868B (en) | 2012-11-14 |
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