JP2006066769A - Inductor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an on-chip inductor having a small area occupied by a chip and capable of increasing a self-resonant frequency and a Q-value, and to provide its manufacturing method. <P>SOLUTION: A right-handed spiral structure and a left-handed spiral structure arranged facing each other are wound around an axis in a horizontal direction to a semiconductor substrate. The central end of the right-handed spiral structure is connected with the central end of the left-handed spiral structure. Viewing from the direction of the winding axis, the direction of the current flowing in the right-handed spiral structure and the direction of the current flowing in the left-handed spiral structure are equal and their wirings are closely located each other. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an inductor, in particular, an on-chip inductor and a manufacturing method thereof, and more specifically to an on-chip inductor having a plurality of spiral structures wound around a semiconductor substrate in the horizontal direction and a manufacturing method thereof.

  With the progress of miniaturization and higher functionality of portable devices and the like, high frequency circuit inductor elements are provided on a semiconductor substrate. In such an on-chip inductor, it is desired that a sufficient inductance is obtained and that a high self-resonance frequency and a Q value are obtained, and at the same time, it is desired to reduce the chip occupation area in order to reduce the size of the chip itself. Yes.

  An example of a conventional on-chip inductor is shown in FIG. FIG. 1 is a schematic perspective view for explaining an outline of a conventional on-chip inductor. FIG. 1A shows a spiral type inductor having a wiring pattern wound on a semiconductor substrate a plurality of times around the axis perpendicular to the semiconductor substrate. FIG. 1B shows a meander type inductor in which a wiring pattern is bent on a semiconductor substrate. FIG. 1C shows a solenoid type inductor having a wiring pattern wound around a semiconductor substrate a plurality of times around the horizontal direction.

  In the case of the spiral inductor shown in FIG. 1A, a lead pattern is required from the center end of the spiral, and the lead pattern has to be arranged so as to cross the spiral, so that there is a problem that inductance is reduced. . In the meander type inductor shown in FIG. 1B, the directions of the currents flowing in the neighboring bent wirings are opposite to each other, so that the mutual inductance is canceled out and the inductance is reduced. It was. Further, these inductors have a large chip occupation area with respect to the obtained inductance. Further, the solenoid type inductor of FIG. 1C has a smaller chip occupation area than a spiral type inductor, but it is difficult to increase the inductance. In order to increase the inductance, the number of turns may be increased. However, increasing the number of turns eventually increased the chip occupation area.

  Therefore, as shown in Non-Patent Document 1, Patent Document 1, and Patent Document 2, etc., a spiral pattern wound around a semiconductor substrate on the axis perpendicular to the semiconductor substrate, and oppositely wound in the opposite direction. A laminated spiral structure in which the wound spiral pattern is laminated in the vertical direction has been considered. According to these, a large inductance can be obtained for the same chip occupation area.

JP-A-9-330816 JP 2003-347123 A Genen, M.M. W. Green, G .; J. et al. Arnold, R .; G. Jenkins, J .; A. Jansen, R .; H. , “Miniature multilayer spiral inductors for GaAs MMICs”, Page (s): 303-306, Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1989. Technical Digest 1989. , 11th Annual

  However, although the inductance can be increased in the laminated spiral structure as described above, a chip occupation area similar to that of the spiral inductor as shown in FIG.

  There is also a problem that it is difficult to increase the self-resonance frequency. The self-resonant frequency ω is defined by 1 / √ (LC), and the capacitance C is a capacitance that the inductor has parasitically. When the inductor is formed on the semiconductor substrate, the capacitance C includes the wiring-substrate capacitance and the wiring capacitance. Accordingly, the laminated spiral type has a large opposing area between the semiconductor substrate and the wiring pattern and a large parasitic capacitance, so that the self-resonant frequency is low.

  Furthermore, there is a problem that it is difficult to increase the Q value. In the case of the laminated spiral structure, the magnetic flux is perpendicular to the semiconductor substrate. However, when a highly conductive substrate material is used, the magnetic flux in the perpendicular direction is canceled out by the substrate, so that the inductance is reduced. Therefore, since the Q value is defined by ωL / R, when the inductance L decreases, the Q value also decreases.

  In general, when an on-chip inductor is formed in a rewiring layer or the like on a semiconductor substrate, a position as far as possible from the semiconductor substrate, that is, the uppermost wiring layer is used in order to reduce parasitic capacitance with the semiconductor substrate. . However, in the case of the laminated spiral structure, since the lower spiral structure is closer to the semiconductor substrate, the parasitic capacitance is increased and the self-resonant frequency is lowered. Since the facing area between the substrate and the wiring pattern is wide, the influence that the wiring pattern becomes closer to the semiconductor substrate is large, and the lamination of the spiral structure has a large influence on the self-resonant frequency.

  In view of such circumstances, the present invention intends to provide an inductor having a small chip occupying area and capable of increasing a self-resonant frequency and a Q value, and a manufacturing method thereof.

  In order to achieve the above-described object of the present invention, an inductor according to the present invention faces a right-handed spiral structure and a right-handed spiral structure wound more than one turn around the horizontal direction with respect to the semiconductor substrate. The left-handed spiral structure wound more than one turn around the horizontal direction with respect to the semiconductor substrate is connected to the center end of the right-handed spiral structure and the center end of the left-handed spiral structure. A connecting portion or a connecting portion to which the outer end of the right-handed spiral structure and the outer end of the left-handed spiral structure are connected is provided.

  The right-handed spiral structure and the left-handed spiral structure may have the same winding axis.

  Furthermore, the right-handed spiral structure and the left-handed spiral structure may each be wound in a plane perpendicular to the semiconductor substrate.

  Furthermore, it is preferable that the direction of the current flowing through the right-handed spiral structure and the direction of the current flowing through the left-handed spiral structure are equal when viewed from the winding axis direction.

  Further, it is preferable that the wirings having the same current direction among the wirings of the right-handed spiral structure and the wirings of the left-handed spiral structure are positioned in the vicinity.

  Furthermore, it has a plurality of right-handed spiral structures and left-handed spiral structures, and the plurality of right-handed and left-handed spiral structures are alternately arranged, and the outer ends of the spiral structures are adjacent to the outer ends of the spiral structures adjacent on one side It may be connected and the center end of the spiral structure may be connected to the center end of the spiral structure adjacent on the opposite side.

  The on-chip inductor may be input / output symmetric.

  Furthermore, the spiral structure may be provided in the rewiring layer.

  Further, the spiral structure may be configured by a multilayer substrate and vias.

  Here, the multilayer substrate may have an insulating layer made of a magnetic material or a low dielectric material between them.

  Note that the right-handed spiral structure and the left-handed spiral structure may be 1.5 turns or 2.5 turns.

  The method of forming an on-chip inductor according to the present invention includes a process of providing a right-handed spiral structure on a semiconductor substrate, the right-handed spiral structure being wound more than one turn around the horizontal direction with respect to the semiconductor substrate. And a process of providing a left-handed spiral structure that is disposed so as to face the spiral structure and wound more than one turn around the horizontal direction with respect to the semiconductor substrate. The process of providing a right-handed spiral structure and the process of providing a left-handed spiral structure include a process of forming a first insulator layer directly or between other layers on a semiconductor substrate, and a first insulation. Forming a first wiring layer on the body layer; forming a second insulator layer on the first wiring layer; forming a first via in the second insulator layer; Forming a second wiring layer on the second insulating layer; forming a third insulating layer on the second wiring layer; and forming a second via in the third insulating layer. A step of forming a third wiring layer on the third insulating layer, a step of forming a fourth insulating layer on the third wiring layer, and a third via in the fourth insulating layer. And a step of forming a fourth wiring layer on the fourth insulator layer. In each of the first to fourth wiring layers, the second wiring layer and the third wiring layer are connected by the second via, and the first wiring layer and the third wiring layer are connected by the first via and the second via. The first wiring layer and the fourth wiring layer are connected by the first via, the second via, and the third via, and the center end of the right-handed spiral structure and the center end of the left-handed spiral structure are connected, Alternatively, patterning may be performed so that the outer end of the right-hand spiral structure and the outer end of the left-hand spiral structure are connected.

  Here, the first to fourth wiring layers may be patterned so that the right-handed spiral structure and the left-handed spiral structure are each wound in a plane perpendicular to the semiconductor substrate.

  And providing a plurality of right-handed spiral structures and left-handed spiral structures, wherein the plurality of right-handed and left-handed spiral structures are alternately arranged, and the spiral structure has an outer end adjacent on one side. The first to fourth wiring layers may be patterned so that the center end of the spiral structure is connected to the center end of the adjacent spiral structure on the opposite side.

  Further, the process of forming the third insulator layer includes a process of forming a fifth wiring layer, a process of forming a fifth insulator layer on the fifth wiring layer, and a fifth insulator layer. A process for forming a fourth via and a process for forming a sixth wiring layer on the fifth insulator layer. The second wiring layer, the fifth wiring layer, and the sixth wiring may be provided. If the layer is patterned so that the fifth wiring layer and the sixth wiring layer are connected by the fourth via, and the second wiring layer and the sixth wiring layer are connected by the second via and the fourth via. good.

  The inductor and the manufacturing method thereof according to the present invention have an advantage that the chip occupation area with respect to the obtained inductance can be reduced, and the self-resonance frequency and the Q value can be increased.

  The best mode for carrying out the present invention will be described below with reference to the drawings. In the illustrated example and the like, the on-chip inductor formed in the multilayer wiring layer and the rewiring layer on the semiconductor integrated circuit is basically described. However, the present invention is not limited to this, and the multilayer printed circuit is not limited to the integrated circuit. It may be an inductor formed on a mounting substrate such as a substrate. Therefore, the term “multilayer substrate” in the present specification includes all of a plurality of layers such as a multilayer wiring layer, a rewiring layer, and a multilayer printed board.

  FIG. 2 is a schematic perspective view showing the on-chip inductor of the present invention. As shown in FIG. 2, the on-chip inductor of the present invention is a structure in which a right-handed spiral structure and a left-handed spiral structure are connected at their center ends. The right-handed spiral structure includes a wiring layer 4 and vias 30, 20, 10, a wiring layer 1 and vias 11 and 21, a wiring layer 3 and vias 22, and a wiring layer 2. It has a structure in which more than 1 volume is wound in the right volume. Further, the left-handed spiral structure is arranged so as to face the right-handed spiral structure, and the wiring 4 ′ and the vias 31 ′, 21 ′, 11 ′, the wiring 1 ′, the vias 10 ′, 20 ′, and the wiring 3 ′. And a via 22 'and a wiring 2', and is structured to be wound more than one turn in a left turn in a plane with the horizontal direction as an axis with respect to the semiconductor substrate.

  The wirings 2 and 2 'at the center ends of the right-handed spiral structure and the left-handed spiral structure are connected in the middle between the vias 22 and 22'. By connecting symmetrically in the middle, the on-chip inductor is input / output symmetric. In the illustrated example, the wiring 2 and the wiring 2 ′ are connected to each other at the center and are symmetric with respect to the input / output. However, the present invention is not limited to this and is offset to the left or right between the vias 22 and 22 ′. Of course, it may be configured. In the illustrated example, the center end of the right-handed spiral structure and the center end of the left-handed spiral structure are connected. However, the present invention is not limited to this, and the outer ends, that is, the right-handed spiral structure. The wiring 4 and the left-handed spiral structure wiring 4 ′ may be connected at the center or at the left and right.

The method for manufacturing the on-chip inductor according to the present invention will be specifically described below with reference to FIG. FIG. 3 is a cross-sectional side view of the right-hand spiral structure portion of the on-chip inductor of the present invention. First, a first insulator layer 51 is deposited on a semiconductor substrate 50, for example, a Si substrate. As the insulator layer, for example, SiO ₂ is used. Note that a magnetic material or a low dielectric material may be used as the insulator layer. Next, a conductive material layer 52 such as aluminum is deposited on the first insulator layer 51 and patterned to form the first wiring layer 1. As the conductive material, a low resistivity material such as gold or copper can be used in addition to aluminum. Then, a second insulator layer 53 is deposited on the conductive material layer 52. Further, the first vias 10 and 11 are formed at predetermined positions of the second insulator layer 53. By connecting between wirings to be formed later by these vias, it is possible to form a spiral structure wound around the semiconductor substrate in the horizontal direction. Then, a conductive material layer 54 is deposited on the second insulator layer 53, and the second wiring layer 2 is formed by patterning. Further, a third insulator layer 55 is deposited on the conductive material layer 54 to form second vias 20, 21, and 22. In the illustrated example, the third insulator layer 55 is thicker than the other insulator layers, but this cancels the mutual inductance when the distance between the second and third wiring layers is short. This is to provide a certain distance. Needless to say, this may be realized by using a plurality of other insulator layers and other wiring layers having the same thickness as the other insulator layers. In the present specification, these are collectively referred to as a third insulator layer 55. Next, a conductive material layer 56 is deposited on the third insulator layer 55 and patterned to form the third wiring layer 3. Further, a fourth insulator layer 57 is deposited, and the via 30 is formed. Then, a conductive material layer 58 is deposited, and the fourth wiring layer 4 is patterned on the fourth insulator layer 57. In this way, the wiring layers are connected by vias, and a spiral structure is formed that is wound clockwise with the horizontal direction as an axis with respect to the semiconductor substrate. Specifically, the second wiring layer 2 and the third wiring layer 3 are connected by the via 22, the first wiring layer 1 and the third wiring layer 3 are connected by the via 11 and the via 21, and the first wiring layer 1 And the fourth wiring layer 4 are connected by the via 10, the via 20, and the via 30. As described above, the spiral structure of the on-chip inductor according to the present invention is configured by using a multilayer substrate and vias each including a large number of insulator layers and wiring layers.

  Each wiring layer also has a left-handed spiral structure wiring layer at the same level, and is connected by vias in the same way as the right-handed spiral structure, forming a spiral structure that is wound left-handed around the horizontal direction with respect to the semiconductor substrate Is done. The second wiring layer is patterned so that the second wiring layer 2 that is the center end of the right-handed spiral structure and the center end (not shown) of the left-handed spiral structure are connected at the same level. .

  A wiring pattern of each wiring layer will be described with reference to FIG. FIG. 4A shows an on-chip inductor according to the present invention in which the winding axes of the right-handed spiral structure and the left-handed spiral structure are equal and each spiral structure is patterned so as to be wound in a vertical plane with respect to the semiconductor substrate. It is an upper surface schematic diagram which shows the wiring pattern of each wiring layer. The on-chip inductor of the present invention is basically composed of four wiring layers, and the wiring pattern of each wiring layer has the same wiring length for the right-handed spiral structure and the left-handed spiral structure as shown in the figure. The vias are provided at predetermined positions. Thus, the right-handed spiral structure composed of the wirings 1 to 4 and the left-handed spiral structure composed of the wirings 1 ′ to 4 ′ are formed on the insulator layer. As described above, it is preferable to provide a sufficient distance between the second wiring layer and the third wiring layer.

  FIG. 4B shows a wiring in which the wiring pattern of the second wiring layer to which the right-handed spiral structure and the left-handed spiral structure are connected is asymmetrical, and the on-chip inductor is asymmetrical between input and output. It is an upper surface schematic diagram which shows a pattern. Of course, an input / output asymmetric inductor may be used as shown in FIG.

  The influence of the mutual inductance between the on-chip inductor thus configured and the conventional solenoid inductor will be described with reference to FIG. FIG. 5 is a diagram for explaining the influence of mutual inductance in the conventional solenoid type inductor and the inductor of the present invention. FIG. 5A is a schematic perspective view of the conventional solenoid type inductor and its wiring portion. FIG. 5B is a perspective view of the inductor of the present invention and a cross-sectional view of the wiring portion thereof. As shown in the figure, the wiring of the present invention has the same direction of the current flowing through the spiral structure when viewed from the winding axis direction, and each wiring is located in the vicinity as shown in FIG. Therefore, as compared with the wiring arranged in a line as in the conventional solenoid type inductor shown in FIG. 5A, in the present invention, each wiring is located in the vicinity, so that three wirings per one. The mutual inductance due to can be increased.

  Table 1 shows the simulation results of the characteristics of the spiral type, meander type, and solenoid type inductors shown in FIG. As can be seen from Table 1, the inductor of the present invention has the smallest chip occupation area. Further, although the chip occupation area is small, the inductance L can be sufficiently obtained, and since the chip occupation area is small, it is possible to prevent the Q value from being reduced due to the substrate resistance. Furthermore, it can be seen that a sufficiently high characteristic can be obtained for the self-resonant frequency.

  In order to obtain a larger inductance, the distance between wirings with the same direction of current flow can be reduced even if the chip occupation area remains the same, or the distance between wirings with different current flow directions can be increased. . Further, the inductance can be improved by increasing the number of turns or increasing the wiring length. Further, the Q value can be improved by using a low resistivity substance such as gold or copper as the wiring material or by increasing the width or thickness of the wiring. Furthermore, it is possible to improve inductance, Q value, and self-resonance frequency by providing an insulating layer made of a magnetic material or a low dielectric material between wirings.

  Here, an example of increasing the number of turns of the spiral structure of the present invention will be described with reference to FIGS. FIG. 6 is a schematic perspective view for explaining an example in which a plurality of spiral structures are provided, which is a modification of the on-chip inductor of the present invention. As shown in the figure, in this example, the spiral structures are arranged so as to face each other, and four right-handed spiral structures and two left-handed spiral structures that are wound around the semiconductor substrate in the horizontal direction are provided alternately. Is. The left-handed spiral structure adjacent to the right-handed spiral structure is connected at the center end, and the right-handed spiral structure adjacent to the right-handed spiral structure on the opposite side is connected at the outer end to be connected in series. As a result, the inductance can be improved. In addition, even in this case, the chip occupation area can be made smaller than in the conventional example.

  Further, as shown in FIG. 7, the number of turns of the right-handed spiral structure and the left-handed spiral structure itself can be increased. In the spiral structure of the present invention shown in FIG. 2 and the like, the spiral is one or more turns, specifically 1.5 turns, but in the case of the on-chip inductor of FIG. It has a structure. It is also possible to increase the number of turns in this way. However, in the vicinity of the center of the spiral, the interval between the wirings through which current flows in the opposite direction is narrowed. Therefore, it is preferable that the interval be sufficiently wide so as not to cancel the mutual inductance.

  Next, another modification of the spiral structure of the on-chip inductor of the present invention will be described. FIG. 8 is a schematic top view for explaining a wiring pattern of each wiring layer according to another modification of the on-chip inductor of the present invention. In this example, the right-handed spiral structure composed of the wiring 1 to the wiring 4 and the left-handed spiral structure composed of the wiring 1 ′ to the wiring 4 ′ have the same winding axis. Each is not wound in a plane, and the right-handed spiral structure and the left-handed spiral structure are wound closer to each other toward the center. As a result, the parasitic capacitance between the wirings can be reduced, and the self-resonance frequency can be increased. However, since the mutual inductance decreases, the Q value also decreases. Therefore, these configurations may be variously selected depending on the application.

  Furthermore, as shown in FIG. 9A, the winding is performed in a plane perpendicular to the semiconductor substrate. However, the winding axes of the spiral structures may not coincide with each other and may be offset. Even in such a configuration, the self-resonance frequency can be increased although there is a trade-off with the Q value and the inductance. Furthermore, as shown in FIG. 9B, each spiral structure may be configured so that it is wound in a non-planar manner and the winding axes do not coincide.

  As described above, in the on-chip inductor of the present invention, the chip occupation area can be reduced, so that the facing area between the wiring and the semiconductor substrate can be reduced, and the distance can be increased. Since it is possible, the self-resonant frequency can be increased. Also, since the spiral structure is wound around the semiconductor substrate in the horizontal direction, unlike the case where the substrate is wound around the vertical direction, the magnetic flux is not canceled by the substrate. It becomes difficult to be influenced by the Q value with respect to the conductivity.

  Note that the on-chip inductor and the manufacturing method thereof according to the present invention are not limited to the illustrated examples described above, and it is needless to say that various changes can be made without departing from the gist of the present invention. For example, in the above-described example, the on-chip inductor of the present invention is provided on a multilayer substrate or a rewiring layer. However, the present invention is not limited to this, and may be configured with three-dimensional wiring by, for example, MEMS technology. Absent.

FIG. 1 is a schematic perspective view for explaining three types of conventional on-chip inductors. FIG. 2 is a schematic perspective view showing the on-chip inductor of the present invention. FIG. 3 is a cross-sectional side view of the right-hand spiral structure portion of the on-chip inductor of the present invention. FIG. 4 is a schematic top view for explaining the wiring pattern of each wiring layer of the on-chip inductor of the present invention. FIG. 5 is a diagram for explaining the influence of mutual inductance in the conventional solenoid type inductor and the inductor of the present invention. FIG. 6 is a schematic perspective view for explaining an example in which a plurality of on-chip inductor spiral structures of the present invention are provided. FIG. 7 is a schematic perspective view for explaining an example in which the number of turns of the spiral structure itself of the on-chip inductor of the present invention is increased. FIG. 8 is a schematic top view for explaining the wiring pattern of each wiring layer in another example of the on-chip inductor of the present invention. FIG. 9 is a schematic top view for explaining a wiring pattern of each wiring layer of still another example of the on-chip inductor of the present invention.

Explanation of symbols

1, 1 '1st wiring layer 2, 2' 2nd wiring layer 3, 3 '3rd wiring layer 4, 4' 4th wiring layer 10, 11, 20, 21, 22, 30, 10 ', 11', 20 ', 21', 22 ', 31' Via 50 Semiconductor substrate

Claims (17)

An inductor formed on a semiconductor substrate, the inductor comprising:
A right-handed spiral structure wound more than one turn around the horizontal direction with respect to the semiconductor substrate;
A left-handed spiral structure that is disposed so as to face the right-handed spiral structure and is wound left-handed more than one turn around the horizontal direction with respect to the semiconductor substrate;
A connection portion where the center end of the right-handed spiral structure and the center end of the left-handed spiral structure are connected, or a connection where the outer end of the right-handed spiral structure and the outer end of the left-handed spiral structure are connected And
An inductor comprising:   2. The inductor according to claim 1, wherein the right-handed spiral structure and the left-handed spiral structure have the same winding axis.   2. The inductor according to claim 1, wherein the right-handed spiral structure and the left-handed spiral structure are each wound in a plane perpendicular to the semiconductor substrate.   4. The inductor according to claim 1, wherein a direction of current flowing through the right-handed spiral structure is equal to a direction of current flowing through the left-handed spiral structure when viewed from the winding axis direction. Inductor.   5. The inductor according to claim 4, wherein wirings having the same current direction are arranged in the vicinity of the right-handed spiral structure wiring and the left-handed spiral structure wiring. 6.   6. The inductor according to claim 1, further comprising a plurality of right-handed spiral structures and left-handed spiral structures, wherein the plurality of right-handed and left-handed spiral structures are alternately arranged. The inductor is characterized in that the outer end of the spiral structure is connected to the outer end of the adjacent spiral structure on one side, and the center end of the spiral structure is connected to the center end of the adjacent spiral structure on the opposite side.   The inductor according to claim 6, wherein two right-handed spiral structures and two left-handed spiral structures are provided.   8. The inductor according to claim 1, wherein the inductor is input / output symmetric.   The inductor according to any one of claims 1 to 8, wherein the spiral structure is provided in a rewiring layer.   The inductor according to any one of claims 1 to 8, wherein the spiral structure includes a multilayer substrate and vias.   11. The inductor according to claim 10, wherein the multilayer substrate has an insulating layer made of a magnetic material or a low dielectric material between them.   The inductor according to any one of claims 1 to 11, wherein the right-handed spiral structure and the left-handed spiral structure are 1.5 turns or 2.5 turns. A method of forming an inductor on a semiconductor substrate, the method comprising:
Providing a right-handed spiral structure on the semiconductor substrate, the right-handed winding being wound more than one turn around the horizontal direction with respect to the semiconductor substrate;
Providing a left-handed spiral structure that is arranged to face the right-handed spiral structure and is wound left-handed more than one turn around the horizontal direction with respect to the semiconductor substrate;
Comprising
The process of providing the right-handed spiral structure and the process of providing the left-handed spiral structure are as follows:
Forming a first insulator layer directly or between other layers on the semiconductor substrate;
Forming a first wiring layer on the first insulator layer;
Forming a second insulator layer on the first wiring layer;
Forming a first via in the second insulator layer;
Forming a second wiring layer on the second insulator layer;
Forming a third insulator layer on the second wiring layer;
Forming a second via in the third insulator layer;
Forming a third wiring layer on the third insulator layer;
Forming a fourth insulator layer on the third wiring layer;
Forming a third via in the fourth insulator layer;
Forming a fourth wiring layer on the fourth insulator layer;
Comprising
Each of the first to fourth wiring layers is
The second wiring layer and the third wiring layer are connected by the second via,
The first wiring layer and the third wiring layer are connected by the first via and the second via,
The first wiring layer and the fourth wiring layer are connected by the first via, the second via, and the third via,
The center end of the right-handed spiral structure and the center end of the left-handed spiral structure are connected, or the outer end of the right-handed spiral structure and the outer end of the left-handed spiral structure are connected,
So that it is patterned,
An inductor manufacturing method characterized by the above.   14. The method according to claim 13, wherein the first to fourth wiring layers are patterned so that the right-handed spiral structure and the left-handed spiral structure are each wound in a plane perpendicular to the semiconductor substrate. An inductor manufacturing method characterized by the above.   15. The method according to claim 13, further comprising providing a plurality of the right-handed spiral structure and the left-handed spiral structure, wherein the plurality of right-handed and left-handed spiral structures are alternately provided. The first ends are arranged such that the outer ends of the spiral structures are connected to the outer ends of the adjacent spiral structures on one side, and the center ends of the spiral structures are connected to the center ends of the adjacent spiral structures on the opposite side. A method for manufacturing an inductor, wherein the fourth wiring layer is patterned.   16. The method of manufacturing an inductor according to claim 15, wherein two right-handed spiral structures and two left-handed spiral structures are provided. 17. The method according to any one of claims 13 to 16, wherein the step of forming the third insulator layer further includes
Forming a fifth wiring layer;
Forming a fifth insulator layer on the fifth wiring layer;
Forming a fourth via in the fifth insulator layer;
Forming a sixth wiring layer on the fifth insulator layer;
Comprising
Each of the second wiring layer, the fifth wiring layer, and the sixth wiring layer is
The fifth wiring layer and the sixth wiring layer are connected by the fourth via,
The second wiring layer and the sixth wiring layer are connected by the second via and the fourth via;
So that it is patterned,
An inductor manufacturing method characterized by the above.