CN102160178A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN102160178A
CN102160178A CN2009801365043A CN200980136504A CN102160178A CN 102160178 A CN102160178 A CN 102160178A CN 2009801365043 A CN2009801365043 A CN 2009801365043A CN 200980136504 A CN200980136504 A CN 200980136504A CN 102160178 A CN102160178 A CN 102160178A
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CN
China
Prior art keywords
electrode
capacitor
memory element
film
semiconductor device
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Granted
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CN2009801365043A
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Chinese (zh)
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CN102160178B (en
Inventor
阿部贵征
高桥康之
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Publication of CN102160178A publication Critical patent/CN102160178A/en
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Publication of CN102160178B publication Critical patent/CN102160178B/en
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract

A semiconductor device including a memory cell is provided. The memory cell comprises a transistor, a memory element and a capacitor. One of first and second electrodes of the memory element and one of first and second electrodes of the capacitor are formed by a same metal film. The metal film functioning as the one of first and second electrodes of the memory element and the one of first and second electrodes of the capacitor is overlapped with a film functioning as the other of first and second electrodes of the capacitor.

Description

Semiconductor device
Technical field
The present invention relates to semiconductor device and manufacture method thereof.
Background technology
Have high reliability, low manufacturing cost and use widely with the memory that forms such as the inorganic semiconductor element of silicon, thus generally widely known to.
The research and development of using conventional material and technology will use inorganic semiconductor element, dielectric film and/or the wiring of silicon etc. to be formed at the novel memory on the flexible substrate have therein obtained carrying out energetically.
Be formed at such as the memory on the flexible substrate of plastics and can be embedded in the paper, and be considered with the business card card that acts on information exchange, poster etc.
At (OTP) of One Time Programmable memory (promptly, can write memory of data by the fracture of dielectric film when the write data and the short circuit between the wiring) research and development in, in the time of on semiconductor element is formed on flexible substrate, manufacturing process of (OTP) memory of this One Time Programmable and operation are relatively easy in some cases.
In the memory cell of the memory of anti-fusing type, arranged that auxiliary capacitor is to improve write capability.In the memory of routine, auxiliary capacitor and memory component are by independent layout.
Below auxiliary capacitor will be described.When being written in parallel to, provide capacitor to the element supplies charges (below, be called auxiliary capacitor) to make it possible to realize that height writes yield (yield in writing) with element.The example of auxiliary capacitor comprises those capacitors that contain each mos capacitance device that is all formed by " active layer-GI film-metal film ", and those capacitors that contain each MIM (metal-insulator-metal type) capacitor that is all formed by " metal film-dielectric film-metal film ".
[patent documentation 1] Japanese Laid-Open Patent Application No.H02-023653
Summary of the invention
The increase of the figure place of memory has caused the increase of the area of memory cell.The percentage of the area that is taken by the memory cell (comprising memory cell, decoder, interface, booster circuit etc.) of memory circuit is big and increase along with the change of figure place.This is because be under the N situation doubly at holding capacitor, respectively the do for oneself subduplicate multiple of N of the area of row decoder and column decoder, and the area of memory cell be N doubly.
Figure 21 A schematically shows memory cell to 21C area is along with the quantity of holding capacitor increases and increases.Memory circuit 2100 comprises memory cell 2107, column decoder 2105, row decoder 2106, interface 2104 and the booster circuit 2103 with substantially the same area occupied.Memory circuit 2101 has 4 times of figure places to memory circuit 2100.Memory circuit 2102 has 16 times of figure places to memory circuit 2100.In memory circuit 2100, the percentage of the area occupied of memory cell is 20%, and figure place is that the percentage of the area occupied of memory cell in 4 times the memory circuit 2101 is about 40% therein, and figure place is that the percentage of the area occupied of memory cell in 16 times the memory circuit 2102 is more than 60% therein.
This shows that at the area that reduces memory cell aspect the high integration of memory circuit or the miniaturization be important.
The present invention has considered this problem and has made, and the memory device that has wherein reduced the area of memory cell under the situation that does not increase technology is provided.
The memory element in memory cell and the lamination of the auxiliary capacitor electrode by making memory element and auxiliary capacitor forms as public electrode, thereby makes the memory cell minification thus and make the chip can minification.Thereby cost can reduce.
In the auxiliary capacitor with MOS structure, writing efficient can be by improving p type impurity as the impurity that is added into active layer.
In order to reach above target, a kind of embodiment of the present invention comprises the semiconductor device of selecting transistor, memory element and auxiliary capacitor, and wherein an electrode of memory element electrode and auxiliary capacitor is public; Another electrode of auxiliary capacitor is formed by the semiconductor film with impurity; And a described electrode of memory element and described another electrode of auxiliary capacitor are overlapping, have dielectric film between them.
In order to reach above target, a kind of embodiment of the present invention comprises the semiconductor device of selecting transistor, memory element and auxiliary capacitor, wherein select transistorized gate electrode, an electrode of memory element and an electrode of auxiliary capacitor form simultaneously; A described electrode of memory element and a described electrode of auxiliary capacitor are public; Select another electrode of transistorized active layer and auxiliary capacitor to form by the semiconductor film that forms simultaneously and be doped with impurity; The dielectric film of auxiliary capacitor and the transistorized gate insulating film of selection form simultaneously; And a described electrode of memory element and described another electrode of auxiliary capacitor are overlapping, have described dielectric film between them.
In order to reach above target, a kind of embodiment of the present invention comprises the semiconductor device of selecting transistor, memory element and auxiliary capacitor, and wherein an electrode of memory element electrode and auxiliary capacitor is public; Select in transistorized source electrode and the drain electrode one to be electrically connected with another electrode of memory element and another electrode of auxiliary capacitor; Described another electrode of auxiliary capacitor is formed by the semiconductor film with impurity; And a described electrode of memory element and described another electrode of auxiliary capacitor are overlapping, have dielectric film between them.
In order to reach above target, a kind of embodiment of the present invention comprises the semiconductor device of selecting transistor, memory element and auxiliary capacitor, and wherein auxiliary capacitor comprises three electrodes and two dielectric films; Electrode of memory element and first electrode of auxiliary capacitor are public; Second electrode of auxiliary capacitor is formed by the semiconductor film with impurity; Another electrode of memory element and the third electrode of auxiliary capacitor are public; First dielectric film of auxiliary capacitor and the transistorized gate insulating film of selection form simultaneously; Second dielectric film of auxiliary capacitor and the transistorized interlayer dielectric of selection form simultaneously; A described electrode of memory element and second electrode and the third electrode of auxiliary capacitor are overlapping, have first dielectric film and second dielectric film between them.
Another electrode of auxiliary capacitor is according to an embodiment of the present formed by the semiconductor film with p type impurity.
In order to reach above target, a kind of embodiment of the present invention comprises the semiconductor device of selecting transistor, memory element and auxiliary transistor, and wherein an electrode of memory element electrode and auxiliary capacitor is public; Another electrode of auxiliary capacitor is formed by metal film; And a described electrode of memory element and another electrode of auxiliary capacitor are overlapping, have dielectric film between them.
An electrode of memory element according to an embodiment of the present uses tungsten to form.
Semiconductor device according to an embodiment of the present is formed on the flexible substrate.
Semiconductor device according to an embodiment of the present is the chipset contoured beam antenna.
Being used to make according to the structure of the method for the semiconductor device of disclosed a kind of embodiment of the present invention in this manual is the method that is used for producing the semiconductor devices, and may further comprise the steps: metal film is formed on the substrate; First dielectric film is formed on the described metal film; Semiconductor film is formed on described first dielectric film; The described semiconductor film of etching is to form first island semiconductor film and second island semiconductor film; Second dielectric film is formed on described first island semiconductor film and described second island semiconductor film; Mask is formed on described first island semiconductor film, and p type impurity is added into described second island semiconductor film, described first island semiconductor film is covered by this mask; Removal covers the described mask of described first island semiconductor film and metal film is formed on described first island semiconductor film and described second island semiconductor film; The described metal film of etching is so that gate electrode is formed on described first island semiconductor film and first electrode is formed on described second island semiconductor film; Mask is formed on described second island semiconductor film, and n type impurity is added into described first island semiconductor film, gate electrode is covered by this mask as mask and described second island semiconductor film; Remove the described mask that covers described second island semiconductor film, mask is formed on described first island semiconductor film, and p type impurity is added on described second island semiconductor film, described first electrode is covered by this mask as mask and described first island semiconductor film; Remove the described mask that covers described first island semiconductor film; The 3rd dielectric film is formed on described first island semiconductor film and described second island semiconductor film; By etching the 3rd dielectric film anisotropically sidewall is formed on described gate electrode and described first electrode; Described second dielectric film that removal is exposed from described gate electrode, described first electrode and described sidewall; Mask is formed on described second island semiconductor film, and n type impurity is added into described first island semiconductor film, described second island semiconductor film is covered by this mask; Remove the described mask that covers described second island semiconductor film; The 4th dielectric film is formed on described first island semiconductor film and described second island semiconductor film; The pentasyllabic quatrain velum is formed on described the 4th dielectric film; First contact hole is formed in described the 4th dielectric film and described pentasyllabic quatrain velum on described first electrode; Cambium layer in described first contact hole; With second contact hole, the 3rd contact hole, the 4th contact hole, the 5th contact hole and the 6th contact hole are formed at described first island semiconductor film, described gate electrode, within described the 4th dielectric film and described pentasyllabic quatrain velum on described second island semiconductor film and described first electrode, wherein said second contact hole and the 4th contact hole are formed on described first island semiconductor film, described the 3rd contact hole is formed on the described gate electrode, described the 5th contact hole is formed on described second island semiconductor film, and described the 6th contact hole is formed on described first electrode; Metal film is formed on described pentasyllabic quatrain velum and described first contact hole to the, six contact holes; The described metal film of etching makes described first contact hole, described the 4th contact hole and described the 5th contact hole be electrically connected and described second contact hole, described the 3rd contact hole and described the 6th contact hole are not electrically connected; And remove described substrate and described metal film so that described first dielectric film is fixed in the plate substrate.
In the said method that is used for producing the semiconductor devices, described first electrode and described gate electrode comprise tungsten.
In the said method that is used for producing the semiconductor devices, the plate substrate is any in plastics, paper, prepreg and the ceramic wafer.
In the said method that is used for producing the semiconductor devices, described layer is that wherein silicon oxynitride is stacked in lamination on the amorphous silicon.
The memory element in the memory cell and the lamination of auxiliary capacitor are formed, and can make the memory cell minification thus.Thereby cost can reduce.
In auxiliary capacitor, write efficient and can improve, thereby can improve reliability by p type impurity is used as the impurity that is added into active layer with MOS structure.
Description of drawings
In the accompanying drawings:
Fig. 1 is the cross sectional view of the inside of memory cell according to an embodiment of the present;
Fig. 2 is the cross sectional view of the inside of conventional memory cell;
Fig. 3 is the top view of the inside of conventional memory cell;
Fig. 4 is the top view of the inside of memory cell according to an embodiment of the present;
Fig. 5 is the cross sectional view of laminated construction with auxiliary capacitor of MOS structure according to an embodiment of the present;
Fig. 6 is the cross sectional view of laminated construction with auxiliary capacitor of mim structure according to an embodiment of the present;
Fig. 7 be have according to an embodiment of the present the MOS structure and the cross sectional view of the laminated construction of the auxiliary capacitor of the combination of mim structure;
The circuit that Fig. 8 shows the module of memory cell and is used to drive memory cell;
Fig. 9 is the block diagram that the structure of semiconductor device according to an embodiment of the present is shown;
Figure 10 A and Figure 10 B are respectively the schematic diagram and the cross sectional view of semiconductor device according to an embodiment of the present;
Figure 11 A and Figure 11 B are respectively the schematic diagram and the cross sectional view of second half conductor device according to an embodiment of the present;
Figure 12 A schematically shows the structure and the manufacture method of second half conductor device according to an embodiment of the present to Figure 12 C;
Figure 13 A is the view that the structure of semiconductor device according to an embodiment of the present is shown to Figure 13 C;
Figure 14 A schematically shows the application example of semiconductor device according to an embodiment of the present to Figure 14 F;
Figure 15 A shows the production process of semiconductor device of the semiconductor storage unit that comprises anti-fusing to Figure 15 E;
Figure 16 A shows the production process of semiconductor device of the semiconductor storage unit that comprises anti-fusing to Figure 16 E;
Figure 17 A shows the production process of semiconductor device of the semiconductor storage unit that comprises anti-fusing to Figure 17 E;
Figure 18 A shows the production process of semiconductor device of the semiconductor storage unit that comprises anti-fusing to Figure 18 C;
Figure 19 A shows the production process of semiconductor device of the semiconductor storage unit that comprises anti-fusing to Figure 19 D;
Figure 20 shows the difference of writing yield based on the polarity of the adminicle with MOS structure according to an embodiment of the present; And
Figure 21 A schematically shows the conventional situation of the area occupied that increases memory cell to Figure 21 C.
Embodiment
Embodiments of the invention will illustrate with reference to the accompanying drawings.But the present invention is not limited to following description, and those skilled in the art should be understood that easily that pattern of the present invention and details can revise in every way under the situation that does not break away from the spirit and scope of the present invention.The description of the embodiment that will provide below therefore, the present invention should not be interpreted as being defined in.
Embodiment 1
Embodiment 1 will describe memory device according to an embodiment of the present.
Fig. 1 is the cross sectional view of the inside of memory device.Memory cell 1000 comprises selects transistor 1001, auxiliary capacitor 1002 and memory element 1003.Select transistor 1001 to comprise active layer 1004a, dielectric film 1009 and electrode 1005 (gate electrode 1005).Electrode 1007a, 1007b (source electrode and drain electrode 1007a, 1007b) are electrically connected with source region and the drain region of active layer 1004a.Auxiliary capacitor 1002 comprises active layer 1004b, dielectric film 1009 and electrode 1006, and memory element 1003 comprises electrode 1007c, electrode 1006 and semiconductor film 1008.
As shown in Figure 1, select terminal, the terminal of auxiliary capacitor 1002 and the terminal of memory element 1003 of transistor 1001 to be electrically connected.Electrode 1006 is used for a terminal of auxiliary capacitor 1002 and a terminal of memory element 1003 jointly, and is connected to negative electrode (power line) by electrode 1007c.In addition, resistance and the difference between the resistance after the short circuit before the short circuit of memory element according to an embodiment of the present is about 10 6As general value is 100M Ω or bigger, is preferably 1G Ω or bigger.In addition, the resistance after the short circuit is 10K Ω or littler, is preferably 1K Ω or littler.As just described, the resistance before the short circuit and the difference of the resistance after the short circuit are about 10 6
To be described in the principle that writes in the memory below.
The electrode 1007a terminal of transistor 1001 (select) is electrically connected with bit line electrode, and electrode 1005 is electrically connected with word line, makes the selecteed element conductive in address thus.When making when selecting transistor 1001 conductings, the electrode 1007b of memory element 1003 is given high potential, and its electrode 1006 gives earthing potential by negative electrode.Thereby voltage or electric current are applied in the electrode of memory element 1003, and when applied amount had surpassed certain voltage level or a certain amount of electric current, electrode was by short circuit.Auxiliary capacitor 1002 is stored charge when selecting transistor 1001 conductings, and will be stored in electric charge in the auxiliary capacitor 1002 by the moment in memory element 1003 short circuits and be fed within the memory element 1003 and promote write state.In addition, when the impurity that has the MOS structure and be added into active layer when auxiliary capacitor 1002 is p type impurity, write that yield is increased and reliability is improved.
Difference with conventional structure will be described below.
Fig. 2 shows the conventional example that comprises the memory cell of selecting transistor, auxiliary capacitor and memory element.In memory cell 2000, select transistor 2001, auxiliary capacitor 2002 and memory element 2003 to be arranged independently, and be electrically connected to 2004d by electrode 2004a.Though do not illustrate, electrode 2004b and electrode 2004d are electrically connected.Be different from conventional example, in an embodiment of the present invention, the electrode of auxiliary capacitor 1002 and the electrode of memory element are public electrodes 1006, and memory element 1003 is stacked on the auxiliary capacitor 1002.
In addition, for the material at the structure division shown in Fig. 1, each is formed active layer 1004a and 1004b by polysilicon film or amorphous silicon film; Electrode 1005, electrode 1006 and electrode 1007 each all by forming such as the such metal film of tungsten, aluminium or titanium with high conductivity; Semiconductor film 1008 (film between the electrode of memory element) forms with the laminated construction of amorphous silicon film and silicon oxynitride (SiON) film; GI film 1009 (dielectric film of gate insulating film and formation capacitor) is used such as silica (SiO 2) the dielectric film of inorganic material form; Identical materials can be applied to the used dielectric film of auxiliary capacitor.Interlayer dielectric 1010 usefulness are such as silicon oxynitride (SiON), silicon oxynitride (SiNO) or silica (SiO 2) inorganic material or form such as the dielectric film of the organic material of polyimides (PI).Especially, the electrode 1006 of memory element (that is, being used for the metal of negative electrode) is preferably tungsten, and efficient is increased and reliability is improved because write.
Fig. 3 is the top view of conventional memory cell, and Fig. 4 is the top view of memory cell according to an embodiment of the present.
In Fig. 3, Reference numeral 3000 indication whole memory unit; 3001, select transistor; 3002, auxiliary capacitor; 3003, memory element.In Fig. 4, be similar to Fig. 3, Reference numeral 4000 indication whole memory unit; 4001, select transistor; 4002, auxiliary capacitor; 4003, memory element.
In an embodiment of the present invention, an electrode of auxiliary transistor 4002 and an electrode of memory element 4003 are public, and memory element 4003 is arranged on the electrode of auxiliary capacitor 4002, thereby the area of comparing memory cell with the memory of routine can reduced size.
Embodiment 2
Embodiment 2 will describe according to an embodiment of the present semiconductor device and the used combination of auxiliary capacitor.
In addition, the material of hereinafter described active layer, GI film, dielectric film and metal film is identical with those materials described in embodiment 1.
Fig. 5 is the cross sectional view of laminated construction with auxiliary capacitor of MOS structure.
In Fig. 5, Reference numeral 5000 indication whole memory unit, auxiliary capacitor 5001 has wherein GI film 5004 (between active layer 5002 and metal film 5003) as the MOS structure of capacitor in this memory cell.As mentioned above, in the capacitor with MOS structure, active layer is doped with n type or p type impurity and makes it can be used as capacitor.Writing yield can be by improving with p type doping impurity active layer.
Fig. 6 is the cross sectional view of laminated construction with auxiliary capacitor of MIM (metal-insulator-metal type) structure.
In Fig. 6, Reference numeral 6000 indication whole memory unit, auxiliary capacitor 6001 has wherein dielectric film 6004 (between metal film 6002 and metal film 6003) as the mim structure of capacitor in this memory cell.
Fig. 7 is the cross sectional view of laminated construction of auxiliary capacitor with combination of MOS structure and mim structure.
In Fig. 7, Reference numeral 7000 indication whole memory unit, auxiliary capacitor 7001 has the combination of MOS structure 7002 and mim structure 7003 in this memory cell.In the MOS structure, GI film 7007 (between active layer 7004 and metal film 7005) is as capacitor, and in mim structure, dielectric film 7008 (between the electrode and public electrode of memory element) is as capacitor.MOS structure and mim structure are combined.Comprise in the situation of a plurality of films at dielectric film 7008, film be contained in parts in the dielectric film 7008 be etched into thin and parts dielectric film 7008 attenuation as capacitor, this is effective.
Embodiment 3
Embodiment 3 will be described with reference to the drawings the structure more specifically of memory device according to an embodiment of the present.
Fig. 8 is the block diagram that the module of memory cell is shown and is used to drive the circuit of memory cell.Memory circuit 8000 comprises memory cell array 8001, column decoder 8002, row decoder 8003, address selector 8004, selector 8005, read/write circuit 8006 and booster circuit 8007.In memory cell array 8001, the memory cell 100 of n * m piece described in embodiment 1 is by matrix arrangements.
The operation of memory circuit is described.For memory circuit 8000, read to enable (RE) signal, write enable (WE) signal, address signal, these operation signals are transfused to boosting timeclock signal (cp_clk, charge pump clock signal), and the stepup transformer input voltage vin is used as electric power.Though do not illustrate, the electric power (for example VDD and GND) that is used for drive circuit is used as the power supply that is used to operate equally.
The operation that RE and WE are imported into selector 8005 and memory is determined.For instance, read operation at RE effectively and WE is non-carries out when effective, write operation at WE effectively and RE is non-carries out when effective, and holding state takes place when effective in that WE and RE are all non-.
In the situation of write operation, also may produce the enable signal that boosts (CPE, charge pump enable signal), this enable signal that boosts is the condition of operation booster circuit.By this way, can suppress increase by the current sinking due to unnecessary the boosting.In addition, control signal produces in write operation or read operation, and is imported into address selector, is prevented by the improper operation due to the driving decoder under holding state thus.
Address signal is divided via address selector 8004, and the signal that demarcates is imported into column decoder 8002 and row decoder 8003.Each all comprises a plurality of decoders column decoder 8002 and row decoder 8003, and a combination by the value of address signal in the included decoder of each decoder is driven.Then, pass through the combination of the decoder that driven, a memory cell that is used to write or read is determined.As mentioned above, also not have to carry out in the state of reading both having to carry out to write, it is non-effective that the control signal that is produced by selector becomes the signal that is input to decoder, and it is selected to make decoder not have.
The read/write circuit 8006 that is connected with column decoder 8002 drives inner reading circuit or write circuit in response to the selection signal that is produced by selector 8005.In this case, write circuit can be driven writing under the state, and perhaps reading circuit can be driven under read states.Sense data 0 or data 1 state of the memory cell that reading circuit has been visited from reading circuit, and it is exported as data outputs (OUTPUT).
Booster circuit 8007 is operated in response to the cp_clk of conduct from the input signal of outside when the CPE that is produced by selector 8005 is effective, amplifies the electric power Vin that applies from the outside, and it is exported as Vout.The structure of booster circuit 8007 can be known structure.Vout is imported into selector 8005, and selector 8005 is supplied it in write operation as the electric power (Vcoldec) of giving column decoder 8002 and to the electric power (Vrowdec) of row decoder 8003.
A kind of embodiment of the present invention can be applied to constitute the memory cell of memory cell array 8001.According to an embodiment of the present, the area of memory cell array 8001 can be reduced, and as a result of, the area of memory circuit 8000 can be reduced.This effect is along with the quantity of the memory cell that constitutes memory cell array 8001 becomes big (in other words, the quantity along with holding capacitor becomes big) and becomes more favourable.
Embodiment 4
Semiconductor device with memory device has according to an embodiment of the present been described in the present embodiment.
Semiconductor device in the present embodiment comprises memory circuit, is stored as the required information of memory circuit, and uses non-contacting means (for example, radio communication) and outside exchange message.By this feature, semiconductor device in the present embodiment has the individual information that for example has been used for storing therein object etc. and discerns the application of the individual authentication system of this object by reading this signal.For example, for the semiconductor device in the present embodiment is used for this application, higher reliability is essential, because the data of relevant individual information are stored with identifying object.
The structure of semiconductor device in the present embodiment is described with reference to Figure 9.Fig. 9 is the block diagram that the structure of semiconductor device in the present embodiment is shown.
As shown in Figure 9, semiconductor device 300 comprises RF circuit 301, clock generating circuit 302, logical circuit 303 and the antenna in antenna part 318 317.Notice that though do not have shown in Figure 9ly, semiconductor device 300 sends to wireless signal such as the external circuit of Wireless Telecom Equipment and from this external circuit by antenna 317 and receives wireless signal.Notice that data transmission method is divided into following three kinds of methods roughly: electromagnetism couples method, a pair of in the method coil is arranged to toward each other and communicates by letter and undertaken by interacting; Electromagnetic induction method, communication uses induction field to carry out in the method; And the electromagnetic wave method, communication uses electromagnetic wave to carry out in the method.In these methods any can be used in the present embodiment.
The structure of every kind of circuit is described below.RF circuit 301 comprises power circuit 304, demodulator circuit 305 and modulation circuit 306.In addition, clock generating circuit 302 comprises frequency dividing circuit 307, counting circuit 309 and reference clock generation circuit 319.In addition, logical circuit 303 has the function of carrying out arithmetic processing, and comprises controller 313, CPU (being also referred to as CPU) 310, ROM (read-only memory) 311 and RAM (random access memory) 312.
In addition, controller 313 comprises cpu i/f 314, RF interface 315 and Memory Controller 316.
In addition, in RF circuit 301, power circuit 304 comprises rectification circuit and holding capacitor, and has by the signal that received and produce supply voltage and supply voltage is supplied to the function of other circuit.Demodulator circuit 305 comprises rectification circuit and LPF (low pass filter) and has the function that extracts order or data from signal of communication.Modulation circuit 306 has the function of modulation transmissions data, and the data of being modulated are used as and send signal and send out from antenna 317.
The operation of semiconductor device in the present embodiment is described below.At first, the signal that sends out from the PERCOM peripheral communication device is received by semiconductor device.The signal that is received that is imported into semiconductor device is by demodulator circuit 305 demodulation and be input to RF interface 315 in the controller 313 then.The signal of being received that is input to RF interface 315 stands arithmetic processing by cpu i/f 314 via CPU310.In addition, utilize the signal of being received that is input to RF interface 315, the visit of ROM 311 and RAM 312 is carried out by Memory Controller 316.
Then, the transmission data generate after arithmetic processing is carried out by CPU 310, and the data among ROM311 and the RAM 312 are transfused to and are output, and transmit data and are modulated to signal and are sent to external communication device from antenna 317 by modulation circuit 306.
In the present embodiment, memory device according to an embodiment of the present can be mounted as the ROM 311 of semiconductor device or RAM 312, perhaps another memory circuit.When the memory device of installing according to an embodiment of the present, can provide size to dwindle more semiconductor device.In addition, because memory device according to an embodiment of the present can make with low cost, so the manufacturing cost of semiconductor device can be minimized.In addition, formed the chipset contoured beam antenna of those parts from the componentry to the antenna wherein integrated, can reduce cost thus.
Notice that the present invention can suitably combine with any other embodiment.
Embodiment 5
The method that is used to make the semiconductor device with memory device is according to an embodiment of the present described in embodiment 5.
The semiconductor device of present embodiment is described with reference to figure 10A and 10B.Figure 10 A is the schematic diagram of structure that the semiconductor device of present embodiment is shown, and Figure 10 B is its cross sectional view.
Shown in Figure 10 A, the antenna 402 that semiconductor device in the present embodiment comprises substrate 400, is arranged at the componentry 401 on the substrate 400 and is electrically connected with componentry 401.
Componentry 401 comprise a plurality of such as memory device element and have the function of the signal that processing receives from the outside.Antenna 402 has the function that sends the data in the semiconductor device.
In addition, shown in Figure 10 B, semiconductor device in the present embodiment comprises the element 404 that is arranged on the substrate 400, be arranged at interlayer film 403 on element 404 and the substrate 400, be arranged on the interlayer film 403 and as conductive layer 405, the conductive layer 406 that is electrically connected with element 404 of antenna 402 and the componentry 401 with the conductive layer 406 that is electrically connected with element 404.
In addition, the conductive layer 405 that plays a part antenna 402 is set in the layer identical with conductive layer 406 in the structure of Figure 10 B, but this is not restrictive example.Can also use wherein that dielectric film provides so that cladding element part and conductive layer 405 are set at the structure on this dielectric film with being separated after being provided with componentry 401.
And the semiconductor device of present embodiment is not limited to the structure of Figure 10 A and 10B.Another structure example of the semiconductor device of present embodiment is described with reference to figure 11A and 11B.Figure 11 A is the schematic diagram of another structure that the semiconductor device of present embodiment is shown, and Figure 11 B is its cross sectional view.
Shown in Figure 11 A, the antenna 702 that semiconductor device in the present embodiment comprises substrate 700, is arranged at the componentry 701 on the substrate 700 and is electrically connected with componentry 701.
With with the mode of the structural similarity of Figure 10 A and 10B, componentry 701 comprise a plurality of such as memory element element and have the function of the signal that processing receives from the outside.Antenna 702 has the function that sends the data in the semiconductor device.
In addition, shown in Figure 11 B, semiconductor device in the present embodiment comprises: substrate 700, be arranged at conductive layer 711 (as antenna 702) and resin 709 on the part of substrate 700, be arranged at the conducting particles 708 on the part of conductive layer 711, be arranged at the conductive layer 706 on the part of the part of resin 709 and conducting particles 708, be arranged at the componentry 701 on the conductive layer 706, and be arranged at the substrate 703 on the componentry 701.
The conductive layer that is provided with terminal part 710 and is arranged in the layer identical with conductive layer 706 in the structure of Figure 11 A and 11B is used as terminal part 710.In addition, be provided with the substrate 703 of componentry 701 and terminal part 710, and the substrate 700 that is provided with antenna 702 by attached so that form and being electrically connected of terminal part 710.
In the present embodiment, memory device according to an embodiment of the present can be used as the memory device in the componentry 401.When the memory device that uses according to an embodiment of the present, the semiconductor device with high reliability can be made with low cost.
When a plurality of componentries 401 or a plurality of componentry 701 were pre-formed on big substrate and are cut into separated portions then, componentry 401 or 701 can form with low cost.For in the substrate 400, substrate 700 and the substrate 703 that use in this case each, can use flexible substrate that polyethylene terephthalate (PET), Polyethylene Naphthalate (PEN), polyether sulfone (PES), acrylic compounds etc. form as plastic base.
Be contained in a plurality of transistors within componentry 401 or 701, memory device etc. and be not limited to be arranged in the identical layer, but can be arranged in a plurality of layers.In the time of in componentry 401 or 701 is set at a plurality of layers, use interlayer dielectric.For the material of interlayer dielectric, can use resin material such as epoxy resin or acrylic resin, for example polyimide resin the transmittance resin material, comprise compound-material such as the silicone compositions of silicone resin, comprise can be water-soluble homopolymers and the material or the inorganic material of copolymer that can be water-soluble.In addition, can also use the laminated construction of multiple above-mentioned material.Silicone compositions is corresponding to the material with Si-O-Si key.Siloxanes has the skeleton structure of the key of silicon (Si) and oxygen (O).As an alternative, the organic group that contains hydrogen (for example, alkyl or aromatic hydrocarbons) at least is used.The fluoro group can be contained in the organic group.Notice that interlayer dielectric can wait and form by CVD, sputter, SOG method, droplet discharging method, silk screen printing.
And, for the material of interlayer dielectric, the preferred parasitic capacitance of material of using to reduce to generate at interlayer with low-k.When parasitic capacitance reduces, then can realize the operation at a high speed and the reduction of energy consumption.
Conductive layer 405, conductive layer 406 and conductive layer 706 can use CVD, sputter, the printing method such as screen print process or intaglio process method for making, droplet discharging method, distributor method, galvanoplastic to wait and form.Conductive layer 405, conductive layer 406 and conductive layer 706 can form as the alloy material of its main component or the single layer structure or the laminated construction of compound-material with element that is selected from aluminium, titanium, silver, copper, gold, platinum, nickel, palladium, tantalum or molybdenum or any kind that comprises these elements.
For example, using silk screen printing to form in the situation of conductive layer 405, conductive layer 406 or conductive layer 706, conductive layer 711, conductive layer can wherein have several nm electrocondution slurry dissolved to the conducting particles of the particle size of tens μ m or that be scattered in the organic resin and forms by optionally printing.For conducting particles, can use the metallic of one or more kinds in silver, gold, copper, nickel, platinum, palladium, tantalum, molybdenum, the titanium etc., the minuteness particle of silver halide, the perhaps nano particle of Fen Saning.In addition, for the organic resin that is contained in the electrocondution slurry, can use one or more kinds in the organic resin that is selected from binding agent, solvent, dispersant and the coating member (coating member) that play a part metallic.Typically, can use organic resin such as epoxy resin or silicone resin.In addition, when forming conductive layer, cure preferably and after electrocondution slurry is extruded, carry out.For example, (for example, particle size is that conductive layer can obtain the mode of its curing by curing it with 150 ℃～300 ℃ temperature in the situation as the material of electrocondution slurry of 1nm～100nm) as the minuteness particle of its main component containing silver.Alternatively, can be used as minuteness particle with comprising scolder or lead-free solder minuteness particle as its main component.In this case, preferably use minuteness particle with 20 μ m or littler particle size.When scolder or lead-free solder were used, this type of conductive layer can form with low cost.
For example, when integrated circuit etc. is set on componentry 401 or 701, can will comprise transistor by the single layer structure of any kind in amorphous semiconductor, crystallite semiconductor (being also referred to as the microcrystal semiconductor), poly semiconductor, the organic semiconductor etc. or the active layer that laminated construction forms as each transistor that is contained in the componentry.In order to obtain to have the transistor of superperformance, the preferred use by using metallic element to come the active layer of crystallization or come the active layer of crystallization by laser radiation as catalyst.Alternatively, for active layer, can use by using SiH 4/ F 2Gas or SiH 4/ H 2The semiconductor layer that gas (argon gas) forms with plasma CVD is perhaps with the semiconductor layer of laser radiation.
In addition, being contained in these transistorlikes in componentry 401 or 701 can use by the crystalline semiconductor layer (low-temperature polycrystalline silicon layer) that obtains at crystallizing amorphous semiconductor layer under the temperature of 200 ℃～600 ℃ (being preferably 350 ℃～500 ℃) or the crystalline semiconductor layer (high temperature polysilicon layer) by crystallization acquisition under 600 ℃ or higher temperature and form.Note, when the high temperature polysilicon layer is formed on the substrate, preferably use quartz base plate because the poor heat resistance of glass substrate in some cases.
Preferably with hydrogen or halogen with 1 * 10 19Individual atom/cm 3～1 * 10 22Individual atom/cm 3Concentration, more electedly with 1 * 10 19Individual atom/cm 3～5 * 10 20Individual atom/cm 3Concentration be added into be contained in componentry 401 or 701 in transistorized active layers (particularly channel region).Thereby the active layer that can obtain to have few defects is not easy to crack in described active layer.
In addition, preferably provide stop such as the barrier film of alkali-metal pollutant in case be contained in componentry 401 or 701 in transistor or componentry 401 or 701.Thereby can provide does not have componentry 401 or 701 contaminated and that have higher reliability.Notice that silicon nitride film, silicon oxynitride film, oxygen silicon nitride membrane etc. can be used as barrier film.In addition, the thickness that is contained in transistorized each active layer within componentry 401 or 701 is 20nm～200nm, is preferably 40nm～170nm, more preferably is 45nm～55nm or 145nm～155nm, and will more preferably be 50nm or 150nm also.Thereby, even can provide wherein at the componentry 401 or 701 that is subjected to also being not easy under the crooked situation cracking.
In addition, preferably, the crystal that is contained in the transistorized active layer in being contained in componentry 401 or 701 is formed so that have the crystal boundary that extends along the direction that is parallel to carrier flow (direction of channel length).This active layer uses continuous wave laser, perhaps so that (being preferably the pulse laser that the frequency of 60MHz～100MHz) operates forms more than the 10MHz.
And this transistorlike that is contained in componentry 401 or 701 has preferably that 0.35V/dec is following (to be preferably the threshold lower swing (subthreshold swing) of 0.09V/dec～0.25V/dec), and 10cm 2The characteristic of/Vs or higher mobility.This class feature can be achieved when each active layer forms by the pulse laser that uses continuous wave laser or operate under 10MHz or higher frequency.
And the transistor that is contained in componentry 401 or 701 has 1MHz or higher on the level of ring oscillator, is preferably the frequency characteristic of 10MHz or higher (under 3～5V).Alternatively, being contained in transistors in componentry 401 or 701, to have each grid be 100kHz or higher, is preferably the frequency characteristic of 1MHz or higher (under 3～5V).
The substrate self that has formed componentry on it can be used, and this is not restrictive example.Figure 12 A and 12B show the example that has wherein used the substrate different with componentry substrate formed thereon.Figure 12 A and 12B show the another kind of structure of the semiconductor device that is used for making present embodiment and the schematic diagram of another kind of method.
Shown in Figure 12 A, formed thereon in the substrate 410 of componentry 411, the componentry 411 on substrate 410 is separated.In addition, shown in Figure 12 B, the componentry 411 that is separated can be attached to the substrate 413 that is different from substrate 410.Note,, for example can use flexible substrate etc. for substrate 413.
Any method in can be by the following method makes componentry 411 separate with substrate 410: wherein metal oxide film is arranged between substrate 410 with high-fire resistance and the componentry 411 and makes the metal oxide film crystallization make the method that componentry 411 is separated to make it to weaken; Wherein hydrogeneous amorphous silicon film is arranged between substrate 410 with high-fire resistance and the componentry 411 and and removes the method that amorphous silicon film makes that componentry 411 is separated by laser radiation or etching; The substrate 410 usefulness machinery that wherein is formed with the high-fire resistance of componentry 411 on it is removed or with solution or such as CF 3Gas come etching to remove to make the method that componentry 411 is separated; Or the like.
Alternatively, replace said method, with play a part separating layer (for example, use tungsten, molybdenum, titanium, tantalum or cobalt to form) metal film, perhaps (for example, using the laminated construction of tungsten oxide, molybdenum oxide, titanium oxide, tantalum oxide, cobalt oxide, metal film and metal oxide film to form) metal oxide film is arranged between substrate 410 and the componentry 411, and can componentry 411 and substrate 410 separated by using physical means.Alternatively, forming opening portion so that after exposing separating layer according to selecting, the part of separating layer is with such as halogen family fluoride (for example, ClF 3) etchant remove, and componentry 411 is physically separated with substrate 410.
In addition, adhesive that can the commodity in useization adhesive of epoxy resin-based adhesive (for example, such as) or resin additive attach to substrate 413 with the componentry 411 that is separated.
When componentry 411 is attached to substrate 413 and makes semiconductor device as described above the manufacturing, even the semiconductor device that then can provide thin, lightweight and when its is dropped, also be not easy to break.In addition, because flexible substrate is used as substrate 413,, substrate 413 can be achieved so can being attached to curved surface or irregular shape and various application.For example, shown in Figure 12 C, semiconductor device 414 according to an embodiment of the present can closely be attached to the curved surface of medicine bottle.And when substrate 410 was reused, semiconductor device can provide originally with lower one-tenth.
Notice that present embodiment can suitably combine with any other embodiment.
Embodiment 6
In embodiment 6, described and wherein used separating technology to make the situation of flexible semiconductor device.
The method that is used for making the semiconductor device of present embodiment is described to 13C with reference to figure 13A.Figure 13 A is the top view that the structure of the semiconductor device in the present embodiment is shown to 13C.
As shown in FIG. 13A, semiconductor device in the present embodiment comprises flexible protective layer 501, has the flexible protective layer 503 of antenna 504 and the componentry 502 that forms by separating technology.The antenna 504 that is formed on the protective layer 503 is electrically connected with componentry 502.Antenna 504 only is formed on the protective layer 503 in the structure shown in Figure 13 A, but this is not restrictive example.Can also antenna 504 be set for protective layer 501.In addition, when the barrier film that is formed by silicon nitride film etc. is formed between componentry 502 and protective layer 501 and 503, then under the situation of not polluting componentry 502, can provide to have the more semiconductor device of high reliability.
For the conductive layer that plays a part antenna 504, can use any materials described in embodiment 4.In addition, componentry 502 and antenna 504 are connected to each other, but this method is not restrictive example by carry out UV processing or ultrasonic waves for cleaning with anisotropic conducting film.Componentry 502 and antenna 504 can interconnect by the whole bag of tricks.
Shown in Figure 13 B, place the thickness of the componentry 502 between protective layer 501 and the protective layer 503 to be preferably 5 μ m or littler, more preferably be 0.1 μ m～3 μ m.In addition, when the thickness of stacked protective layer 501 and protective layer 503 was indicated by d, then the thickness of protective layer 501 and protective layer 503 was preferably (d/2) ± 30 μ m, more preferably was (d/2) ± 10 μ m.In addition, the thickness of protective layer 501 and protective layer 503 is preferably 10 μ m～200 μ m.In addition, the area of componentry 502 is 5mm * 5mm (25mm 2) or littler, be preferably 0.3mm * 0.3mm (0.09mm 2)～4mm * 4mm (16mm 2).
Because protective layer 501 and protective layer 503 uses organic resin materials to form, thereby protective layer 501 and protective layer 503 have high bending.In addition, the componentry 502 that forms by separating technology self has higher bending resistance than single crystal semiconductor.Because componentry 502 can closely be attached to protective layer 501 and protective layer 502 makes between them without any the gap, so the semiconductor device of finishing self has high bending.The componentry 502 that is surrounded by protective layer 501 and protective layer 503 can be set on another object surfaces or within, perhaps can be embedded in the paper.
Describe below wherein and will attach to the situation of substrate by the componentry that separating technology forms with curved surface.
Shown in Figure 13 C, a transistor that is selected from the componentry that forms by separating technology is a line style on the direction (as shown by arrows) that electric current flows.That is to say that drain electrode 505, gate electrode 507 and source electrode 506 are positioned on the straight line.In addition, the direction that flows of electric current and the direction of wherein substrate embowment are arranged to orthogonal.By this layout, even making curved substrate during embowment, stress influence also is little, and the variation that is contained in the characteristics of transistor in the componentry also can be inhibited.
In addition, when the ratio such as the area of the active region (silicon island part) of transistorized active element and the gross area of substrate is 1%～50% (being preferably 1%～30%), then can prevent by the damage due to the stress to element.
Be not provided with therein in the zone of active element, mainly be provided with substrate insulating material, layer insulation membrane material and wiring material.The ratio of area and the gross area of substrate that is different from the zone of active region (for example transistor) is 60% or bigger.Thereby can provide can be by easy semiconductor device crooked and that have high integration.And, formed the chipset contoured beam antenna of those parts from the componentry to the antenna wherein integrated, cost is minimized.
When the semiconductor device with memory device according to an embodiment of the present uses when making as the method for making the semiconductor device in the present embodiment described above, semiconductor device can be manufactured in or even curved surface on and the range of application of semiconductor device can become wider.
Notice that present embodiment can suitably combine with any other embodiment.
Embodiment 7
Any application example of semiconductor device in the memory device with the foregoing description has been described in embodiment 7.
The application example of semiconductor device with arbitrary memory device of the foregoing description is described to 14F with reference to figure 14A.Figure 14 A is the schematic diagram that the use-case of semiconductor device according to an embodiment of the present is shown to 14F.
As Figure 14 A to shown in the 14F, semiconductor device can be widely used and can be by offering, for example, bill, coin, security, blank bond, certificate (for example, driving license or resident's card, referring to Figure 14 A), perhaps (for example such as the object of the container that is used to pack, wrapping paper or Packaging Bottle, referring to Figure 14 C), recording medium (for example, DVD or video tape, referring to Figure 14 B), the vehicles (for example, bicycle is referring to Figure 14 D), personal belongings (for example, sack or glasses), food, plant, animal, human body, clothes, daily necessities or electronic equipment (for example, liquid crystal display, the EL display device, television set or mobile phone) or the mode of the shipping label (referring to Figure 14 E and 14F) of object use.
Semiconductor device 600 according to an embodiment of the present attaches to the surface by being installed in the printed board, and perhaps the mode that embeds wherein fixes in object.For example, semiconductor device by in the paper that embeds books or the mode in the organic resin of packing fix in object.Because according to an embodiment of the present semiconductor device 600 has been realized reducing of size, thickness and weight, even thereby after will semiconductor device 600 according to an embodiment of the present being fixed in object the attractive design of object itself do not suffer damage yet.In addition, when semiconductor device 600 that will be according to an embodiment of the present offers bill, coin, security, blank bond, certificate etc., then can provide authentication function, and utilize this authentication function can prevent forgery them.In addition, when semiconductor device that will be according to an embodiment of the present attached to the container that is used to pack, recording medium, personal belongings, food, clothes, daily necessities, electronic device etc., the system such such as check system just can be used effectively.In addition, when general's semiconductor device according to an embodiment of the present attached to the vehicles, the fail safe of antitheft grade can be improved.
When the semiconductor device with memory device according to an embodiment of the present was used in the present embodiment described application purpose by this way, the data that then can be used in exchange message were kept accurate value.Therefore, the authenticity of object or fail safe can be improved.
Example 1
Example 1 will with reference to figure 15A to 15E, Figure 16 A to 16E, Figure 17 A to 17E, Figure 18 A to 18C and Figure 19 A the manufacture method of the semiconductor device that comprises anti-fusing N-type semiconductor N memory device is described to 19D.At this example that manufacturing wherein is arranged at logical circuit part 1550, semiconductor memory circuit part 1552 and antenna part 1554 semiconductor device on the same substrate is described.The circuit that comprises thin-film transistor is integrated in the logical circuit part 1550.Semiconductor memory circuit part 1552 comprises the memory cell that contains a plurality of thin-film transistors and anti-fusing type memory element.Note, for convenience's sake, illustrate in the drawings two thin-film transistors being contained in the logical circuit part 1550, be contained in a thin-film transistor and a memory element in the semiconductor memory circuit part 1552 and be contained in a capacitor in the antenna part and the cross sectional view of a thin-film transistor.Note, all illustrate so that clearly describe cross section structure with the ratio of exaggeration at each element shown in the cross sectional view of example 1.
Notice that the word in example 1 " semiconductor device " means the device that can utilize semiconductor property to operate.
At first, will be formed on the supporting substrate 1501 as the metal level 1502 of separating layer.Glass substrate is used as supporting substrate 1501.For metal level 1502, use tungsten layer, tungsten nitride layer or the molybdenum layer of the thickness that obtains by sputtering method with 30nm～200nm.
Then, the surface of metal oxide layer 1502 is to form metal oxide layer.Metal oxide layer can be by coming the surface of metal oxide layer 1502 with pure water or Ozone Water, perhaps come the surface of metal oxide layer 1502 with oxygen plasma and form.Alternatively, metal oxide layer can form by heating in oxygen containing environment.In addition alternatively, metal oxide layer can also form in the back in the step that is used as the insulating barrier of the separating layer of formation on metal level 1502 and form.For example, when forming as the silicon oxide layer of insulating barrier or silicon oxynitride layer by plasma CVD method, metal level 1502 surperficial oxidized makes to form metal oxide layer.Note, metal oxide layer is not shown in the drawings.In addition, the base insulating layer such as silicon oxide layer or silicon nitride layer can be arranged between separating layer (being metal level 1502) and the substrate at this.In the laminated construction of example 1, the silicon oxynitride layer with thickness of 100nm is used as base insulating layer, and the tungsten layer with thickness of 30nm is used as metal level, and the silicon oxide layer with thickness of 200nm is used as first insulating barrier (Figure 15 A).
Then, on metal level 1502, form first insulating barrier 1503.Insulating barrier such as silicon oxide layer, silicon nitride layer or silicon oxynitride layer is formed first insulating barrier 1503.As the example of first insulating barrier 1503, can provide and wherein pile up by using SiH 4, NH 3And N 2O is as the silicon oxynitride layer of the thickness with 50nm～100nm of the plasma CVD method formation of reacting gas and by using SiH 4And N 2O is as the double-decker of the silicon oxynitride layer of the thickness with 100nm～150nm of the plasma CVD method formation of reacting gas.When first insulating barrier 1503 has laminated construction,, be preferably formed silicon nitride layer or silicon oxynitride layer with 10nm or littler thickness for one deck at least of first insulating barrier 1503.Alternatively, can utilize the three-decker of wherein piling up silicon oxynitride layer, silicon oxynitride layer and silicon nitride layer in succession.Though first insulating barrier 1503 is as base insulating layer, then do not provide this layer if not necessity especially.In example 1, the laminated construction of the silicon oxynitride layer that silicon oxynitride layer that 50nm is thick and 100nm are thick is as first insulating barrier (Figure 15 B).
Then, semiconductor layer 1570 is formed on first insulating barrier 1503.Semiconductor layer 1570 is by following formation: the semiconductor layer with non crystalline structure forms by CVD method or sputtering method such as LPCVD method or plasma CVD method, and then by crystallization obtaining crystalline semiconductor layer, and crystalline semiconductor layer optionally is etched into desirable shape.For crystallization method, can use the laser crystallization method, use RTA or annealing furnace the thermal crystallisation method, use the crystallization method of the metallic element (for example nickel) that promotes crystallization etc.Notice that when semiconductor layer formed by plasma CVD method, first insulating barrier 1503 can form continuously with the semiconductor layer with non crystalline structure under the situation that is not exposed to air.Semiconductor layer is formed into 25nm～80nm and (is preferably the thickness of 30nm～70nm).Though there is no particular limitation to the material of semiconductor layer, preferred silicon, the SiGe etc. of using.
Alternatively, handle, can use continuous wave laser for the crystallization of semiconductor layer with non crystalline structure.In order in the crystallization of semiconductor layer, to obtain crystal with bulky grain size with non crystalline structure, second to the 4th harmonic wave of the solid-state laser that preferred employing can continuous wave oscillation.As typical example, can use Nd:YVO 4The second harmonic (532nm) or the third harmonic (355nm) of laser (first-harmonic is 1064nm).In using the situation of continuous-wave laser, by nonlinear optical element with by continuous wave YVO with 10W output 4The laser beam that laser is launched converts harmonic wave to.Harmonic wave can also pass through YVO 4Crystal and nonlinear optical element are positioned in the resonant cavity and obtain.Preferably make laser beam on irradiating surface, form the laser beam of rectangle or elliptical shape and then this laser beam is delivered to object by optical system.At this moment, need about 0.01MW/cm 2～100MW/cm 2(preferably, 0.1MW/cm 2～10MW/cm 2) energy density.Then, can move semiconductor layer with the speed of about 10cm/sec～2000cm/sec relative to laser beam is shone so that make it.In example 1, the amorphous silicon with thickness of 66nm is stacked on first insulating barrier and with laser and shines so that its crystallization (Figure 15 C).
Note,, then a spot of impurity element (boron or phosphorus) is added into semiconductor layer so that the threshold value of the thin-film transistor that control will be finished in the back if need.In example 1, boron adds by the ion doping method, in the method diborane (B 2H 6) do not having under the situation of mass separation by plasma exciatiaon (Figure 15 D).
Semiconductor layer 1570 is selectively etched the semiconductor layer 1571 to 1576 (Figure 15 E) that has desirable shape with formation.In addition, can be in addition with impurity element with low concentration be added into as the semiconductor layer in the zone of n channel transistor to form channel formation region therein.In example 1, boron is added, and is being covered (Figure 16 A) as the semiconductor layer in the zone of p channel transistor by Etching mask 1577.
Then, in the lip-deep oxidation film of removing with the etchant that contains hydrofluoric acid at semiconductor layer, clean the surface of semiconductor layer.Then, form second insulating barrier 1578 that covers semiconductor layer.Forming second insulating barrier 1578 by CVD method or sputtering method makes it reach the thickness of 1nm～200nm.Preferably, formation comprises that thickness is the single layer structure or the laminated construction of the insulating barrier that contains silicon of 10nm～50nm, and uses the plasma by microwave-excitation to carry out surfaces nitrided processing then.Second insulating barrier 1578 is as the gate insulator (GI film) of the thin-film transistor that forms in the back.In example 1, the silicon oxynitride layer with thickness of 10nm is formed second insulating barrier 1578 (Figure 16 B).
In addition, play a part conductor, impurity element (boron or phosphorus) is added into semiconductor layer with high concentration in order to make the regional inner semiconductor layer (1574,1575) that will become capacitor in the back.In this case, preferably mix as the zone of the auxiliary capacitor in the memory cell with the impurity element of giving p type conductivity.Note, can cover (Figure 16 C) with Etching mask 1579 to 1581 with the regional different zone that is used as capacitor.
Then, gate electrode 1504, gate electrode 1505, gate electrode 1506, gate electrode 1507, electrode for capacitors 1508 and be formed on second insulating barrier as first electrode 1509 of the bottom electrode of memory element.The conductive layer of the thickness with 100nm～500nm that obtains by sputtering method is selectively etched and is processed into desirable shape, thereby has obtained gate electrode 1504 to 1507, electrode for capacitors 1508 and first electrode 1509.
Material for the gate electrode 1504 to 1507 and first electrode 1509 can use the material such as tungsten, titanium, aluminium, nickel, chromium, molybdenum, tantalum, cobalt, zirconium, vanadium, palladium, hafnium, platinum or iron; Be selected from the single layer structure or the laminated construction of the material of the alloy of these materials or compound.Preferably be used with the material that forms silicide with pasc reaction.Note, preferably with the gate electrode of high-melting point metal as thin-film transistor.Especially, can provide tungsten or molybdenum.Each all has in the situation of laminated construction at gate electrode 1504 to 1507 and first electrode 1509, can use above-mentioned material to form as the material layer on upper strata, and can be the polysilicon layer that has wherein added such as the impurity element of phosphorus as the material layer of the lower floor on gate insulator one side.In addition, owing to the electrode that first electrode 1509 is used in the anti-fusing that contacts with amorphous silicon, thereby the material of preferred use and pasc reaction.In example 1, used the laminated construction (Figure 16 D) of the thick tungsten of thick tantalum nitride of 30nm and 370nm.
Then, form Etching mask 1582 to 1584 so that make its covering will become the zone of p channel transistor and the zone that will become capacitor, and use gate electrode 1505,1506 and 1507 as mask, impurity element is added in the semiconductor layer in the zone that will become the n channel transistor, thereby forms the low concentration impurity district.For impurity element, can use the impurity element of giving n type conductivity or give the impurity element of p type conductivity.For n type impurity element, can use phosphorus (P), arsenic (As) etc.In example 1, phosphorus is added within the semiconductor layer in the zone that will become the n channel transistor so that make it to contain 1 * 10 15/ cm 3～1 * 10 19/ cm 3The phosphorus of concentration, thereby form n type impurity range (Figure 16 E).
Then, remove Etching mask, and form Etching mask 1585 to 1587 then so that make its covering will become the semiconductor layer of n channel transistor and the zone that will become capacitor, and use gate electrode 1504 as mask, impurity element is added within the semiconductor layer that will become the p channel transistor, thereby forms p type impurity range.For the impurity element of giving p type conductivity, can use boron (B), aluminium (Al), gallium (Ga) etc.At this, boron (B) is added within the semiconductor layer in the zone that will become the p channel transistor so that make it to contain 1 * 10 19/ cm 3～1 * 10 20/ cm 3The boron of concentration, thereby can form p type impurity range.As a result, forming channel formation region 1516 and a pair of p type impurity range 1514 in self aligned mode as in the semiconductor layer of p channel transistor.P type impurity range 1514 is as source region or drain region.In a similar manner, in the semiconductor layer that will become capacitor, form p type impurity range 1515,1517 (Figure 17 A) in self aligned mode with different impurity concentrations.
Then, on the side surface of gate electrode 1504 to 1507, form side wall insulating layer 1510 and on the side surface of first electrode 1509, form side wall insulating layer 1511.Side wall insulating layer 1510 and 1511 formation method are as follows: at first, by formation such as plasma CVD method, sputtering method the 3rd insulating barrier 1588 make the layer of its nitride with the oxide that contains silicon, silicon or silicon or contain the single layer structure of layer of organic material (for example organic resin) or laminated construction so that cover second insulating barrier, gate electrode 1504 to 1507, electrode for capacitors 1508 and first electrode 1509.In example 1, used the laminated construction (Figure 17 B) of the thick LTO of thick silicon oxynitride layer of 100nm and 200nm.Then, the anisotropic etching of mainly carrying out on vertical direction by etching wherein comes optionally etching the 3rd insulating barrier 1588, forms insulating barrier (side wall insulating layer 1510 and side wall insulating layer 1511) thus so that make it and the contacts side surfaces of gate electrode 1504 to 1507, electrode for capacitors 1508 and first electrode 1509.Notice that the part of second insulating barrier 1578 is etched removing when side wall insulating layer 1510 forms.This part of second insulating barrier 1578 is removed, and makes gate insulator 1512 be formed under each and the side wall insulating layer 1510 in the gate electrode 1504 to 1507.In addition, this part of second insulating barrier is removed, and makes insulating barrier 1513 be formed under electrode for capacitors 1508, first electrode 1509 and the side wall insulating layer 1511 (Figure 17 C).
Then, form Etching mask 1589 to 1591 so that make it cover semiconductor layer in the zone that will become the p channel transistor, and use gate electrode 1505,1506 and 1507 and side wall insulating layer 1510 impurity element is added within the semiconductor layer in the zone that will become the n channel transistor as mask, thereby form the high concentration impurities district.Etching mask is removed after having added impurity element.In example 1, phosphorus (P) is added within the semiconductor layer in the zone that will become the n channel transistor so that make it to contain 1 * 10 19/ cm 3～1 * 10 20/ cm 3The phosphorus of concentration, thereby can form n type high concentration impurities district and n type impurity range.As a result, within as each semiconductor layer in the zone of n channel transistor, form channel formation region 1520, a pair of low concentration impurity district 1519 and a pair of high concentration impurities district 1518 as source region and drain region as the LDD district in self aligned mode.Notice that the low concentration impurity district 1519 that is used as the LDD district is formed on (Figure 17 D) under the side wall insulating layer 1510.
Note, described LDD district wherein at this and be formed in the semiconductor layer that is included in the n channel thin-film transistor and the LDD district is not formed on structure in the semiconductor layer that is included in the p channel thin-film transistor, but this is not restrictive example.The LDD district can be formed at and be included in n channel thin-film transistor and the p channel thin-film transistor semiconductor layer in the two.Especially, when gate insulator (GI film) is when approaching, particularly,, then preferably adopt the LDD structure so that improve the withstand voltage of p channel transistor when the thickness of gate insulator is 10nm or more hour.
Then, after having formed the 4th hydrogeneous insulating barrier 1522, carry out the hydrogenation treatment and the activation processing of adding the impurity element within the semiconductor layer to by sputtering method, LPCVD method, plasma CVD method etc.Heat treatment in stove (under 300 ℃～550 ℃ temperature 1～12 hour) or use the RTA method of lamp source to be used in the hydrogenation treatment and the activation processing of impurity element.For example, will be used for the 4th hydrogeneous insulating barrier 1522 by the silicon oxynitride layer that plasma CVD method obtains.At this, the thickness of the 4th hydrogeneous insulating barrier 1522 is set to 50nm～200nm.In addition, come in the situation of crystallization semiconductor layer at the metallic element (being typically nickel) that uses the promotion crystallization, air-breathing (gettering) that reduce the nickel in the channel formation region can also carry out in activation.Notice that the 4th hydrogeneous insulating barrier 1522 is ground floors of interlayer insulating film.In example 1, the silicon oxynitride with thickness of 50nm is stacked as the 4th insulating barrier and stands 4 hours the heat treatment (Figure 17 E) as the hydrogenation treatment and the activation processing of impurity element under 550 ℃.
Then, wait the 5th insulating barrier 1523 that forms as the second layer of interlayer insulating film by sputtering method, LPCVD method, plasma CVD method.The individual layer or the insulating barrier in the lamination that are in such as silicon oxide layer, silicon nitride layer and/or silicon oxynitride layer are used as the 5th insulating barrier 1523.At this, the thickness of the 5th insulating barrier 1523 is 300nm～800nm.In example 1, the laminated construction of the silicon oxynitride that silicon oxynitride that 100nm is thick and 600nm are thick is formed the 5th insulating barrier 1523 and has stood 1 hour heat treatment (Figure 18 A) under 410 ℃.
Then, on the 5th insulating barrier 1523, form Etching mask and optionally etching the 4th insulating barrier 1522 and the 5th insulating barrier 1523, thereby form first opening 1521 that reaches first electrode 1509.Etching mask is removed after etching.The diameter of first opening 1521 can be about 1 μ m～6 μ m.In example 1, the diameter of first opening 1521 is 2 μ m (Figure 18 B).
Then, use sputtering method, LPCVD method, plasma CVD method wait the layer that forms as memory element, that is, and and the lamination of silicon oxynitride layer and amorphous silicon layer.In example 1, the silicon oxynitride layer that forms the amorphous silicon layer of thickness in order and have the thickness of 6nm by plasma CVD method with 15nm.Then, form Etching mask and optionally etching method for amorphous silicon layer and silicon oxynitride layer, thereby form and the overlapping amorphous silicon layer of first opening 1521 and the lamination 1524 of silicon oxynitride layer.The lamination 1524 of amorphous silicon layer and silicon oxynitride layer is as the erosion resistant layer of memory element.Etching mask is removed (Figure 18 C) after etching.
Then, form Etching mask and optionally etching the 4th insulating barrier 1522 and the 5th insulating barrier 1523, thus form the contact hole 1592a that reaches semiconductor layer to 1592j, reach gate electrode contact hole 1593a to the 1593e and second opening 1594 that reaches first electrode 1509.Etching mask is removed (Figure 19 A) after etching.
Then, on the surface that semiconductor layer exposes and the oxidation film that on the surface that first electrode 1509 exposes, forms remove with the etchant that contains hydrofluoric acid, and simultaneously, clean the exposed surface of semiconductor layer and the exposed surface of first electrode 1509.
Then, conductive layer forms with the source electrode of the top electrode that forms memory element, thin-film transistor and drain electrode etc. by sputtering method, and analog.This conductive layer is by the material such as tungsten, titanium, aluminium, nickel, chromium, molybdenum, tantalum, cobalt, zirconium, vanadium, palladium, hafnium, platinum or iron, and perhaps the individual layer of their alloy or compound or lamination form.In addition, this conductive layer also is used for the source electrode and the drain electrode of thin-film transistor.Therefore, the preferred material that has with the relative low contact resistance of the semiconductor layer of thin-film transistor that uses.For example, use titanium layer, the aluminium lamination that contains Trace Silicon and titanium layer three-decker or titanium layer, contain the three-decker of the aluminium alloy layer and the titanium layer of nickel and carbon.In example 1, used the three-decker of the thick titanium layer of thick aluminum layer of the thick titanium layer of 100nm, 350nm and 100nm.In addition, example 1 shows the material of the bottom electrode that wherein tungsten layer is used as memory element and the example that titanium layer is used as the material of top electrode.But material is not subjected to special restriction as long as the state that they can make resistance elements is transformed into low resistance state and identical materials can be used for the top electrode and the bottom electrode of memory element from high resistance state.When using identical materials to form the bottom electrode of memory element and top electrode, then form described bottom electrode and top electrode and they are had be selected from such as the material of the material of tungsten, titanium, aluminium, nickel, chromium, molybdenum, tantalum, cobalt, zirconium, vanadium, palladium, hafnium, platinum or iron, the single layer structure of their alloy material or compound-material or laminated construction.
Then, form Etching mask, and optionally the etching conductive layer is to form each conductive layer that all is used as source electrode or drain electrode 1525, conductive layer 1526, conductive layer 1527, conductive layer 1528, conductive layer 1531, conductive layer 1532, wiring 1529 with the transistorized bit line that elects, wiring 1530 as word line, each all is used as the wiring 1535 of grid lead wiring, wiring 1536, wiring 1537, second electrode 1540 and the third electrode 1541 of semiconductor memory circuit part, each all is used as the wiring 1533 and the wiring 1534 of electrode of the capacitor of antenna part, and the 4th electrode 1542 of antenna part.Second electrode 1540 and first opening 1521 are overlapping and as the top electrode of memory element, and are electrically connected with semiconductor layer 1574 as a terminal of the electrode of auxiliary capacitor.In addition, third electrode 1541 is overlapping to be electrically connected with first electrode 1509 with second opening 1594.Notice that the 4th electrode 1542 is electrically connected with the thin-film transistor of antenna part and power unit, although at this this connection is not shown.Then, Etching mask is removed (Figure 19 B) after etching.
In example 1, the thin-film transistor of logical circuit part 1550, be formed on the same substrate as the thin-film transistor of the transistorized thin-film transistor 1558 of selection, auxiliary capacitor 1559, memory element 1560 and the antenna part 1554 of semiconductor memory circuit part 1552.In example 1, show the p channel transistor and the n channel transistor that are arranged in the logical circuit part 1550, be arranged at thin-film transistor 1558, auxiliary capacitor 1559, memory element 1560 in the semiconductor memory circuit part 1552, be arranged at the capacitor in the antenna part 1554 and the cross sectional view of n channel transistor.Notice that the present invention is not limited to this example, and the thin-film transistor that is arranged in the semiconductor memory circuit part 1552 can be the p channel thin-film transistor.In addition, the p channel thin-film transistor can be arranged in the antenna part 1554.At this, show a n channel thin-film transistor for convenience's sake.
Then, form the 6th insulating barrier 1543 with the thin-film transistor of covering logic circuit part 1550, the thin-film transistor of semiconductor memory circuit part 1552 and the thin-film transistor of memory element and antenna part 1554.The insulating barrier that contains the insulating barrier of silica or use organic resin to form can be used as the 6th insulating barrier 1543.The preferred insulating barrier that contains silica that uses is to improve the reliability of semiconductor device.Alternatively, the preferred insulating barrier that contains organic resin that forms by coating process that uses is because the 6th insulating barrier 1543 preferably has the surface of complanation in the situation that forms the antenna that the back will form with silk screen printing.The material that is used to form the 6th insulating barrier 1543 can suitably be selected by those skilled in the art.In addition, can form antenna that the back will form so that it is reached and logical circuit part 1550 and semiconductor memory circuit part 1552 overlapping areas.In this case, the 6th insulating barrier 1543 also plays a part to be used for the interlayer insulating film with the antenna insulation.Have in round-shaped (for example, loop aerial) or the spiral-shaped situation at antenna, one of two ends of antenna are drawn by the wiring of lower floor and are connect; Thereby it is preferred that the 6th insulating barrier 1543 is provided.But, using microwave method and antenna (for example to have rectilinear form, dipole antenna), in the situation of flat shape (for example, paster antenna) etc., the antenna that the back will form can be arranged to make it not overlap with logical circuit part and semiconductor memory circuit; Thereby, the 6th insulating barrier 1543 might not be provided.
Then, form Etching mask, and etching the 6th insulating barrier 1543 optionally, thereby the 4th opening 1596 that reaches the 3rd opening 1595 of third electrode 1541 and reach the 4th electrode 1542 formed.Etching mask is removed (Figure 19 C) after etching.
Then, on the 6th insulating barrier 1543, form metal level.For metal level, can use the individual layer or the lamination that are selected from Ti, Ni and/or Au.Then, form Etching mask, and etch metal layers optionally, thereby be formed for the lead-in wire wiring 1544 of first electrode 1509 and the basalis 1545 that is formed for antenna.Notice that lead-in wire wiring 1544 and basalis 1545 can not use the sputtering method of Etching mask optionally to form by using metal mask at this yet.When providing when being used for the basalis 1545 of antenna, can be guaranteed with the large contact surface of antenna is long-pending.In addition, might not form lead-in wire wiring 1544, this depends on the layout of circuit design.Lead-in wire wiring 1544 is connected with the ground power supply as negative electrode.
Then, on the basalis 1545 that is used for antenna, form antenna 1546.Antenna 1546 can form and be selectively etched into the such method of desirable shape then by sputtering method and form by the metal level of wherein Al, Ag etc.Alternatively, antenna 1546 can form by silk screen printing.Silk screen printing refers to wherein uses the rubber, plastics or the steel edge that are called as scraping brushing device (squeegee) that China ink or slurry are transferred to the method for the goods on the opposing face that is arranged in sieve plate, and wherein said ink or slurry are provided in predetermined figure and are formed on the sieve plate that such mode forms by the suprabasil photosensitive resin made from wire netting or macromolecular compound fleece.Silk screen printing has the advantage (Figure 19 D) that the formation of the figure on big relatively area is realized with low cost.
In example 1, the thin-film transistor and the memory element of the thin-film transistor of logical circuit part 1550 and semiconductor memory circuit part 1552, and the thin-film transistor of antenna part 1554 and antenna are formed on the same substrate.
Then, remove metal level 1502 and supporting substrate 1501 by separation.Separation can betide metal oxide layer inside, between first insulating barrier 1503 and metal oxide layer at the interface, perhaps between metal oxide layer and metal level 1502 at the interface, make it possible to relatively little power will be on first insulating barrier 1503 and to separate with supporting substrate 1501 as the part of semiconductor device.When metal level 1502 and supporting substrate 1501 are removed, fixing base can be attached to the side that provides antenna.
Then, a plate that will wherein form a plurality of semiconductor device by cutting, scribing etc. is divided into a plurality of semiconductor device.In addition, by using the method for wherein picking up and isolate each semiconductor device, then this partiting step is not necessary.
Then, semiconductor device is fixed in the plate substrate.For the plate substrate, can use plastics, paper, prepreg, ceramic wafer etc.Can stationary semiconductor devices so that it is placed between two plate substrates, perhaps can semiconductor device be fixed in a plate substrate with adhesive phase.For adhesive phase, can use the various curable adhesive of adhesive, resinoid or the Photocurable adhesive (for example ultraviolet light curing adhesive) that solidify such as reactable, perhaps anaerobic adhesive.In addition, when the formation of paper, arrange semiconductor device, thereby semiconductor device can be provided in the inside of a paper.
The memory of the semiconductor device that forms by above step is made of semiconductor storage unit according to an embodiment of the present.According to an embodiment of the present, memory element 1560 directly is stacked on the auxiliary capacitor 1559, and wherein first electrode 1509 reduces area occupied thus as the public electrode of auxiliary capacitor 1559 and memory element 1560.The semiconductor device that comprises semiconductor storage unit according to an embodiment of the present can reduced size.In addition, logical circuit part 1550, semiconductor memory circuit part 1552 and antenna part 1554 are formed on the same substrate, can write or reduce operation improperly during sense data thus.
Example 2
In example 2,, the difference of writing yield based on the polarity of the auxiliary capacitor with MOS structure has been described with reference to Figure 20 for memory element according to an embodiment of the present.
N type auxiliary capacitor is called as " A structure ", and P type auxiliary capacitor is called as " B structure ".To put on each memory element for writing required voltage (approximately 8V), and obtained write-once write successfully percentage as " writing yield ".The capacitance of auxiliary capacitor " A structure " and " B structure " is respectively 1pF and 0.4pF.Comparative result is illustrated among Figure 20.
According to Figure 20, the yield of writing of " A structure " is about 90%, and the yield of writing of " B structure " then is about 100%.Therefore, " B structure " write the yield of writing that yield is higher than " A structure ", although the auxiliary capacitor value of " B structure " is lower than the auxiliary capacitor value of " A structure ".Therefore, " A structure " is preferred to the present invention.
The application is based on submitting the Japanese patent application No.2008-241792 of Japan Patent office on September 19th, 2008, and mode by reference is incorporated into this in full with this application in view of the above.

Claims (26)

1. semiconductor device that comprises memory cell, described memory cell comprises:
Transistor, described transistorized grid is electrically connected with word line, and in described transistorized source electrode and the drain electrode one is electrically connected with bit line;
Memory element, first electrode of described memory element is electrically connected with in described transistorized described source electrode and the described drain electrode another; And
Capacitor, first electrode of described capacitor is electrically connected with described another in described transistorized described source electrode and the described drain electrode, and second electrode of described capacitor is electrically connected with second electrode of described memory element,
Wherein:
Described second electrode of described second electrode of described memory element and described capacitor is formed by same metal film;
Described first electrode of described capacitor is formed by the semiconductor film with impurity; And
The described metal film of described second electrode that plays a part described second electrode of described memory element and described capacitor is overlapping with the described semiconductor film of described first electrode that plays a part described capacitor.
2. semiconductor device according to claim 1, wherein said transistorized active layer comprises polysilicon film or amorphous silicon film with the described semiconductor film that plays a part described first electrode of described capacitor,
Wherein said transistorized gate insulating film and comprise inorganic material at described first electrode of described capacitor and the dielectric film between described second electrode, and
Wherein said transistorized described grid comprises metal film.
3. semiconductor device according to claim 1, described first electrode of wherein said memory element and the third electrode of described capacitor are formed by same metal film;
The described metal film of described third electrode that plays a part described first electrode of described memory element and described capacitor is overlapping with the described metal film of described second electrode of described second electrode that plays a part described memory element and described capacitor.
4. semiconductor device according to claim 1, the described metal film that wherein plays a part described second electrode of described second electrode of described memory element and described capacitor comprises tungsten.
5. semiconductor device according to claim 1, the described impurity that wherein is contained in the described semiconductor film is the impurity of giving p type conductivity.
6. semiconductor device according to claim 1, wherein said memory cell is formed on the flexible substrate.
7. semiconductor device according to claim 1 also comprises antenna.
8. semiconductor device that comprises memory cell, described memory cell comprises:
Transistor, described transistorized grid is electrically connected with word line, and in described transistorized source electrode and the drain electrode one is electrically connected with bit line;
Memory element, first electrode of described memory element is electrically connected with in described transistorized described source electrode and the described drain electrode another; And
Capacitor, first electrode of described capacitor is electrically connected with described another in described transistorized described source electrode and the described drain electrode, and second electrode of described capacitor is electrically connected with second electrode of described memory element,
Wherein:
Described second electrode of described memory element and described second electrode of described capacitor are formed by the first identical metal film;
Described first electrode of described capacitor is formed by second metal film; And
Described first metal film of described second electrode that plays a part described second electrode of described memory element and described capacitor is overlapping with described second metal film of described first electrode that plays a part described capacitor.
9. semiconductor device according to claim 8, wherein said transistorized active layer comprises polysilicon film or amorphous silicon film,
Wherein said transistorized gate insulating film and comprise inorganic material at described first electrode of described capacitor and the dielectric film between described second electrode, and
Wherein said transistorized described grid comprises metal film.
10. semiconductor device according to claim 8, described first electrode of wherein said memory element and the third electrode of described capacitor are formed by the 3rd identical metal film;
Described the 3rd metal film of described third electrode that plays a part described first electrode of described memory element and described capacitor is overlapping with described first metal film of described second electrode of described second electrode that plays a part described memory element and described capacitor.
11. semiconductor device according to claim 8, described first metal film that wherein plays a part described second electrode of described second electrode of described memory element and described capacitor comprises tungsten.
12. semiconductor device according to claim 8, wherein said memory cell is formed on the flexible substrate.
13. semiconductor device according to claim 8 also comprises antenna.
14. a semiconductor device that comprises memory cell, described memory cell comprises:
Transistor, described transistorized grid is electrically connected with word line, and in described transistorized source electrode and the drain electrode one is electrically connected with bit line;
Memory element, first electrode of described memory element is electrically connected with in described transistorized described source electrode and the described drain electrode another; And
Capacitor, first electrode of described capacitor is electrically connected with described another in described transistorized described source electrode and the described drain electrode, and second electrode of described capacitor is electrically connected with second electrode of described memory element,
Wherein:
Described second electrode of described second electrode of described memory element and described capacitor is formed by same metal film;
Described first electrode of described capacitor is formed by first semiconductor film with impurity;
The described metal film of described second electrode that plays a part described second electrode of described memory element and described capacitor is overlapping with described first semiconductor film of described first electrode that plays a part described capacitor; And
Described memory element comprises described first electrode that is arranged in described memory element and second semiconductor film between described second electrode.
15. semiconductor device according to claim 14, wherein said transistorized active layer comprises polysilicon film or amorphous silicon film with described first semiconductor film that plays a part described first electrode of described capacitor,
Wherein said transistorized gate insulating film and comprise inorganic material at described first electrode of described capacitor and the dielectric film between described second electrode, and
Wherein said transistorized described grid comprises metal film.
16. semiconductor device according to claim 14, described first electrode of wherein said memory element and the third electrode of described capacitor are formed by same metal film;
The described metal film of described third electrode that plays a part described first electrode of described memory element and described capacitor is overlapping with the described metal film of described second electrode of described second electrode that plays a part described memory element and described capacitor.
17. semiconductor device according to claim 14, the described metal film that wherein plays a part described second electrode of described second electrode of described memory element and described capacitor comprises tungsten.
18. semiconductor device according to claim 14, the described impurity that wherein is contained in described first semiconductor film is the impurity of giving p type conductivity.
19. semiconductor device according to claim 14, wherein said memory cell is formed on the flexible substrate.
20. semiconductor device according to claim 14 also comprises antenna.
21. a semiconductor device that comprises memory cell, described memory cell comprises:
Transistor, described transistorized grid is electrically connected with word line, and in described transistorized source electrode and the drain electrode one is electrically connected with bit line;
Memory element, first electrode of described memory element is electrically connected with in described transistorized described source electrode and the described drain electrode another; And
Capacitor, first electrode of described capacitor is electrically connected with described another in described transistorized described source electrode and the described drain electrode, and second electrode of described capacitor is electrically connected with second electrode of described memory element,
Wherein:
Described second electrode of described memory element and described second electrode of described capacitor are formed by the first identical metal film;
Described first electrode of described capacitor is formed by second metal film;
Described first metal film of described second electrode that plays a part described second electrode of described memory element and described capacitor is overlapping with described second metal film of described first electrode that plays a part described capacitor; And
Described memory element comprises described first electrode that is arranged in described memory element and the semiconductor film between described second electrode.
22. semiconductor device according to claim 21, wherein said transistorized active layer comprises polysilicon film or amorphous silicon film,
Wherein said transistorized gate insulating film and comprise inorganic material at described first electrode of described capacitor and the dielectric film between described second electrode, and
Wherein said transistorized described grid comprises metal film.
23. semiconductor device according to claim 21, described first electrode of wherein said memory element and the third electrode of described capacitor are formed by the 3rd identical metal film;
Described the 3rd metal film of described third electrode that plays a part described first electrode of described memory element and described capacitor is overlapping with described first metal film of described second electrode of described second electrode that plays a part described memory element and described capacitor.
24. semiconductor device according to claim 21, described first metal film that wherein plays a part described second electrode of described second electrode of described memory element and described capacitor comprises tungsten.
25. semiconductor device according to claim 21, wherein said memory cell is formed on the flexible substrate.
26. semiconductor device according to claim 21 also comprises antenna.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104620383A (en) * 2012-09-13 2015-05-13 高通股份有限公司 Anti-fuse device
CN108336983A (en) * 2017-01-17 2018-07-27 日本电波工业株式会社 Piezoelectric vibration piece and piezoelectric element
US10388875B2 (en) 2014-07-25 2019-08-20 Semiconductor Energy Laboratory Co., Ltd. Separation method, light-emitting device, module, and electronic device

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110119776A (en) * 2009-03-02 2011-11-02 가부시키가이샤 무라타 세이사쿠쇼 Antifuse device
KR101321833B1 (en) * 2010-04-09 2013-10-23 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Oxide semiconductor memory device
KR101148392B1 (en) * 2010-07-13 2012-05-21 삼성전기주식회사 Method for manufacturing semiconductor package substrate
JP6087046B2 (en) * 2011-03-01 2017-03-01 太陽誘電株式会社 Thin film element transfer method and circuit board manufacturing method
EP2711984A1 (en) * 2012-09-21 2014-03-26 Nxp B.V. Metal-insulator-metal capacitor formed within an interconnect metallisation layer of an integrated circuit and manufacturing method thereof
JP2014143410A (en) * 2012-12-28 2014-08-07 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacturing method of the same
JP6152729B2 (en) * 2013-03-26 2017-06-28 ソニー株式会社 Imaging apparatus and imaging display system
US9590059B2 (en) * 2014-12-24 2017-03-07 Taiwan Semiconductor Manufacturing Co., Ltd. Interdigitated capacitor to integrate with flash memory
JP6345107B2 (en) * 2014-12-25 2018-06-20 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
JP6500200B2 (en) * 2015-02-25 2019-04-17 株式会社フローディア Semiconductor memory device
JP6736430B2 (en) * 2016-09-05 2020-08-05 株式会社ジャパンディスプレイ Semiconductor device
US10263013B2 (en) * 2017-02-24 2019-04-16 Globalfoundries Inc. Method of forming an integrated circuit (IC) with hallow trench isolation (STI) regions and the resulting IC structure
CN107478320B (en) * 2017-08-23 2019-11-05 京东方科技集团股份有限公司 Transistor sound sensing element and preparation method thereof, sonic transducer and portable equipment
CN108333844A (en) * 2018-02-06 2018-07-27 京东方科技集团股份有限公司 Array substrate and its manufacturing method, display panel and its manufacturing method
US11031506B2 (en) 2018-08-31 2021-06-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including transistor using oxide semiconductor
US11164937B2 (en) * 2019-01-23 2021-11-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
TWI749953B (en) * 2020-05-04 2021-12-11 南亞科技股份有限公司 Semiconductor structure and semiconductor layout structure
CN115871338A (en) 2021-09-30 2023-03-31 群创光电股份有限公司 Heater device with memory unit and operation method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060267141A1 (en) * 2005-05-31 2006-11-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
CN1873997A (en) * 2005-05-31 2006-12-06 株式会社半导体能源研究所 Semiconductor device and method for manufacturing semiconductor device
CN101105975A (en) * 2006-07-14 2008-01-16 株式会社半导体能源研究所 Nonvolatile memory

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0223653A (en) 1988-07-12 1990-01-25 Seiko Epson Corp Integrated circuit
US5070384A (en) 1990-04-12 1991-12-03 Actel Corporation Electrically programmable antifuse element incorporating a dielectric and amorphous silicon interlayer
JP3501416B2 (en) 1994-04-28 2004-03-02 忠弘 大見 Semiconductor device
US5554552A (en) * 1995-04-03 1996-09-10 Taiwan Semiconductor Manufacturing Company PN junction floating gate EEPROM, flash EPROM device and method of manufacture thereof
JPH10178098A (en) * 1996-12-19 1998-06-30 Kawasaki Steel Corp Semiconductor integrated circuit device with anti-fuse element
JPH10341000A (en) * 1997-04-11 1998-12-22 Citizen Watch Co Ltd Nonvolatile semiconductor storage device and its manufacture
US6787835B2 (en) 2002-06-11 2004-09-07 Hitachi, Ltd. Semiconductor memories
JP2004221141A (en) * 2003-01-09 2004-08-05 Renesas Technology Corp Semiconductor read only memory
US7130234B2 (en) 2003-12-12 2006-10-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7319633B2 (en) 2003-12-19 2008-01-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
KR101157409B1 (en) 2004-02-10 2012-06-21 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Nonvolatile memory and IC card, ID card and ID tag incorporated with the same
JP4652087B2 (en) 2004-03-11 2011-03-16 株式会社半導体エネルギー研究所 Semiconductor device
KR101155943B1 (en) 2004-04-28 2012-06-18 가부시키가이샤 한도오따이 에네루기 켄큐쇼 MOS capacitor and semiconductor device
EP1886261B1 (en) 2005-05-31 2011-11-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2007201437A (en) 2005-12-27 2007-08-09 Semiconductor Energy Lab Co Ltd Semiconductor device
US7675796B2 (en) 2005-12-27 2010-03-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7605410B2 (en) * 2006-02-23 2009-10-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
EP1850378A3 (en) 2006-04-28 2013-08-07 Semiconductor Energy Laboratory Co., Ltd. Memory device and semicondutor device
US7742351B2 (en) 2006-06-30 2010-06-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device
CN102646681B (en) 2006-10-04 2015-08-05 株式会社半导体能源研究所 Semiconductor device
JP5296360B2 (en) * 2006-10-04 2013-09-25 株式会社半導体エネルギー研究所 Semiconductor device and manufacturing method thereof
JP5263757B2 (en) * 2007-02-02 2013-08-14 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US7994000B2 (en) 2007-02-27 2011-08-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
KR101051673B1 (en) * 2008-02-20 2011-07-26 매그나칩 반도체 유한회사 Anti-fuse and method of forming the same, unit cell of nonvolatile memory device having same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060267141A1 (en) * 2005-05-31 2006-11-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
CN1873997A (en) * 2005-05-31 2006-12-06 株式会社半导体能源研究所 Semiconductor device and method for manufacturing semiconductor device
CN101105975A (en) * 2006-07-14 2008-01-16 株式会社半导体能源研究所 Nonvolatile memory

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104620383A (en) * 2012-09-13 2015-05-13 高通股份有限公司 Anti-fuse device
CN104620383B (en) * 2012-09-13 2018-02-02 高通股份有限公司 Antifuse device
US10388875B2 (en) 2014-07-25 2019-08-20 Semiconductor Energy Laboratory Co., Ltd. Separation method, light-emitting device, module, and electronic device
CN108336983A (en) * 2017-01-17 2018-07-27 日本电波工业株式会社 Piezoelectric vibration piece and piezoelectric element
CN108336983B (en) * 2017-01-17 2022-11-08 日本电波工业株式会社 Piezoelectric vibrating reed and piezoelectric device

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