JPH10178098A - Semiconductor integrated circuit device with anti-fuse element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a filament part from being disconnected due to a switch-off phenomenon, and prevent program data from being moldified unexpectedly after a program ends of providing a noise suppression means for relaxing or absorbing noise between a power supply terminal and one electrode of an anti- fuse element. SOLUTION: A noise suppression means is arranged at a path ∥between anti- fuse elements AF1 and AF2 and a transistor TR, The noise suppression means is formed by a resistor R that is connected in series with the path, and the resistor R smoothes and relaxes noise that is largee than a program voltage that so inputted to a program power supply terminal Pp. By increasing the resistance of the resistor R higher than that of a filament, noise becomes dull and related due to the resistor R, thus preventing the filament from being disconnected based on a switch-off phenomenon. A reliable anti-fuse elements AF1 and AF2 can be obtained so that program data cannot be changed by accident after the program ends.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device having an anti-fuse element. In particular, the present invention
The present invention relates to a semiconductor integrated circuit device in which one electrode of an anti-fuse element is electrically connected to a power terminal. In the present invention, the anti-fuse element constitutes a semiconductor integrated circuit device such as a field programmable gate array (FPGA) and a programmable read only memory (PROM).

[0002]

2. Description of the Related Art An antifuse element mounted on a semiconductor integrated circuit device such as an FPGA or a PROM includes a lower layer electrode, an antifuse insulating film, and an upper layer electrode as described in, for example, the following document. IEEE, Electron Device Lette
r, Vol.12, No.4, April 1991, pp.151-153., IEEE, Electro
n Device Letter, Vol.13, No.9, September, 1992, pp.488-
490.

[0003] Both the lower electrode and the upper electrode of the anti-fuse element are connected between circuits mounted on a semiconductor integrated circuit device.
A wiring for electrically connecting elements and the like is used, and is formed on the same wiring layer and the same wiring material as the wiring. That is, the lower electrode of the anti-fuse element is the first electrode of the semiconductor integrated circuit device.
The upper-layer electrode is formed in the same manufacturing process as the second-layer wiring, and the upper-layer electrode is formed in the same manufacturing process as the second-layer wiring. The antifuse insulating film is formed on the surface of the lower electrode, and is formed between the lower electrode and the upper electrode.

The user can arbitrarily program the anti-fuse element. The program is performed by applying a program voltage to an anti-fuse element at a location to be programmed.

The program voltage supplied to the power supply terminal uses a voltage higher than the circuit operating voltage of the semiconductor integrated circuit device, and the program voltage is applied between the lower electrode and the upper electrode of the anti-fuse element. When a program voltage is applied, the insulating film for the antifuse is broken, and the material of the upper and lower electrodes melts and flows into the broken portion of the insulating film for the antifuse, and a filament (conductive) electrically connects the upper and lower electrodes. Passage) is formed. Since the program can be executed after the manufacturing process of the semiconductor integrated circuit device has been completed, it is characterized in that the time required for completing the product can be shortened.

[0006]

However, in the above-mentioned anti-fuse element mounted on the semiconductor integrated circuit device, a switch-off phenomenon occurs in which the filament portion is broken during the operation after the program is completed, and the circuit does not operate. There was a problem that. The switch-off phenomenon is a phenomenon in which when a noise voltage higher than the program voltage is applied between the upper and lower electrodes of the anti-fuse element, the filament is melted by Joule heat and the filament is disconnected.
The present inventor considers. The noise voltage that causes the switch-off phenomenon includes, for example, static electricity generated artificially.

The present invention has been made to solve the above problems.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device having a highly reliable anti-fuse element which prevents a break in a filament portion of the anti-fuse element due to a switch-off phenomenon and prevents the contents of a program from being changed abruptly after a program is completed. An integrated circuit device is provided.

It is a further object of the present invention to provide a semiconductor integrated circuit device which achieves the above object, reduces a signal delay flowing through the anti-fuse element, and realizes a high circuit operation speed.

[0010]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device in which one electrode of an anti-fuse element is electrically connected to a power supply terminal. The power supply terminal and one electrode of the anti-fuse element include noise suppression means for reducing or absorbing noise that breaks the filament of the anti-fuse element, and the noise of the anti-fuse element caused by the noise input to the power supply terminal. The disconnection is prevented by the noise suppressing means. In the invention described in claim 1, for example, when static electricity generated by human handling is input to the power supply terminal as noise higher than the program voltage, most of the noise is supplied to the anti-fuse element by the noise suppressing unit before the noise reaches the anti-fuse element. Relaxed or absorbed. As a result, the noise reduced by the noise suppression means or the noise that has been largely absorbed is supplied to the filament of the anti-fuse element, so that the generation of Joule heat is suppressed in the filament portion, and the disconnection of the filament can be prevented.

According to a second aspect of the present invention, in the semiconductor integrated circuit device according to the first aspect, the noise suppressing means is connected in series between the power supply terminal and one electrode of the anti-fuse element. And a resistor having a resistance greater than the resistance of the filament of the anti-fuse element. According to the second aspect of the present invention, since the noise input to the power supply terminal is reduced by the resistor before reaching the antifuse element, disconnection of the filament of the antifuse element can be prevented.

According to a third aspect of the present invention, in the semiconductor integrated circuit device according to the second aspect, the resistor has a resistance in a range of 3 to 20 times the resistance of the filament of the anti-fuse element. It is characterized by being set to a value. According to the third aspect of the invention, the resistance of the resistor is three times the resistance of the filament of the anti-fuse element.
By setting the value to twice or more, noise input to the power supply terminal can be sufficiently reduced, so that the filament can be prevented from being broken. Furthermore, by setting the resistance value of the resistor to be 20 times or less the resistance value of the filament of the anti-fuse element, a signal delay flowing through the filament of the anti-fuse element can be suppressed, so that the circuit operation speed can be increased. .

According to a fourth aspect of the present invention, in the semiconductor integrated circuit device according to the second or third aspect,
A switching element is provided between the power terminal and the resistor.
MISFET (Metal Insulator Semiconductor Field Effect
Transistor), and the resistor is formed of the same gate material formed on the same conductive layer as the gate electrode of the MISFET. In the invention described in claim 4, since the resistor can be formed of the same gate material on the same conductive layer as the gate electrode of the MISFET, the resistor can be easily incorporated. As a feature of the manufacturing process, the resistor can be formed in the same step as the step of forming the gate electrode of the MISFET (also used as a step), so that the number of manufacturing steps corresponds to the step of forming the resistor. Can be reduced.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit device according to the first aspect, the noise suppressing means is connected in parallel between the power supply terminal and at least one electrode of the anti-fuse element. It is a connected diode element or a MISFET connected in series between the power supply terminal and one electrode of the anti-fuse element.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit device having an anti-fuse element and employing a CMOS structure according to an embodiment of the present invention will be described below.

The circuit configuration diagram 1 is a circuit diagram of the anti-fuse element according to the embodiment of the present invention. As shown in FIG. 1, one electrode of the anti-fuse elements AF1 and AF2 electrically connected in parallel is connected to a program power supply terminal Pp through a transistor Tr used as a switching element. The anti-fuse element AF1 is in a state where it is programmed by a program and generates a filament. The anti-fuse element AF2 indicates a state in which no programming is performed by the program and no filament is generated.

The program power supply terminal Pp supplies a program voltage necessary for programming the anti-fuse element AF1. As the program voltage, 10 V is used in the present embodiment. The circuit operating voltage flowing through the filament of the anti-fuse element AF1 uses a voltage in the range of 3-5V. The transistor Tr is formed by a CMOS transistor. The gate electrode of this CMOS transistor is connected to the switching control terminal Pc.

The anti-fuse elements AF1 and AF2
A noise suppressor is arranged on a path between the power supply terminal and the program power supply terminal Pp, more specifically, on a path between the anti-fuse elements AF1 and AF2 and the transistor Tr. In the present embodiment, the noise suppressing means is formed by a resistor R connected in series to the path. The resistor R has a function of smoothing and reducing noise higher than the program voltage input to the program power supply terminal Pp.

[0019] Structure Figure 2 is the anti-fuse element AF1, AF2, plan view including a resistor R is a transistor Tr and noise suppression means, FIG. 3 is a sectional view taken along line A-A shown in FIG. 2 .

The semiconductor integrated circuit device has a single crystal p
The semiconductor device 1 is mainly configured. This semiconductor substrate 1
In this case, a p-type well region 2 is formed in the main surface of the region where the n-channel MISFET is formed, and an n-type well region 3 is formed in the main surface of the region where the p-channel MISFET is formed.

A field insulating film 4 is formed on the main surface of each element isolation region of the p-type well region 2 and the n-type well region 3.
Is formed. The field insulating film 4 is formed of, for example, SiO ₂ formed by oxidizing the surface of the semiconductor substrate 1 by a selective oxidation method. The main surface of the element isolation region of the p-type well region 2 has p
A mold channel stopper region 5 is formed.

The n-channel MISFET includes a p-type well region 2 used as a channel forming region, a gate insulating film 6, a gate electrode 7G, and a pair of n-type semiconductor regions 8 used as a source region and a drain region. Although detailed description is omitted, in the present embodiment, the n-channel MIS
The FET has a salicide structure, and the gate electrode 7G is a polycrystalline S
The n-type semiconductor region 8 has a silicide layer on the surface while being formed in a polycide structure in which an i film and a silicide film are stacked. Silicide film of gate electrode 7G, n
The silicide layer of the type semiconductor region 8 is formed of TiSi ₂ , although not limited to this material. Furthermore, the n-channel MISFET is LD
The n-type semiconductor region 8 is formed in the D structure, and the impurity concentration on the channel forming region side is set to be low.

The p-channel MISFET includes an n-type well region 3 used as a channel forming region, a gate insulating film 6, a gate electrode 7G, and a pair of p-type semiconductor regions 9 used as a source region and a drain region. Similarly p
The channel MISFET has a salicide structure and is formed with an LDD structure.

The resistor R as the noise suppressing means is formed by the gate wiring 7R. The gate wiring 7R is formed on the surface of the field insulating film 4 and has an n-channel MISFE.
The same gate material as the gate electrode 7G is formed on the same conductive layer (gate wiring layer) as the gate electrode 7G of each of the T and p channel MISFETs. That is, in this embodiment, the gate wiring 7R is formed of a polycide film formed of a laminated film of a polycrystalline Si film and a TiSi ₂ film. Gate wiring 7
In R, since the specific resistance of the TiSi ₂ film is smaller than the specific resistance of the polycrystalline Si film, the size of the TiSi ₂ film controls the effective resistance of the resistor R. The gate wiring 7R is
Since the specific resistance value of the first-layer wiring and the second-layer wiring mainly composed of Al, which will be described later, is large, a sufficient resistance value can be set in a small occupied area.

The anti-fuse elements AF1 and AF2
Is formed on the surface of the interlayer insulating film 10 covering the n-channel MISFET, the p-channel MISFET and the resistor R. Each of the anti-fuse elements AF1 and AF2 has a structure in which a lower layer electrode 12F, an anti-fuse insulating film 15, and an upper layer electrode 16F are sequentially laminated.

The lower electrode 12F is formed of the same conductive layer and the same wiring material as the first layer wiring 12 of the semiconductor integrated circuit device. The first layer wiring 12 is formed on the surface of the interlayer insulating film 10, and in this embodiment, Al or Cu, or an alloy film containing at least one of Al and Cu, and TiW silicide laminated on the surface thereof The membrane is formed of a composite membrane. That is, the lower layer electrode 12F is formed of the same composite film as the first layer wiring 12.

The antifuse insulating film 15 is provided in the lower electrode 12F in the opening 14 formed in the interlayer insulating film 13 covering the surfaces of the first wiring layer 12 and the lower electrode 12F.
Formed on the surface of

The upper layer electrode 16F is formed of the same conductive layer and the same wiring material as the second layer wiring 16. The second-layer wiring 16 is formed on the surface of the interlayer insulating film 13 and on the surface of the antifuse insulating film 15, and is formed of an Al-Cu alloy film in the present embodiment. That is, the upper electrode 16
F is similarly formed of an Al-Cu alloy film.

In each of the thus configured anti-fuse elements AF1 and AF2, the anti-fuse element AF1 is programmed by a program, and the lower electrode 12F and the upper layer electrode 16F of the anti-fuse element AF1 are electrically connected. A filament F is formed.

The lower electrode 12F of each of the anti-fuse elements AF1 and AF2 is electrically connected to a gate wiring 7R as a resistor R through a connection hole 11 formed in the interlayer insulating film 10. The upper layer electrode 16F is the second layer wiring 16
Through to the internal circuit.

A final passivation film 17 is formed on the upper layer electrode 16F of the second layer wiring 16 and the antifuse elements AF1 and AF2.

Manufacturing Method FIGS. 4 and 5 are cross-sectional views illustrating a method of manufacturing the above-described semiconductor integrated circuit device for each process.

First, an n-type well region 3, p
After forming each of the type well regions 2, a field insulating film 4 is formed on each main surface of the n-type well region 3 and the p-type well region 2 in the element isolation region (see FIG. 4). Further, in substantially the same step as the formation of the field insulating film 4, a p-type channel stopper region 5 is formed in the main surface portion of the p-type well region 2 in the element isolation region.

Next, as shown in FIG. 4, an n-channel MISFET is formed on the main surface of the p-type well region 2 and a p-channel MISFET is formed on the main surface of the n-type well region 3, respectively. A resistor R is formed thereon.

In the n-channel MISFET and the p-channel MISFET, first, after forming the gate insulating film 6, a polycrystalline Si film is formed on the surface of the gate insulating film 6. The polycrystalline Si film is deposited by a CVD method or a sputtering method, and is patterned after introducing impurities (for example, P) for the purpose of lowering resistance. Using the polycrystalline Si film as a mask, an n-type semiconductor region 8 is formed on the main surface of the p-type well region 2, and a p-type semiconductor region 9 is formed on the main surface of the n-type well region 3. Both the n-type semiconductor region 8 and the p-type semiconductor region 9 are formed by ion implantation. In this embodiment, since both the n-channel MISFET and the p-channel MISFET are formed in the LDD structure, the ion implantation method uses a polycrystalline Si film as a mask to implant impurities at a low concentration, and forms a sidewall spacer. Impurities are implanted at a high concentration using the sidewall spacers as a mask. Thereafter, in order to form a salicide structure, a refractory metal film such as a Ti film is formed on the entire surface by a sputtering method, silicidation is performed, and the surface of the polycrystalline Si film, the surface of the n-type semiconductor region 8, p-type semiconductor region 9
A TiSi ₂ film is formed on each of the surfaces.

The Ti film that is not silicided is selectively removed. When the silicidation process is completed, the gate electrode 7G, the n-type semiconductor region 8, and the p-type semiconductor region 9 are formed, respectively, and the n-channel MISFET and the p-channel MISFET are completed.

Further, in the same step as the step of forming the gate electrode 7G, a gate wiring 7R as a resistor R as a noise suppressing means is formed. In this embodiment,
The TiSi ₂ film of the gate wiring 7R that effectively controls the resistance value is 3
Since it is formed with a thickness of 0 nm, when the wiring width is about 2 μm, a resistance value of 8.7Ω is obtained per 1 μm of the wiring length, and about 1.15
With a wiring length of μm-11.5 μm, a resistance value of 10-100Ω can be easily obtained.

Next, as shown in FIG.
Second, the second-layer wiring 16 is formed, and the anti-fuse elements AF1 and AF2 are formed.

First, after forming the interlayer insulating film 10, a connection hole 11 is formed, and a first-layer wiring 12 is formed on the surface of the interlayer insulating film 10. In the same step as the step of forming the first-layer wiring 12, the anti-fuse elements AF1,
Each lower electrode 12F of AF2 is formed. First
The layer wiring 12 and the lower electrode 12F are formed on the Al-Cu film by, for example, WSi.
It is formed of a composite film in which films are stacked. The Al-Cu film is formed to a thickness of 800 nm by a sputtering method. The WSi film is formed to a thickness of 200 nm by, for example, a sputtering method, and is formed in an amorphous state.

Then, the first-layer wiring 12 and the lower-layer electrode 12
An interlayer insulating film 13 covering F is formed, and the interlayer insulating film 13 on the lower electrode 12F is removed to form an opening 14. Thereafter, an antifuse insulating film 15 is formed in the opening 14 on the surface of the lower electrode 12F. In the present embodiment the antifuse insulating film 15 is used the Si ₃ N ₄ film, the the Si ₃ N ₄ film is deposited by plasma CVD method using a gas-phase reaction of the silane, ammonia and nitrogen gas. Si ₃ N ₄
The film is formed in a thickness range of 5 to 100 nm, and is formed, for example, in a thickness of 10 nm in the present embodiment.

Then, a second-layer wiring 16 is formed on the surface of the interlayer insulating film 13 (actually, the antifuse insulating film 15 formed on the entire surface). In the same step as the step of forming the second layer wiring 16, the anti-fuse element A
An upper electrode 16F is formed on the lower electrode 12F of each of F1 and AF2 and on the surface of the antifuse insulating film 15. The second layer wiring 16 and the upper layer electrode 16F are made of Al-Cu
This Al-Cu film is formed to a thickness of 800 nm by a sputtering method.

Finally, a final passivation film 17 is formed on the entire surface, so that the anti-fuse element A
A semiconductor integrated circuit device having F1 and AF2 is completed.

FIG. 6 shows the effect of the noise suppressing means according to the present embodiment.
FIG. 7 is a current-voltage characteristic diagram when a resistor R is disposed.

As shown in FIG. 6, in the anti-fuse element AF1 in which the programmed filament F is formed, a switch-off phenomenon occurs in which the filament F is suddenly disconnected when the voltage and the current increase. The resistance value of the filament F of the anti-fuse element AF1 is 10Ω,
When a voltage of 0.2V-0.4V is applied and a current of 20mA-40mA flows, the filament F is broken.

On the other hand, as shown in FIG. 7, a resistor R is inserted in series between the anti-fuse element AF1 and the program power supply terminal Pp, and the resistance of the resistor R is determined by the resistance of the filament F. Since the noise is reduced and reduced by the resistor R by making the resistance R larger, the breakage of the filament F due to the switch-off phenomenon does not occur. When the resistance value of the resistor R is set to 100Ω and about 10 times the resistance value of the filament F, the filament F does not break even at a voltage of about 5 V and a current of about 50 mA.

FIG. 8 is a diagram showing the relationship between the change in the resistance value of the resistor R according to the present embodiment and the rate of occurrence of the switch-off phenomenon. The horizontal axis is the resistor R and the anti-fuse element AF.
1 shows the ratio of the resistance value to the filament F, and the vertical axis shows the ratio% at which the switch-off phenomenon occurs. The resistance value of the filament F is fixed at 10Ω, and the resistance value of the resistor R is 10Ω.
Ω, 20Ω, 30Ω, etc. The resistance value of the resistor R
In the case of 10Ω, that is, in the case of the resistance ratio of 1, the filament F was broken by the switch-off phenomenon at a rate of about 80%. This ratio is the result based on 100 samples. When the resistance value of the resistor R is increased to 20Ω and the resistance ratio is 2, about 30
Breakage of the filament F occurs at a rate of%. And
When the resistance value of the resistor R is set to 30 Ω or more, that is, when the resistance ratio is set to 3 or more, the filament F
No disconnection occurs. Accordingly, the resistance of the resistor R is 3 times the resistance of the filament F of the anti-fuse element AF1.
More than double is required.

Further, if the resistance value of the resistor R is too high, specifically, if the resistance value of the resistor R exceeds 20 times the filament F, the signal delay flowing through the filament F exceeds the allowable range. Since the circuit operation speed becomes slow, the resistance value of the resistor R needs to be set to 20 times or less the resistance value of the filament F.

Modifications FIGS. 9 and 10 are circuit diagrams each illustrating a modification of the noise suppression means. The noise suppression means shown in FIG. 9 is formed by a MISFET Rt inserted in series between each of the anti-fuse elements AF1 and AF2 and the program power supply terminal Pp. This MISFETRt is connected to the program power supply terminal P
Noise is absorbed by the diode element parasitically formed by the p-side semiconductor region and the well region where the semiconductor region is formed, and the noise is reduced by the channel resistance.

The noise suppressing means shown in FIG. 10 is formed by a diode element D inserted in parallel between each of the anti-fuse elements AF1 and AF2 and the program power supply terminal Pp. The diode element D can absorb noise.

Further, in the present invention, the noise suppressing means can be arranged between each of the anti-fuse elements AF1 and AF2 and the program power supply terminal Pp, and between the transistor Tr and the program power supply terminal Pp.

Further, in the present invention, the resistor R as a noise suppressing means can be formed in a semiconductor region (diffusion layer).

[0052]

According to the present invention, there is provided a semiconductor integrated circuit having a highly reliable anti-fuse element which prevents a filament portion of the anti-fuse element from being disconnected due to a switch-off phenomenon, and which does not unexpectedly change the program content after the program is completed. A circuit device can be provided.

Further, in the present invention, it is possible to provide a semiconductor integrated circuit device having an anti-fuse element capable of reducing a signal delay flowing through the anti-fuse element and realizing a high circuit operation speed, in addition to the above effects.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of an anti-fuse element according to an embodiment of the present invention.

FIG. 2 is a plan view including an anti-fuse element, a transistor, and a resistor serving as noise suppression means.

FIG. 3 is a sectional view taken along the line AA shown in FIG.

FIG. 4 is a cross-sectional view in a first step for describing the method for manufacturing a semiconductor integrated circuit device described above.

FIG. 5 is a sectional view in a second step.

FIG. 6 is a current-voltage characteristic diagram in a case where a resistor serving as noise suppression means is not provided.

FIG. 7 is a current-voltage characteristic diagram when a resistor as noise suppression means is arranged.

FIG. 8 is a diagram illustrating a relationship between a change in the resistance value of the resistor and a rate of occurrence of a switch-off phenomenon.

FIG. 9 is a circuit diagram illustrating a modified example of the noise suppression unit.

FIG. 10 is a circuit diagram illustrating a modified example of the noise suppression unit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 7G gate electrode, 7R gate wiring, 12 1st layer wiring, 12F Lower layer electrode, 15 Antifuse insulating film, 16 2nd layer wiring, 16F
Upper electrode, AF anti-fuse element, Tr transistor, Pp program power supply terminal, R resistor (noise suppressing means), Rt MISFET (noise suppressing means), D diode element (noise suppressing means), F filament.

Claims (5)

[Claims] 1. A semiconductor integrated circuit device in which one electrode of an anti-fuse element is electrically connected to a power terminal, wherein a filament of the anti-fuse element is disconnected between the power terminal and one electrode of the anti-fuse element. A semiconductor integrated circuit device, comprising: a noise suppressing unit configured to reduce or absorb noise to be caused, wherein a break of a filament of an anti-fuse element due to noise input to the power supply terminal is prevented by the noise suppressing unit. 2. The semiconductor integrated circuit device according to claim 1, wherein said noise suppressing means is connected in series between said power supply terminal and one electrode of an anti-fuse element, A semiconductor integrated circuit device comprising a resistor having a larger resistance value than a resistance value of a filament. 3. The semiconductor integrated circuit device according to claim 2, wherein the resistor has a resistance value in a range of 3 to 20 times a resistance value of a filament of the anti-fuse element. A semiconductor integrated circuit device characterized by the above-mentioned. 4. The semiconductor integrated circuit device according to claim 2, wherein a switch element is provided between the power supply terminal and a resistor.
A semiconductor integrated circuit device, wherein an MISFET is arranged, and the resistor is formed of the same gate material formed on the same conductive layer as a gate electrode of the MISFET. 5. The semiconductor integrated circuit device according to claim 1, wherein the noise suppressing unit is a diode element connected in parallel between the power supply terminal and at least one electrode of an anti-fuse element. A semiconductor integrated circuit device comprising a MISFET connected in series between the power terminal and one electrode of the anti-fuse element.