JP2010079984A - Driving method of semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an anti-fuse type semiconductor memory device capable of writing an information even in other than manufacture and to enhance a miniaturization of semiconductor memory device and a capacity increase thereof. <P>SOLUTION: This semiconductor memory device is provided with a memory cell array in which the memory cells are arranged in a matrix state, and constituted of a bit line driving circuit and a word line driving circuit. In the case of memory cells such as m×n pieces of memory cells 103 (MC(1, 1) to M(m, n)) are arranged in the matrix state, the memory cells are arranged at crossing parts of bit lines and word lines. By constituting the bit line driving circuit 101 and the word line driving circuit 102 by the less number of components, the scale miniaturization and capacity increase of the memory device can be achieved. Such a driving method of the memory device is provided that less number of components of the bit line driving circuit and word line driving circuit are feasible. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and a semiconductor device. In particular, the present invention relates to an antifuse-type semiconductor memory device including an antifuse-type semiconductor memory device, and a semiconductor device.

  Note that in this specification, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. In this specification, a semiconductor memory device refers to a memory device that can function by utilizing semiconductor characteristics.

  2. Description of the Related Art Technology development related to devices that are temporarily (volatile memory) or semipermanently (nonvolatile memory) by applying an electrical or physical action to a storage device (also referred to as a memory) included in an electronic device is thriving It is. In recent years, the design and development of a new storage device for reducing the cost by improving the functionality or miniaturization is also active. Note that the volatile memory refers to a storage device in which data is lost even after the data is retained. The nonvolatile memory refers to a storage device that can hold data semipermanently after holding the data.

  Among non-volatile memories, ROM (Read Only Memory) dedicated for reading is classified into mask ROM and PROM (Programmable ROM). The PROM is an EEPROM (Electrically Erasable and Programmable Read Only Memory), the fuse type ROM, and the antifuse type ROM belong to the PROM.

  The mask ROM is a ROM in which information is written using a photomask or a laser direct drawing apparatus in a manufacturing process. A fuse-type ROM is a ROM that uses a fuse, which is in a conductive state at the time of manufacture, as a memory element. After the manufacture, the fuse is cut by current and information is stored by cutting off the electrical connection between the electrodes of the fuse. ROM (hereinafter referred to as a fuse-type storage device). On the other hand, an antifuse-type ROM is a ROM that uses an antifuse, which is in a non-conductive state at the time of manufacture, as a memory element, and information is obtained by electrically connecting the electrodes of the antifuse with an electric current after manufacture. A ROM for writing (hereinafter referred to as an antifuse-type storage device). For example, Patent Document 1 describes an antifuse storage device in which an antifuse storage element is electrically connected in series to a PN junction diode.

  An object of the present invention is to provide an antifuse-type semiconductor memory device capable of writing information other than manufacturing. Another object of the present invention is to reduce the size and capacity of a semiconductor memory device.

  The semiconductor memory device of the present invention has a memory cell array in which memory cells are arranged in a matrix, and includes a bit line driving circuit and a word line driving circuit. FIG. 1 shows an example of a memory cell in which m × n memory cell arrays 103 (MC (1, 1) to M (m, n)) are arranged in a matrix. Note that the memory cell is provided at the intersection of the bit line and the word line. By configuring the bit line driving circuit and the 101 word line driving circuit 102 with a smaller number of parts, the memory device can be reduced in size and capacity. The present invention provides a method for driving a memory device in which the number of parts of the bit line driving circuit and the word line driving circuit can be reduced.

  According to one aspect of the present invention for solving the above problems, a driving method of a semiconductor memory device according to the present invention includes a memory cell including a diode element and a memory element, and an anti-transistor including a plurality of signal lines including bit lines and word lines. In a driving method of a fuse type semiconductor memory device, a bit line and a word line which are not selected for writing are set in a floating state during a writing operation.

  According to one aspect of the present invention for solving the above problems, a driving method of a semiconductor memory device according to the present invention includes a memory cell including a diode element and a memory element, and an anti-transistor including a plurality of signal lines including bit lines and word lines. In a method for driving a fuse type semiconductor memory device, a bit line that is selected for writing during a write operation is set to a positive potential, a word line that is selected for writing is set to a ground potential, and a bit line that is not selected for writing The word line is floated.

  According to one aspect of the present invention for solving the above problems, a driving method of a semiconductor memory device according to the present invention includes a memory cell including a diode element and a memory element, and an anti-transistor including a plurality of signal lines including bit lines and word lines. In a method of driving a fuse-type semiconductor memory device, a bit line that is selected for writing during a write operation is set to a positive potential, a word line that is selected for writing is set to a negative potential, and a bit line that is not selected for writing The word line is floated.

  The diode element of the present invention is a pin-type diode or a pn-type diode.

  The semiconductor memory device of the present invention is formed on a flexible substrate.

  The semiconductor memory device of the present invention is used for a wireless chip.

  According to the present invention, a semiconductor memory device can be reduced in size, and a semiconductor memory device with a large capacity and low cost can be provided.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

(Embodiment 1)
In this embodiment mode, a semiconductor memory device of the present invention is described.

  A configuration example of a memory cell array and a peripheral driver circuit included in a semiconductor memory device is illustrated in FIG. A circuit diagram of a memory cell included in the memory cell array is illustrated in FIG. FIG. 11 is a top view of the memory cell 106 in FIG.

  The semiconductor memory device 100 includes a bit line drive circuit 101, a word line drive circuit 102, and a memory cell array 103. In FIG. 1A, as an example, a memory cell array in which m × n memory cells 106 (MC (1, 1) to MC (m, n)) are arranged in a matrix of m vertical × n horizontal. An example of 103 is shown. Note that the memory cell 106 is provided at each intersection of the bit line and the word line. The semiconductor memory device 100 generates a plurality of voltage levels in each memory cell from the bit line driving circuit 101 and the word line driving circuit 102.

  Note that the terms “first”, “second”, “third” to “N” (N is a natural number) used in this specification are given to avoid confusion of components and are not limited numerically. I will add that.

  Note that in this specification, A and B are connected to each other, including A and B being directly connected, as well as those being electrically connected. Here, A and B are electrically connected when A and B have an object having some electrical action, and A and B are substantially identical through the object. It shall represent the case of becoming a node.

  Specifically, A and B are connected via a switching element such as a transistor, and when A and B are approximately at the same potential due to conduction of the switching element, or A and B are connected via a resistance element. Are connected to each other, and the potential difference generated between both ends of the resistance element is such that the operation of the circuit including A and B is not affected. It represents the case where it can be understood as.

  Note that a semiconductor memory device refers to a memory device that can function by utilizing semiconductor characteristics. Note that the semiconductor memory device includes a memory cell array including a plurality of memory cells. Note that the semiconductor memory device may include a bit line driver circuit, a word line driver circuit, and an interface unit which are peripheral driver circuits for driving a plurality of memory cells. Note that the peripheral driver circuit that drives the plurality of memory cells may be formed over the same substrate as the plurality of memory cells. By forming the peripheral driver circuit and the plurality of memory cells over the same substrate such as a glass substrate, there is an advantage that the peripheral driver circuit and the plurality of memory cells can be manufactured at a lower cost than in the case of manufacturing using a single crystal silicon substrate.

  Note that in this specification, the pin type diode can be applied even if another diode element such as a pn type diode is used. In the description, the bit line side having a high potential (voltage) is used as an anode when operating, and the antifuse side having a low potential (voltage) is used as a cathode when operating. The antifuse will be described with the terminal electrically connected to the cathode of the pin diode as the first terminal and the word line side as the second terminal. In addition, the p-type, i-type, and n-type semiconductor regions constituting the pin-type diode are referred to as a p-type semiconductor region, an intrinsic semiconductor region, and an n-type semiconductor region, respectively.

  Note that in this specification, a transistor is an element having at least three terminals including a gate, a drain, and a source, and has a channel region between the drain region and the source region. Current can flow through the region and the source region. Here, since the source and the drain vary depending on the structure and operating conditions of the transistor, it may be difficult to limit which is the source or the drain. Therefore, in this embodiment, the regions functioning as the source and the drain may be referred to as a first terminal and a second terminal, respectively. A terminal functioning as a gate may be referred to as a gate terminal.

  Note that the voltage in each wiring described in this specification corresponds to a potential difference in the case where a ground potential GND (also referred to as ground voltage GND, VGND, or 0) is used as a reference potential. Therefore, the voltage is sometimes called a potential, or the potential is called a voltage.

  Next, in this embodiment, the operation of the semiconductor memory device 100 shown in FIGS. 1A and 1B will be described with reference to FIGS.

  3, 4, 5, and 6, for the sake of explanation, data is written and written by the first bit line B1 or the second bit line B2, the first word W1 or the second word line W2. A memory cell MC (1, 1), a memory cell MC (1, 2), a memory cell MC (2, 1), and a memory cell MC (2, 2) to be read are shown.

As described above, the antifuse used in the present invention is in a non-conductive state (resistor R _O ) at the time of manufacture, and is electrically connected between the first terminal and the second terminal of the antifuse by flowing a current after manufacture. By doing so, it is in a conductive state (resistance R _W ) and information is written. The size of the relationship between the resistance value of the resistor _{R O} and the resistor _{R W} is a a resistor _{R O} »resistor _{R W.} Therefore, information is written by applying a high voltage between the first terminal and the second terminal of the antifuse to flow current.

  Specifically, when data is written by passing a current through the memory cell MC (1, 1), the first bit line B1 is set to the write voltage Vw and the first word line W1 is set as shown in FIG. GND, the second bit line, and the second word line W2 are brought into a floating state. Then, as indicated by an arrow 201 in FIG. 2A, a current flows from the first bit line B1 to the first word line W1 via a pin-type diode and an antifuse. That is, a high voltage is applied between the first terminal and the second terminal of the antifuse, and a conductive state in which information is written is established. Note that the voltages of the bit line and the word line are all set to GND before the write state is entered.

  A case where the memory cell MC (2, 1) is not written in FIG. 2B will be described. The voltage of W2 changes to a value close to Vw by capacitive coupling generated between the first terminal and the second terminal of the antifuse. Therefore, a voltage necessary for writing is not generated between the first terminal and the second terminal of the antifuse of the memory cell MC (2, 1), so that the antifuse is kept non-conductive.

  A case where the memory cell MC (2, 2) is not written will be described. Although W2 changes to a value close to Vw1 due to capacitive coupling generated in other memory cells, in any case, a voltage required for writing is not applied between the first terminal and the second terminal of the antifuse. The antifuse remains non-conductive.

  In FIG. 2, the positional relationship between the four memory cells represents a relative positional relationship in the memory cell array. The memory cell MC (1,1) is the selected memory cell, the memory cell MC (1,2) is the same column memory cell, the memory cell MC (2,1) is the same row memory cell, and the memory cell MC (2,2) is not selected. It can be called a memory cell. Each of the above relationships holds even when an arbitrary memory cell MC (m, n) is written in the memory cell array.

(Embodiment 2)

  A write operation in this embodiment will be described with reference to FIG. When data is written by passing a current through the memory cell MC (1, 1), the first bit line B1 is the write voltage Vw1, the first word line W1 is Vw2, and the second bit line and the second word line W2 are written. To float. Then, as indicated by an arrow 301 in FIG. 3A, a current flows from the first bit line B1 to the first word line W1 via a pin-type diode and an antifuse. That is, a high voltage is applied between the first terminal and the second terminal of the antifuse, and a conductive state in which information is written is established.

  In FIG. 3A, the second bit line B2 and the second word line W2 are left floating. The first voltage Vw1 is a positive voltage, the second write voltage Vw2 is a negative voltage, and the difference between the voltages Vw1 and Vw2 is set to be the antifuse write voltage. Note that the voltages of the bit line and the word line are all set to GND before the write state is entered.

  A case where the memory cell MC (2, 1) is not written in FIG. 3B will be described. The voltage of W2 changes to a value close to Vw1 due to capacitive coupling generated between the first terminal and the second terminal of the antifuse. For this reason, a voltage necessary for writing is not generated between the first terminal and the second terminal of the antifuse of the memory cell MC (1,2), so that the antifuse is kept non-conductive.

  A case where the memory cell MC (1,2) is not written in FIG. 3C will be described. The second write voltage Vw2 is a forward voltage of the pin-type diode, and Vw2 is applied to the second terminal of the antifuse. Then, the first terminal of the antifuse changes to a value close to Vw2 due to capacitive coupling with the second terminal, and the antifuse maintains a non-conductive state.

  A case where the memory cell MC (2, 2) is not written will be described. B2 changes to Vw2 and W2 changes to a value close to Vw1 due to capacitive coupling generated in another memory cell, but the potential difference between the first terminal and the second terminal of the antifuse is equal to the capacitance C1 between the terminals of the antifuse. Since the voltage is divided by the capacitance C2 between the anode and the cathode of the pin-type diode and does not reach the voltage necessary for writing, the antifuse keeps the non-conduction state.

(Embodiment 3)

  In this embodiment, a specific structure of the memory device described in Embodiment 1 is described with reference to drawings.

  FIG. 4 shows a circuit configuration of the bit line driving circuit 101 and the word line driving circuit 102. One bit line driving circuit 101 and one word line driving circuit 102 are connected to each bit line and word line of the memory cell. The bit line driving circuit includes a bit address selection signal 401 that is a signal for controlling selection / non-selection of the bit line, a level shift circuit 402 that converts the voltage amplitude of the bit address selection signal into a write voltage Vw1, and a switch 403 that drives the bit line. It consists of The word line driving circuit includes a word address selection signal 404 which is a signal for controlling selection / non-selection of a word line and a switch 405 for driving the word line.

  In FIG. 4, when a selection signal is input to the gate terminal of the switch of the bit line driver circuit via the level shifter, the bit line 406 is charged with Vw1. Conversely, when a non-selection signal is input, the switch is turned off and the bit line 408 is in a floating state. When the selection signal is input to the gate terminal of the switch of the word line driver circuit, the word line 407 is set to the GND state, and when the non-selection signal is input, the word line 409 is set to the floating state.

  In some cases, the bit line driving circuit in FIG. 4 is connected to a reading circuit for reading data from the memory.

  Note that in this specification, the switch is not limited to a specific one as long as it can control conduction or non-conduction between one terminal and the other terminal. Examples of the switch include an electrical switch and a mechanical switch. As an example, an analog switch or the like may be configured using a thin film transistor.

(Embodiment 4)

  In this embodiment, a specific structure of the memory device described in Embodiment 2 is described with reference to drawings.

  FIG. 5 shows a circuit configuration of the bit line driving circuit 101 and the word line driving circuit 102. One bit line driving circuit 101 and one word line driving circuit 102 are connected to each bit line and word line of the memory cell. The bit line driving circuit 101 includes a bit address selection signal 501 and a switch 502 for driving the bit line. The word line driving circuit 102 includes a level shift circuit 504 that converts the voltage amplitude of the word address selection signal 503 and the bit address selection signal into a write voltage Vw2, and a switch 505 that drives the word line.

  In FIG. 5, when a selection signal is input to the gate terminal of the switch 502 of the bit line driver circuit 101, the bit line 506 is charged with Vw1, and when a non-selection signal is input, the switch 502 is turned off and the bit line 508 is turned off. It becomes a floating state. The switch 505 of the word line driver circuit 102 also charges the word line 507 with Vw2 when a selection signal is input to the gate terminal, and puts the word line 509 into a floating state when a non-selection signal is input.

  In some cases, the bit line driver circuit in FIG. 5 is connected to a read circuit for reading data from the memory.

  For comparison, a memory device that performs an operation without bringing unselected bit lines and word lines into a floating state will be described with reference to FIG. A circuit configuration of the bit line driving circuit 101 and the word line driving circuit 102 is shown. One bit line driving circuit 101 and one word line driving circuit 102 are connected to each bit line and word line of the memory cell. The bit line driving circuit 101 includes a bit address selection signal 601 and a level shift circuit 602 for converting the voltage amplitude of the bit address selection signal into a write voltage Vw1, and switches 603 and 604 for driving the bit line. The word line driving circuit 102 includes a level shift circuit 606 for converting the voltage amplitude of the word address selection signal 605 and the bit address selection signal into a write voltage Vw2, and switches 607 and 608 for driving the word lines. Since the number of level shift circuits and switches is larger than the configurations shown in the third and fourth embodiments, the storage device is increased in size.

(Embodiment 5)
In this embodiment mode, a semiconductor device including a semiconductor memory device will be described as an application example of the semiconductor memory device of the present invention.

  The semiconductor device in this embodiment has a memory circuit therein, stores necessary information in the memory circuit, and exchanges information with the outside using non-contact means, for example, wireless communication. Utilizing this feature, the semiconductor device in this embodiment has uses such as an individual authentication system that stores individual information such as articles and recognizes the articles by reading the information. In order to use it, the individual information data is stored to identify the article, and therefore higher reliability is required.

  A structure of the semiconductor device in this embodiment is described with reference to FIGS. FIG. 7 is a block diagram illustrating a configuration of the semiconductor device according to the present embodiment.

  As shown in FIG. 7, the semiconductor device 700 includes an antenna 704 that receives a wireless signal 703 transmitted from an antenna 702 connected to a reader / writer 701 (referred to as a wireless communication device or an interrogator). The semiconductor device 700 includes a rectifier circuit 705, a constant voltage circuit 706, a demodulation circuit 707, a modulation circuit 708, a logic circuit 709, a semiconductor memory device 710, and a ROM 711. Note that there are three major data transmission formats: an electromagnetic coupling method in which a pair of coils are arranged facing each other to communicate by mutual induction, an electromagnetic induction method in which communication is performed by an induction electromagnetic field, and a radio wave method in which communication is performed using radio waves. In this embodiment, any system can be applied.

  Next, the configuration of each circuit will be described. The antenna 704 is for transmitting and receiving a radio signal 703 to and from the antenna 702 connected to the reader / writer 701. The rectifier circuit 705 rectifies an input AC signal generated by receiving a radio signal by the antenna 704, for example, half-end double-voltage rectification, and smoothes the rectified signal by a capacitive element provided at a subsequent stage. This is a circuit for generating an input potential. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 705. The limiter circuit is a circuit for controlling the input AC signal not to be input to a subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large. The constant voltage circuit 706 is a circuit for generating a stable power supply voltage from the input potential and supplying it to each block. Further, the constant voltage circuit 706 may include a reset signal generation circuit inside. The reset signal generation circuit is a circuit for generating a reset signal of the logic circuit 709 using a stable rise of the power supply voltage. The demodulation circuit 707 is a circuit for demodulating an input AC signal by detecting an envelope and generating a demodulated signal. The logic circuit 709 is a circuit for analyzing and processing the demodulated signal. The semiconductor memory device 710 is a semiconductor memory device that has the circuit configuration described in the above embodiment and can write data only once in accordance with processing. The ROM 711 is a circuit for storing a unique number (ID) and outputting it according to processing. Note that the ROM 711 may be provided as necessary. The modulation circuit 708 is a circuit for performing modulation in accordance with data output from the antenna 704.

  In this embodiment mode, the semiconductor memory device of the present invention can be mounted as the semiconductor memory device 710 of the semiconductor device 700. With the structure including the semiconductor memory device of the present invention, the number of wirings can be reduced, miniaturization can be achieved, and malfunction during data writing or reading can be reduced.

  Note that this embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 6)
In this embodiment, a method for manufacturing a semiconductor device including an antifuse-type semiconductor memory device is described below with reference to FIGS. 8A to 8D and FIGS. 9A to 9C. explain. Here, an example of manufacturing a semiconductor device in which a logic circuit portion 1550, a semiconductor memory circuit portion 1552, and an antenna portion 1554 are provided over the same substrate is shown. In the logic circuit portion 1550, circuits using thin film transistors are integrated. In the semiconductor memory circuit portion 1552, a memory cell is configured by a plurality of pin-type diodes and antifuses. For convenience, two thin film transistors constituting the logic circuit portion 1550, one pin-type diode and one antifuse constituting the semiconductor memory circuit portion 1552, and one capacitor and one thin film transistor constituting the antenna portion 1554 are cross sections. The figure is shown. Note that each element shown in the cross-sectional view in this embodiment is described with an exaggerated scale in order to clearly describe the structure.

Note that in this embodiment mode, a semiconductor device is described as an overall device that can function using semiconductor characteristics.

  First, a metal layer 1502 serving as a separation layer is formed over the supporting substrate 1501. A glass substrate is used as the support substrate 1501. As the metal layer 1502, a 30-200 nm tungsten layer, tungsten nitride layer, or molybdenum layer obtained by a sputtering method is used.

  Next, the surface of the metal layer 1502 is oxidized to form a metal oxide layer. The metal oxide layer may be formed by oxidizing the surface of the metal layer 1502 using pure water or ozone water, or by oxidizing the surface of the metal layer 1502 with oxygen plasma. Alternatively, the metal oxide layer may be formed by heating in an atmosphere containing oxygen. Alternatively, the metal oxide layer may be formed in a step of forming an insulating layer formed over the metal layer 1502 to be a peeling layer later. For example, when a silicon oxide layer or a silicon oxynitride layer is formed as the insulating layer by a plasma CVD method, the surface of the metal layer 1502 is oxidized to form a metal oxide layer. Note that the metal oxide layer is not shown here.

Next, a first insulating layer 1503 is formed over the metal layer 1502. As the first insulating layer 1503, an insulating layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer is formed. As an example of the first insulating layer 1503, a silicon nitride oxide layer with a thickness of 50 nm to 100 nm formed using SiH ₄ , NH ₃ , and N ₂ O as a reaction gas by a plasma CVD method, SiH ₄ , and N ₂ A two-layer structure of a silicon oxynitride layer with a thickness of 100 nm to 150 nm formed using O as a reaction gas can be given. In the case where the first insulating layer 1503 has a stacked structure, it is preferable that at least one layer be a silicon nitride layer or a silicon oxynitride layer with a thickness of 10 nm or less. Alternatively, a three-layer structure in which a silicon nitride oxide layer, a silicon oxynitride layer, and a silicon nitride layer are sequentially stacked may be formed. The first insulating layer 1503 functions as a base insulating layer; Further, a base insulating layer such as a silicon oxide layer or a silicon nitride layer may be provided between the separation layer (here, the metal layer 1502) and the substrate.

  Next, a semiconductor layer is formed over the first insulating layer 1503. The semiconductor layer is formed by depositing a semiconductor layer having an amorphous structure by a CVD method such as an LPCVD method or a plasma CVD method, or a sputtering method, and then selectively etching the crystalline semiconductor layer obtained by crystallization. Process into desired shape. As a crystallization method, a laser crystallization method, a thermal crystallization method using an RTA or a furnace annealing furnace, a crystallization method using a metal element that promotes crystallization such as nickel, or the like may be used. Note that when the semiconductor layer is formed by a plasma CVD method, the first insulating layer 1503 and the semiconductor layer having an amorphous structure can be continuously formed without being exposed to the air. The semiconductor layer is formed with a thickness of 25 nm to 80 nm (preferably 30 nm to 70 nm). The material of the semiconductor layer is not particularly limited, but is preferably formed of silicon or silicon germanium.

A continuous wave laser can also be used for crystallization of a semiconductor layer having an amorphous structure. In crystallization of a semiconductor layer having an amorphous structure, in order to obtain a crystal having a large grain size, a solid-state laser capable of continuous oscillation is used, and the second to fourth harmonics of the solid-state laser are applied. preferable. Typically, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) may be applied. When a continuous wave laser is used, a laser beam emitted from a continuous wave YVO ₄ laser having an output of 10 W is converted into a harmonic by a non-linear optical element. There is also a method of emitting harmonics by putting a YVO ₄ crystal and a nonlinear optical element in a resonator. Then, it is preferably formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and irradiated to the object to be processed. The energy density at this time needs to be about 0.01 MW / cm ^{2 to} 100 MW / cm ² (preferably 0.1 MW / cm ^{2 to} 10 MW / cm ² ). Then, irradiation may be performed by moving the semiconductor layer relative to the laser beam at a speed of about 10 cm / sec to 2000 cm / sec.

Note that if necessary, a small amount of an impurity element (boron or phosphorus) is added to the semiconductor layer in order to control a threshold value of a thin film transistor to be completed later. Here, boron is added using an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation.

  Next, the oxide film on the surface of the semiconductor layer is removed with an etchant containing hydrofluoric acid, and at the same time, the surface of the semiconductor layer is washed. Then, a second insulating layer that covers the semiconductor layer is formed. The second insulating layer is formed using a CVD method or a sputtering method and has a thickness of 1 nm to 200 nm. Preferably, after forming a single layer or a stacked structure of an insulating layer containing silicon whose thickness is as thin as 10 nm to 50 nm, surface nitriding treatment is performed using plasma excited by microwaves. The second insulating layer functions as a gate insulating layer of a thin film transistor to be formed later.

  Note that a high-concentration impurity element (boron or phosphorus) is added to the semiconductor layer so that the semiconductor layer in a region to be a capacitor later functions as a conductor. At this time, the region other than the capacitor may be covered with a resist mask. In addition, a p-type impurity region, an intrinsic semiconductor region, and an n-type impurity region are also formed in a semiconductor layer to be a pin-type diode using a resist mask or the like.

  Next, a gate electrode 1504, a gate electrode 1505, a gate electrode 1506, a gate electrode 1507, and a first electrode 1509 to be a lower electrode of an antifuse are formed over the second insulating layer. A conductive layer with a thickness of 100 nm to 500 nm obtained by a sputtering method is selectively etched and processed into a desired shape, whereby a gate electrode 1504 to a gate electrode 1507 and a first electrode 1509 are obtained.

  As materials for the gate electrode 1504 to the gate electrode 1507 and the first electrode 1509, simple substances such as tungsten, titanium, aluminum, nickel, chromium, molybdenum, tantalum, cobalt, zirconium, vanadium, palladium, hafnium, platinum, and iron, Alternatively, a single layer or a laminated structure of a material selected from these alloys or compounds is used. Preferably, a material that forms silicide by reacting with silicon is used. However, the gate electrode of the thin film transistor is preferably a refractory metal, specifically tungsten or molybdenum. In the case where the gate electrodes 1504 to 1507 and the first electrode 1509 have a stacked structure, the upper material layer may be any material as described above, and the lower material layer on the gate insulating layer side may be phosphorus or the like. Alternatively, a polysilicon layer to which the impurity element is added may be used. In addition, since the first electrode 1509 is used for an antifuse electrode in contact with amorphous silicon, a material which reacts with silicon is preferably used.

Next, a resist mask is formed so as to cover the semiconductor layer in the region to be the p-channel transistor and the pin-type diode, and the gate electrode 1505, the gate electrode 1506, and the gate electrode 1507 are masked on the semiconductor layer in the region to be the n-channel transistor. A low concentration impurity region is formed by introducing an impurity element. As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity can be used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. Here, an impurity region exhibiting n-type is formed by introducing phosphorus into a semiconductor layer in a region to be an n-channel transistor so as to be contained at a concentration of 1 × 10 ¹⁵ / cm ³ to 1 × 10 ¹⁹ / cm ^3. .

Next, the resist mask is removed, a resist mask is formed so as to cover a part of the semiconductor layer and the pin-type diode that are to be n-channel transistors, and the p-type of the semiconductor layer and the pin-type diode that are to be p-channel transistors. A p-type impurity region is formed by introducing an impurity element into the region to be the impurity region using the gate electrode 1504 as a mask. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, by introducing boron (B) at a concentration of 1 × 10 ¹⁹ / cm ³ to 1 × 10 ²⁰ / cm ³ into a semiconductor layer in a region to be a p-channel transistor, an impurity exhibiting p-type conductivity Regions can be formed. As a result, a channel formation region 1516a and a pair of p-type impurity regions 1514a and a p-type semiconductor region 1514b are formed in a semiconductor layer in a region to be a pin-type diode in a self-aligned manner in a semiconductor layer in a region to be a p-channel transistor. The The p-type impurity region 1514a functions as a source region or a drain region.

  Next, sidewall insulating layers 1510 and 1511 are formed on side surfaces of the gate electrodes 1504 to 1507 and the first electrode 1509. As a method for manufacturing the sidewall insulating layer 1510 and the sidewall insulating layer 1511, first, a plasma CVD method, a sputtering method, or the like is performed so as to cover the second insulating layer, the gate electrode 1504 to the gate electrode 1507, and the first electrode 1509. Thus, a third insulating layer is formed by stacking a single layer or a layer including a layer containing silicon, silicon oxide, or silicon nitride, or a layer containing an organic material such as an organic resin. Next, the third insulating layer is selectively etched by anisotropic etching mainly in the vertical direction, whereby the insulating layers (sides in contact with the side surfaces of the gate electrode 1504 to the gate electrode 1507 and the first electrode 1509) A wall insulating layer 1510 and a sidewall insulating layer 1511) are formed. Note that at the same time as the formation of the sidewall insulating layer 1510, part of the second insulating layer is removed by etching. By removing a part of the second insulating layer, a gate insulating layer 1512 is formed below the gate electrodes 1504 to 1507 and the sidewall insulating layer 1510. Further, by removing a part of the second insulating layer, the insulating layer 1513 remains below the first electrode 1509 and below the sidewall insulating layer 1511.

Next, a resist mask is formed so as to cover a semiconductor layer to be a p-channel transistor and a part of the pin-type diode, and a gate electrode 1505, a gate electrode 1506, a gate electrode 1507, and A high-concentration impurity region is formed by introducing an impurity element using the sidewall insulating layer 1510 as a mask. After the introduction of the impurity element, the resist mask is removed. Here, phosphorus (P) is contained at a concentration of 1 × 10 ¹⁹ / cm ³ to 1 × 10 ²⁰ / cm ³ in a semiconductor layer in a region to be an n-channel transistor and a semiconductor layer in a region to be a pin-type diode. By introducing the n-type impurity region, a high-concentration impurity region and an n-type impurity region exhibiting n-type can be formed. As a result, a channel formation region 1521a or a channel formation region 1521c and a pair of low-concentration impurity regions 1519a or a pair of low-concentration impurity regions 1519c functioning as LDD regions are self-aligned with a semiconductor layer in a region to be an n-channel transistor. Then, a pair of high-concentration impurity regions 1517a or high-concentration impurity regions 1517c functioning as a source region or a drain region is formed. At the same time, the first impurity region 1521b, the second impurity region 1519b, and the third impurity region 1517b are formed in a self-aligned manner in the semiconductor layer in the region to be a capacitor. At the same time, an n-type impurity region 1515a and an intrinsic semiconductor region 1516b are formed in a semiconductor layer in a region to be a pin-type diode. The first impurity region 1521b is formed in a region overlapping with the gate electrode 1506 with the gate insulating layer interposed therebetween. Note that a high-concentration impurity element is selectively added to the first impurity region 1521b before the gate electrode 1506 is formed. Accordingly, the first impurity region 1521b has a higher impurity concentration than the channel formation region 1521a and the channel formation region 1521c. Note that the low-concentration impurity region 1519a and the low-concentration impurity region 1519c, which function as an LDD region, and the second impurity region 1519b are formed below the sidewall insulating layer 1510.

  Note that here, a structure is shown in which an LDD region is formed in a semiconductor layer included in an n-channel transistor and an LDD region is not provided in a semiconductor layer included in a p-channel transistor. LDD regions may be formed in both semiconductor layers of the p-channel transistor.

  Next, after the fourth insulating layer 1522 containing hydrogen is formed by a sputtering method, an LPCVD method, a plasma CVD method, or the like, activation treatment and hydrogenation treatment of the impurity element added to the semiconductor layer are performed. . For the activation treatment and hydrogenation treatment of the impurity element, heat treatment in a furnace (heat treatment at 300 ° C. to 550 ° C. for 1 hour to 12 hours) or an RTA method using a lamp light source is used. As the fourth insulating layer 1522 containing hydrogen, for example, a silicon nitride oxide layer obtained by a plasma CVD method is used. Here, the thickness of the fourth insulating layer 1522 containing hydrogen is 50 nm to 200 nm. In addition, when the semiconductor layer is crystallized using a metal element that promotes crystallization, typically nickel, gettering that reduces nickel in the channel formation region at the same time as activation can be performed. . Note that the fourth insulating layer 1522 containing hydrogen is a first layer of an interlayer insulating layer.

  Next, a fifth insulating layer 1523 which is the second interlayer insulating layer is formed by a sputtering method, an LPCVD method, a plasma CVD method, or the like. As the fifth insulating layer 1523, a single layer or a stacked layer of insulating layers such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer is used. Here, the thickness of the fifth insulating layer 1523 is 300 to 800 nm.

  Next, a resist mask is formed over the fifth insulating layer 1523, and the fourth insulating layer 1522 and the fifth insulating layer 1523 are selectively etched, so that a first opening 1520 reaching the first electrode 1509 is formed. Then, the resist mask is removed after the etching. The diameter of the first opening 1520 may be about 1 μm to about 6 μm, and in this embodiment, the diameter of the first opening 1520 is 2 μm.

  A cross-sectional view of the semiconductor device manufactured through the preceding steps corresponds to FIG.

  Next, a silicon oxynitride layer and an amorphous silicon layer are stacked using a sputtering method, an LPCVD method, a plasma CVD method, or the like. In this embodiment, an amorphous silicon layer with a thickness of 15 nm and a silicon oxynitride layer with a thickness of 6 nm are sequentially stacked using a plasma CVD method. Next, a resist mask is formed, and the amorphous silicon layer and the silicon oxynitride layer are selectively etched, so that an amorphous silicon layer 1524 a and a silicon oxynitride layer 1524 b overlapping with the first opening 1520 are formed. The amorphous silicon layer 1524a and the silicon oxynitride layer 1524b serve as a resistance material layer of the antifuse element. Then, the resist mask is removed after the etching.

  A cross-sectional view of the semiconductor device manufactured through the preceding steps corresponds to FIG.

  Next, a resist mask is formed, and the fourth insulating layer 1522 and the fifth insulating layer 1523 are selectively etched, so that a contact hole reaching the semiconductor layer, a contact hole reaching the gate electrode, and a first hole reaching the first electrode 1509 are formed. Two openings are formed respectively. Then, the resist mask is removed after the etching.

  A cross-sectional view of the semiconductor device through the steps up to here corresponds to FIG.

  Next, the surface of the exposed semiconductor layer and the exposed first surface of the semiconductor layer are removed simultaneously with the removal of the oxide film on the exposed surface of the semiconductor layer and the exposed surface of the first electrode 1509 with an etchant containing hydrofluoric acid. The surface of the electrode 1509 is cleaned.

  Next, in order to form an upper electrode of an antifuse, an electrode of a pin-type diode, a source electrode and a drain electrode of a thin film transistor, a conductive layer is formed by a sputtering method. This conductive layer is made of a simple substance such as tungsten, titanium, aluminum, nickel, chromium, molybdenum, tantalum, cobalt, zirconium, vanadium, palladium, hafnium, platinum, iron, or a single layer of these alloys or compounds, or a laminate thereof. Form with. However, since this conductive layer is used for a source electrode and a drain electrode of a thin film transistor, it is preferable to use a material having a relatively low contact resistance value with a semiconductor layer included in the thin film transistor. For example, a three-layer structure of a titanium layer, an aluminum layer containing a small amount of silicon, and a titanium layer, or a three-layer structure of a titanium layer, an aluminum alloy layer containing nickel and carbon, and a titanium layer is used. In this embodiment, a three-layer stack of a titanium layer with a thickness of 100 nm, a pure aluminum layer with a thickness of 350 nm, and a titanium layer with a thickness of 100 nm is used. In this embodiment, the tungsten layer is used as the material for the lower electrode of the antifuse, and the titanium layer is used as the upper electrode. However, the resistance material layer can be changed from high resistance to low resistance. If possible, the material is not particularly limited, and the same material may be used for the lower electrode and the upper electrode of the antifuse. When the same material is used for the lower and upper electrodes of the antifuse, tungsten, titanium, aluminum, nickel, chromium, molybdenum, tantalum, cobalt, zirconium, vanadium, palladium, hafnium, platinum, iron, etc., or alloys thereof Or it forms with the single layer of the material chosen from a compound, or laminated structure.

  Next, a resist mask is formed and the conductive layer is selectively etched, so that the conductive layer 1525, the conductive layer 1526, the conductive layer 1527, the conductive layer 1528, the conductive layer 1531, and the conductive layer 1532 function as a source electrode or a drain electrode. , Conductive layer 1533, conductive layer 1534, wiring 1529 serving as an electrode of the pin diode element, wiring 1530, wiring 1535 serving as a gate lead wiring, wiring 1536, wiring 1537, wiring 1538, wiring 1539, and second of the semiconductor memory circuit portion The first electrode 3540, the third electrode 1541, and the fourth electrode 1542 of the antenna portion are formed. The second electrode 1540 overlaps with the first opening 1520 and becomes the upper electrode of the antifuse. The third electrode 1541 overlaps with the second opening and is electrically connected to the first electrode 1509. Note that although not shown here, the fourth electrode 1542 is electrically connected to the thin film transistor of the antenna portion. Then, the resist mask is removed after the etching.

  A cross-sectional view of the semiconductor device manufactured through the preceding steps corresponds to FIG. In this embodiment, the thin film transistor of the logic circuit portion 1550, the pin-type diode 1559 and the antifuse 1560 of the semiconductor memory circuit portion 1552, and the thin film transistor of the antenna portion 1554 can be formed over the same substrate. Here, a p-channel transistor and an n-channel transistor provided in the logic circuit portion 1550, a pin-type diode 1559 and an antifuse 1560 provided in the semiconductor memory circuit portion 1552, a capacitor provided in the antenna portion 1554, and an n-channel transistor A cross-sectional view is shown. Note that the present invention is not particularly limited, and the thin film transistor provided in the semiconductor memory circuit portion 1552 may be a p-channel transistor. The antenna portion 1554 may be provided with a p-channel transistor. Here, one n-channel transistor is illustrated for convenience.

  Next, a sixth insulating layer 1543 that covers the thin film transistor of the logic circuit portion 1550, the pin-type diode and antifuse element of the semiconductor memory circuit portion 1552, and the thin film transistor of the antenna portion 1554 is formed. As the sixth insulating layer 1543, an insulating layer containing silicon oxide or an insulating layer made of an organic resin can be used; however, in order to improve the reliability of the semiconductor device, an insulating layer containing silicon oxide is preferably used. In the case where an antenna to be formed later is formed by a screen printing method, it is desirable to have a flat surface. Therefore, it is preferable to use an insulating layer made of an organic resin using a coating method. The material for forming the sixth insulating layer 1543 may be selected as appropriate by the practitioner. Further, an antenna to be formed later may be formed up to a region overlapping with the logic circuit portion 1550 and the semiconductor memory circuit portion 1552. In this case, the sixth insulating layer 1543 also functions as an interlayer insulating layer for insulation from the antenna. In the case of a ring-shaped (for example, a loop antenna) or a spiral antenna, it is preferable to provide a sixth insulating layer 1543 so that one of both ends of the antenna is routed by wiring formed in a lower layer. However, in the case where a microwave method is applied and an antenna having a linear shape (for example, a dipole antenna) or a flat shape (for example, a patch antenna) is used, the antenna to be formed later includes a logic circuit portion and a semiconductor memory circuit portion. The sixth insulating layer 1543 is not necessarily provided because it can be arranged so as not to overlap.

  Next, a resist mask is formed, and the sixth insulating layer 1543 is selectively etched, so that a third opening reaching the third electrode 1541 and a fourth opening reaching the fourth electrode 1542 are formed. Then, the resist mask is removed after the etching.

  A cross-sectional view of the semiconductor device manufactured through the preceding steps corresponds to FIG.

  Next, a metal layer is formed over the sixth insulating layer 1543. As the metal layer, a single layer selected from Ti, Ni, and Au or a laminate thereof is used. Next, a resist mask is formed and the metal layer is selectively etched to form a lead wiring 1544 and an antenna base layer 1545 in the lead wiring portion 1562 of the first electrode 1509. Note that the lead wiring 1544 and the base layer 1545 here can be selectively formed by a sputtering method using a metal mask without using a resist mask. By providing the antenna base layer 1545, a wide contact area with the antenna can be secured. Further, depending on the layout of the circuit design, the lead wiring 1544 may not be particularly formed.

  A cross-sectional view of the semiconductor device manufactured through the preceding steps corresponds to FIG.

  Next, the antenna 1546 is formed over the antenna base layer 1545. The antenna 1546 can be formed by forming a metal layer such as Al or Ag by a sputtering method and then selectively etching the metal layer and processing it into a desired shape, or a screen printing method. The screen printing method refers to a base made of a metal or polymer compound fiber mesh, an ink or paste placed on a screen plate having a predetermined pattern formed of a photosensitive resin, rubber, plastic called squeegee, or This is a method of transferring to a workpiece placed on the opposite side of the screen plate using a metal blade. The screen printing method has an advantage that pattern formation in a relatively large area can be realized at low cost.

  A cross-sectional view of the semiconductor device manufactured through the preceding steps corresponds to FIG. In this embodiment, the thin film transistor of the logic circuit portion 1550, the pin diode and antifuse of the semiconductor memory circuit portion 1552, and the thin film transistor and antenna of the antenna portion 1554 can be formed over the same substrate.

  Next, peeling is performed to remove the metal layer 1502 and the support substrate 1501. Separation can be caused in the metal oxide layer, at the interface between the first insulating layer 1503 and the metal oxide layer, or at the interface between the metal oxide layer and the metal layer 1502, and becomes a semiconductor device with a relatively small force. An upper layer side than the first insulating layer 1503 can be peeled off from the supporting substrate 1501. In addition, when removing the metal layer 1502 and the support substrate 1501, a fixed substrate may be bonded to the side where the antenna is provided.

  Next, one sheet on which a plurality of semiconductor devices are formed is divided by a cutter, dicing, or the like, and cut into individual semiconductor devices. Further, if a method of picking up and peeling semiconductor devices one by one at the time of peeling, this dividing step is not particularly necessary.

  Next, the semiconductor device is fixed to a sheet-like substrate. As the sheet-like substrate, plastic, paper, prepreg, ceramic sheet or the like can be used. The semiconductor device may be fixed between two sheet-like bases, or may be fixed to one sheet-like base with an adhesive layer. As the adhesive layer, various curable adhesives such as a reactive curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive can be used. In addition, a semiconductor device can be provided in the middle of paper formation, and the semiconductor device can be provided inside one piece of paper.

  As described above, by manufacturing a semiconductor device by attaching the semiconductor device to a sheet-like substrate, it is possible to provide a semiconductor device that is thin and light and is not easily broken even when dropped. In addition, since a flexible substrate is used as the sheet-like substrate, it can be bonded onto a curved surface or an irregular shape, and various uses can be realized. Further, by reusing the substrate 1501, a semiconductor device can be provided at lower cost.

  Further, the substrate 1501 used at the time of manufacturing can be left. In this case, the substrate may be thinned by polishing or grinding the substrate so that the substrate bends.

  The memory of the semiconductor device that has undergone the above steps is constituted by the semiconductor memory device according to the present invention. By using a semiconductor device including the semiconductor memory device of the present invention, the number of wirings can be reduced, the size can be reduced, and malfunction during data writing or reading can be reduced.

  The semiconductor device of this embodiment functions as a wireless chip, and is small, thin, lightweight, and flexible. Therefore, even if the semiconductor device is attached to an article, the appearance, aesthetics, and quality can be maintained.

  Note that this embodiment can be combined with any of the other embodiments as appropriate. .

(Embodiment 7)

  In this embodiment, an example of usage of a semiconductor device including the semiconductor memory device of the present invention described in Embodiments 5 and 6 is described.

  As shown in FIG. 10, the semiconductor device has a wide range of uses. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 10 (A)), packaging Containers (wrapping paper, bottles, etc., see FIG. 10C), recording media (DVD software, video tape, etc., see FIG. 10B), vehicles (bicycles, see FIG. 10D), Items such as personal items (such as bags and glasses), foods, plants, animals, human bodies, clothing, daily necessities, or electronic devices (liquid crystal display devices, EL display devices, television devices, or mobile phones), Alternatively, it can be used by being provided on a tag (see FIGS. 10E and 10F) attached to each article.

  The semiconductor device 1700 of the present invention is fixed to an article by being mounted on a printed board, pasted on a surface, or embedded. For example, if it is a book, it is embedded in paper, or if it is a package made of an organic resin, it is embedded in the organic resin and fixed to each article. Since the semiconductor device 1700 of the present invention realizes a small size, a thin shape, and a light weight, the design of the article itself is not impaired even after being fixed to the article. In addition, by providing the semiconductor device 1700 of the present invention in bills, coins, securities, bearer bonds, certificate documents, etc., an authentication function can be provided, and forgery can be prevented by using this authentication function. be able to. In addition, by attaching the semiconductor device of the present invention to packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., it is possible to improve the efficiency of systems such as inspection systems. . Moreover, even if it is vehicles, the security property with respect to theft etc. can be improved by attaching the semiconductor device of this invention.

  As described above, since a semiconductor device including the semiconductor memory device of the present invention is used for each application described in this embodiment, data used for information exchange can be maintained as an accurate value. Further, the authenticity of the article or the reliability of the security can be improved.

  Note that this embodiment can be combined with any of the other embodiments as appropriate.

FIG. 6 illustrates Embodiment 1; FIG. 6 illustrates Embodiment 1; FIG. 6 illustrates Embodiment 2. FIG. 6 illustrates Embodiment 3. FIG. 10 illustrates Embodiment 4; The figure explaining the drive method used as a comparison FIG. 9 illustrates Embodiment 5. FIG. 6 illustrates Embodiment 6. FIG. 6 illustrates Embodiment 6. FIG. 10 illustrates Embodiment 7. 4 is a top view of the memory cell 106. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor memory device 101 Bit line drive circuit 102 Word line drive circuit 103 Memory cell array 104 Pin type diode 105 Antifuse 106 Memory cell 201 Arrow 301 Arrow 401 Bit address selection signal 402 Level shift circuit 403 Switch 404 Word address selection signal 405 Switch 406 Bit line 407 Word line 408 Bit line 409 Word line 501 Bit address selection signal 502 Switch 503 Word address selection signal 504 Level shift circuit 505 Switch 506 Bit line 507 Word line 508 Bit line 509 Word line 601 Bit address selection signal 602 Level shift circuit 603 Switch 604 Switch 605 Word address selection signal 606 Level shift circuit 607 Switch 608 Switch Chi 609 bit lines 610 word lines 611 bit lines 612 word lines 700 semiconductor device 701 reader / writer 702 antenna 703 radio signal 704 antenna 705 rectifier circuit 706 the constant voltage circuit 707 demodulating circuit 708 modulation circuit 709 logic circuit 710 a semiconductor memory device 711 ROM
1501 Support substrate 1502 Metal layer 1503 Insulating layer 1504 Gate electrode 1505 Gate electrode 1506 Gate electrode 1507 Gate electrode 1509 Electrode 1510 Side wall insulating layer 1511 Side wall insulating layer 1512 Gate insulating layer 1513 Insulating layer 1520 Opening 1522 Insulating layer 1523 Insulating layer 1525 Conductive Layer 1526 conductive layer 1527 conductive layer 1528 conductive layer 1529 wiring 1530 wiring 1531 conductive layer 1532 conductive layer 1533 conductive layer 1534 conductive layer 1535 wiring 1536 wiring 1537 wiring 1538 wiring 1539 wiring 1540 electrode 1541 electrode 1542 electrode 1543 insulating layer 1544 under wiring 1545 Formation 1546 Antenna 1550 Logic circuit unit 1552 Semiconductor memory circuit unit 1554 Antenna unit 1559 Pin type diode 1 60 Antifuse 1562 Lead wiring portion 1700 Semiconductor device 1514a p-type impurity region 1514b p-type semiconductor region 1515a n-type impurity region 1516a channel formation region 1516b intrinsic semiconductor region 1517a high-concentration impurity region 1517b impurity region 1517c high-concentration impurity region 1519a low-concentration impurity Region 1519b Impurity region 1519c Low-concentration impurity region 1521a Channel formation region 1521b Impurity region 1521c Channel formation region 1524a Amorphous silicon layer 1524b Silicon oxynitride layer

Claims (7)

A memory cell having a diode element and a memory element;
A plurality of signal lines composed of bit lines and word lines;
In a driving method of an antifuse type semiconductor memory device having
A driving method of a semiconductor memory device, wherein the bit line and the word line to which writing is not selected are set in a floating state during a writing operation. A memory cell having a diode element and a memory element;
A plurality of signal lines composed of bit lines and word lines;
In a driving method of an antifuse type semiconductor memory device having
During the write operation, the bit line that is selected for writing is set to a positive potential, the word line that is selected for writing is set to the ground potential, and the bit line and the word line that are not selected for writing are set in a floating state. A method for driving a semiconductor memory device. A memory cell having a diode element and a memory element;
A plurality of signal lines composed of bit lines and word lines;
In a driving method of an antifuse type semiconductor memory device having
During the write operation, the bit line that is selected for writing is set to a positive potential, the word line that is selected for writing is set to a negative potential, and the bit line and the word line that are not selected for writing are set in a floating state. A method for driving a semiconductor memory device.   4. The method of driving a semiconductor memory device according to claim 1, wherein the diode element is a pin diode.   4. The method for driving a semiconductor memory device according to claim 1, wherein the diode element is a pn-type diode. 5.   6. The method for driving a semiconductor memory device according to claim 1, wherein the semiconductor memory device is formed over a flexible substrate.   7. The method of driving a semiconductor memory device according to claim 1, wherein the semiconductor memory device is used for a wireless chip.

Images