JP5296360B2 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device mounted with memory which can be driven within a range of a current value and a voltage value which can be generated from a wireless signal, and to provide a rewritable memory to which data can be written any time after manufacturing the semiconductor device. <P>SOLUTION: An antenna, antifuse-type ROM and a driver circuit are formed on an insulating substrate. Of a pair of electrodes included in the antifuse-type ROM, the other of the pair of the electrodes is also formed through the same step and of the same material as a source electrode and a drain electrode of a transistor included in the driver circuit. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device having a circuit formed of a thin film transistor (hereinafter referred to as TFT) and a manufacturing method thereof. For example, the present invention relates to an electronic apparatus in which an electro-optical device typified by a liquid crystal display panel or a light-emitting display device having an organic light-emitting element is mounted as a component.

  Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

Conventionally, various types of memories have been proposed. Typical memories include a memory including a magnetic tape and a magnetic disk, a RAM capable of writing and reading, and a ROM (Read Only Memory) dedicated to reading.

Conventional ROMs include a mask ROM that stores information using a mask in an IC manufacturing process, a fuse-type ROM that stores information by fusing fuse elements with an electric current after manufacturing an IC chip, and an insulator short-circuited with an electric current after manufacturing an IC chip. An antifuse-type ROM that stores information by storing the information may be used.

Since the mask ROM stores information with the mask in the IC manufacturing process, a mask corresponding to the information to be written has to be prepared, which increases the manufacturing cost. In addition, the fuse-type ROM may cause a malfunction due to dust generated when the fuse element is melted.

In addition, the antifuse-type ROM is advantageous over other ROMs in that it does not require a mask corresponding to information to be written at the time of manufacture, and dust is not generated when information is written to the memory. Note that the fuse-type ROM and the anti-fuse-type ROM are different from the mask ROM and can be additionally written. In addition, the fuse-type ROM and the anti-fuse-type ROM can also be called a write-once-ready many memory. As an example of an antifuse-type ROM formed on a silicon substrate, there is a technique described in Patent Document 1.

A cross-sectional view of an antifuse-type ROM disclosed in Patent Document 1 is shown in FIG. In FIG. 15, a silicon substrate 50 on which an nMOS transistor is formed, an amorphous silicon film 53, a tungsten film 54, a tungsten film 54 ′, and an Al—Si—Cu wiring 55 are formed. Although Patent Document 1 does not clearly indicate reference numerals 51 and 52, the reference numeral 51 is probably an n + drain region, and the reference numeral 52 is a SiO ₂ film formed by a CVD method. Patent Document 1 is characterized in that a stacked film of a tungsten film 54 ′, an amorphous silicon film 53, and a tungsten film 54 is continuously formed by using a multi-chamber system without being exposed to the atmosphere.

In recent years, a semiconductor device having a wireless communication function, specifically, a wireless chip has attracted attention because a large market is expected. Such a wireless chip may be called an ID tag, an IC tag, an IC chip, an RF (Radio Frequency) tag, a wireless tag, an electronic tag, or an RFID (Radio Frequency Identification) depending on the application.

The configuration of the wireless chip includes an interface, a memory, a control unit, and the like. As the memory, a RAM that can be written and read and a ROM that is dedicated to reading are used, and are selectively used according to the purpose. Specifically, a memory area is allocated for each specific application, and the access right is managed for each application and each directory. In order to manage the access right, the wireless chip has a verification unit that compares and collates with a password of the application, and has a control unit that gives the user an access right related to the application that matches the password as a result of the comparison and collation by the verification unit. Such a wireless chip is formed from a silicon wafer, and integrated circuits such as a memory circuit and an arithmetic circuit are integrated on a semiconductor substrate.

When a card (so-called IC card) on which such a wireless chip is mounted is compared with a magnetic card, the IC card has a large memory capacity, can be provided with an arithmetic function, has high authenticity, and is extremely falsified. It has the merit of being difficult. Therefore, the IC card is suitable for managing personal information. As a memory mounted on an IC card, a ROM dedicated to reading is often used so that it cannot be tampered with.
JP 7-297293 A

A conventional wireless chip is manufactured using an expensive silicon wafer like a microprocessor or a semiconductor memory. Therefore, there was a limit to reducing the unit price of the wireless chip. In particular, the memory area required for the wireless chip occupies a large area in the silicon chip, and it is necessary to reduce the area occupied by the memory area without changing the storage capacity in order to reduce the unit cost of the chip. Yes. Further, although the cost reduction can be expected by making the silicon chip minute, as the silicon chip is further miniaturized, the mounting cost increases. In order to distribute chips to the market, it is very important to lower the chip unit price, which is one of the priorities in product production.

In the wireless chip, when the terminal of the silicon chip and the antenna are connected by ACF or the like, the rate of thermal expansion at a high temperature or the rate of thermal contraction at a low temperature varies depending on the member. Stress is generated. Since the wireless chip is attached to an article, considering the exposure to various environments, disconnection may occur at the connection between the terminal of the silicon chip and the antenna due to thermal stress.

Further, even if a conventional wireless chip is made into a small piece, silicon is used as a structure, and thus is not suitable for being attached to a curved surface of an article. When a silicon chip is mounted on a base made of a flexible material, when the base is bent according to the curved surface of the article, there is a possibility that a portion connecting the silicon chip and the antenna of the base is destroyed. There is also a method for grinding and polishing the silicon wafer itself, but there is a contradiction contradicting the reduction in manufacturing cost because the number of steps for that purpose increases. Even in the case of an IC tag attached to a product even if it is thinned, if the wireless chip is attached to a thin substrate (for example, a film piece or a paper piece), a protrusion is generated on the surface of the substrate, and the appearance is beautiful. Will be damaged. In addition, since protrusions are generated on the surface of the substrate, high-definition printing becomes difficult when printing is performed on a substrate such as a piece of paper. In addition, there is a fear that the location of the silicon chip to be altered is emphasized. Further, when the silicon chip is made into a thin piece, the mechanical strength of the silicon chip is lowered, and the silicon chip may be broken when the base is bent.

In addition, when an antifuse-type ROM is to be mounted on a wireless chip, two process orders can be considered. One is a process sequence in which information is written after manufacturing a silicon chip on which a ROM is formed, and then mounted on an antenna provided on a base to complete a wireless chip. In the case of such a process sequence, a manufacturing apparatus for writing information during the manufacturing process of the wireless chip is required. Each silicon chip is very small, and a manufacturing apparatus that supplies a current for writing different information to the ROM formed on each silicon chip requires precise alignment. Become. Therefore, the manufacturing cost is increased by this manufacturing apparatus.

As another process sequence, after mounting a silicon chip on a substrate having an antenna, a wireless signal is transmitted to a ROM formed on the silicon chip, and information is written using the wireless signal to write the wireless chip. Is the process sequence to complete the process. Compared to the process sequence described above, when such a process sequence is used, an increase in manufacturing cost can be suppressed by using a radio signal.

However, when the process sequence described later is used, the current generated from the radio signal is written into the ROM, so that the write current value and the write voltage value are limited to the ROM.

Therefore, an object of the present invention is to provide a semiconductor device equipped with a memory that can be driven within a range of a current value and a voltage value that can be generated from a radio signal. It is another object of the present invention to provide a write-once memory that can be written at any time after manufacturing a semiconductor device.

It is another object to provide a wireless chip suitable for being attached to a curved surface of an article. Another object is to reduce the manufacturing cost and lower the chip unit price without increasing the number of manufacturing processes.

In addition, since the wireless chip is required to exchange data with the reader in a short time, it is an object to provide a wireless chip with high-speed reading and few malfunctions. Another object of the present invention is to reduce the power consumption of the memory by reducing the power for reading data from the memory, thereby reducing the power consumption of the entire wireless chip.

It has been found that at least one of the above problems can be realized by forming the antifuse-type ROM on the same substrate as the drive circuit, preferably an insulating substrate. Further, according to the present invention, the antifuse-type ROM and its drive circuit are formed on the same substrate, thereby reducing noise and reducing contact resistance, thereby achieving low power consumption of the entire wireless chip. More preferably, an antenna, an antifuse-type ROM, and a driver circuit are formed over an insulating substrate. By forming these on the same substrate, a power signal can be formed based on a signal from an antenna that has received a radio signal, and the power signal can be used effectively without loss.

The antifuse-type ROM is composed of a pair of electrodes made of different materials and a silicon film sandwiched between the pair of electrodes. The material of the pair of electrodes may be any material that forms silicide by reacting with silicon, and is a simple substance such as titanium, tungsten, nickel, chromium, molybdenum, tantalum, cobalt, zirconium, vanadium, palladium, hafnium, platinum, iron, Alternatively, these alloys or compounds can be used.

In addition, of the pair of electrodes constituting the antifuse-type ROM, one electrode is formed of the same process and the same material as the gate electrode of the transistor constituting the driver circuit, thereby simplifying the process. be able to. According to the present invention, an antifuse-type ROM and its drive circuit are formed on the same substrate to reduce noise and contact resistance, thereby achieving low power consumption of the entire wireless chip. Further, since it is required to exchange data with the reader in a short time, it is preferable to use a semiconductor film having a crystal structure as a transistor of the driver circuit, that is, a TFT using a polysilicon film. In order to obtain a TFT having good electrical characteristics, it is preferable that the material of the gate electrode of the transistor is a refractory metal. Among refractory metals, a tungsten film that forms silicide by reacting with silicon is a material having a relatively large work function, and thus has a lower threshold voltage than both a p-channel transistor and an n-channel transistor. It becomes almost symmetrical. That is, it can be said that the tungsten film is suitable for a driver circuit including a CMOS circuit and suitable for one electrode of an antifuse-type ROM.

Further, among the pair of electrodes constituting the antifuse-type ROM, the other electrode is formed in the same process and with the same material as the source electrode and drain electrode of the transistor constituting the driving circuit, thereby simplifying the process. Can be achieved. Since the source electrode and the drain electrode of the transistor are formed in contact with the interlayer insulating film above the source region or the drain region, a material having high adhesion to the interlayer insulating film is preferably used. In addition, a light metal having a specific gravity of 5 or less is used for a source electrode and a drain electrode of the transistor. Since light metals such as aluminum and titanium have low electrical resistance, they are useful as wiring materials for integrated circuits. In addition, it is preferable to use a titanium film because adhesion with an insulating film or another metal film is improved. In addition, the titanium film has a lower material cost and lower electric resistance than a refractory metal. That is, it can be said that the titanium film is suitable for a source electrode and a drain electrode of a transistor, and suitable for one electrode of an antifuse-type ROM.

As described above, in order to reduce the manufacturing cost as much as possible, it is useful to use different materials for the first electrode and the second electrode which are a pair of electrodes of the antifuse-type ROM.

In addition, among the pair of electrodes constituting the antifuse-type ROM, the other electrode is formed by the same process and the same material as the connection electrode for electrically connecting the antenna and the drive circuit. The process can be simplified. By forming the antifuse-type ROM, its drive circuit, and antenna on the same substrate, noise and contact resistance can be reduced, and low power consumption of the entire wireless chip can be achieved.

As a silicon film used for the antifuse-type ROM, an amorphous silicon film, a microcrystalline silicon film, or a polycrystalline silicon film (also referred to as a polysilicon film) can be used. In addition, oxygen or nitrogen may be intentionally included in the silicon film used for the antifuse-type ROM. The amount to be included is not less than the SIMS detection lower limit, preferably 1 × 10 ¹⁵ to less than 1 × 10 ²⁰ / cm ³ by SIMS measurement. By intentionally including oxygen or nitrogen, the difference in electrical resistance before and after writing to the antifuse-type ROM can be increased. By increasing the difference in electric resistance before and after writing, a wireless chip with few malfunctions can be provided.

Further, germanium may be added to a silicon film used for an antifuse-type ROM. Since germanium has lower energy to react with other metal elements than silicon, the write voltage value of the antifuse-type ROM can be reduced. Further, a germanium film or a germanium film containing silicon may be used instead of the silicon film used for the antifuse-type ROM.

In addition, the antifuse-type ROM is significantly different from the antifuse-type ROM described in Patent Document 1 in the overall structure including the substrate. The antifuse-type ROM described in Patent Document 1 uses a silicon substrate that is a conductor that cuts off radio signals, and is not suitable for radio communication. Although there is no description regarding wireless communication in Patent Document 1, even if an antenna is formed in the antifuse-type ROM described in Patent Document 1, radio waves can be transmitted and received only from the surface side on which the antenna is formed. In addition, the induced current generated in the silicon substrate may increase noise and significantly reduce communication sensitivity. This antifuse-type ROM differs greatly from the antifuse-type ROM described in Patent Document 1 in that an insulating substrate is used, and an insulating substrate such as a glass substrate or a plastic substrate transmits a radio signal. Since the substrate is not cut off, radio waves from various directions other than the surface on which the antenna is formed can be transmitted and received. In addition, the antifuse-type ROM does not generate an induced current in the substrate, so that noise does not increase and good communication sensitivity can be realized.

In the technique described in Patent Document 1, as shown in FIG. 15, the tungsten film 54, the amorphous silicon film 53, and the tungsten film 54 'are continuously formed by the CVD method without being exposed to the atmosphere. Accordingly, since the antifuse-type ROM process is simply added to the conventional nMOS process, the total number of processes is large. In contrast to the semiconductor device described in Patent Document 1, in this semiconductor device, the gate electrode of the TFT of the drive circuit and one electrode of the antifuse-type ROM are formed in the same process, and the number of processes is reduced. Note that Patent Document 1 is characterized in that the tungsten film 54, the amorphous silicon film 53, and the tungsten film 54 'are continuously formed without being exposed to the atmosphere. Thus, it is not assumed that the gate electrode of the transistor and one electrode of the antifuse-type ROM are formed in the same process, and Patent Document 1 is greatly different from the manufacturing process of the present semiconductor device.

Alternatively, the antifuse-type ROM can be formed over an insulating substrate such as a glass substrate or a plastic substrate, peeled off from the insulating substrate, and transferred to a piece of paper or a film. The wireless chip using the paper piece thus formed as a base can have almost no protrusion on the surface as compared with a wireless chip using a silicon chip. Therefore, even when printing is further performed on a wireless chip having a paper piece as a base, high-definition printing is possible. In addition, in the conventional wireless chip, there is a possibility that the portion connecting the silicon chip and the antenna of the substrate is destroyed when the substrate is bent in accordance with the curved surface of the article. In addition, an antenna, an antifuse-type ROM, and a drive circuit are formed, so that a flexible wireless chip can be realized.

The driving circuit of the semiconductor device includes an antifuse-type ROM write circuit, an antifuse-type ROM read circuit, a voltage generation circuit such as a booster circuit, a clock generation circuit, a timing control circuit, a sense amplifier, An output circuit or a signal processing circuit such as a buffer is included. The driving circuit of the semiconductor device may include a circuit to which other elements such as a power supply voltage limiter circuit and cryptographic processing dedicated hardware are added.

In addition, the antifuse-type ROM mounted on the semiconductor device may be an active matrix storage device or a passive matrix storage device. In either case, at least one of the problems of the present invention can be solved by forming the drive circuit on the same substrate as the antifuse-type ROM. In the case of an active matrix memory device, a switching element is provided for one antifuse-type ROM and arranged in a matrix. In the case of a passive matrix (simple matrix) memory device, a plurality of bit lines arranged in stripes (bands) and a plurality of word lines arranged in stripes are provided so as to be orthogonal to each other. The material layer is sandwiched between the intersections. Accordingly, the memory element corresponding to the intersection of the selected bit line (to which a voltage is applied) and the selected word line is written or read.

A semiconductor device including a memory that can be driven within a range of a current value and a voltage value that can be generated from a radio signal can be realized, and the unit cost of the chip can be reduced. Further, by reducing the write voltage value, the voltage value formed by the booster circuit or the like from the signal obtained by the antenna can be lowered, and the planar area of the memory drive circuit can be reduced. Therefore, when the antifuse-type ROM is mounted on the chip, the area of the drive circuit occupying the chip can be reduced.

  Embodiments of the present invention will be described below. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.

A manufacturing process of the semiconductor device of the present invention will be described with reference to FIGS. A cross-sectional structure illustrated in FIG. 1A is a process diagram in the middle of manufacturing a semiconductor device.

First, the separation layer 102 and the insulating layer 103 are formed over the substrate 101 having an insulating surface. As the substrate 101 having an insulating surface, a quartz substrate, a glass substrate, or the like can be used. In particular, a glass substrate capable of increasing the area of one side exceeding 1 m is suitable for mass production. Further, a tungsten film with a thickness of 50 nm to 200 nm is used as the separation layer 102, and a silicon oxide film is used as the insulating layer 103. Note that the peeling layer 102 is not limited to a tungsten film, and a tungsten nitride film, a molybdenum film, an amorphous silicon film, or the like may be used. The insulating layer 103 is not limited to a silicon oxide film, and a silicon oxynitride film or a stacked film of a silicon oxide film and a silicon oxynitride film can be used.

Next, a plurality of semiconductor layers are formed over the insulating layer 103. The plurality of semiconductor layers may be formed by a known method. Here, after forming an amorphous silicon film by a known means (sputtering method, LPCVD method, plasma CVD method, etc.), a known crystallization process (laser crystallization method, thermal crystallization method, or catalyst such as nickel is used. A semiconductor film having a crystal structure crystallized by a thermal crystallization method or the like). The plurality of semiconductor layers become active layers of a thin film transistor to be formed later. In order to realize high-speed driving of the driver circuit, a semiconductor film having a crystal structure is preferably used for the active layer of the thin film transistor. By realizing high-speed driving of the driving circuit, high-speed reading of the memory can be realized.

Next, a gate insulating film 104 is formed to cover the plurality of semiconductor layers. As the gate insulating film 104, a single layer or a stacked structure of an insulating film containing silicon is used. As the gate insulating film 104, a plasma CVD method or a sputtering method is used, and the thickness is set to 1 to 200 nm. Alternatively, the gate insulating film 104 may be formed to have a thickness of 10 nm to 50 nm and a single layer or stacked structure of an insulating film containing silicon, and then surface nitridation treatment using plasma by microwaves.

Next, the first gate electrode 105 and the second gate electrode 106 which overlap with the semiconductor layer with the gate insulating film 104 interposed therebetween, and one electrode of the antifuse-type ROM, that is, the first electrode 107 are formed in the same process. To do. The first gate electrode 105, the second gate electrode 106, and the first electrode 107 are simple elements such as titanium, tungsten, nickel, chromium, molybdenum, tantalum, cobalt, zirconium, vanadium, palladium, hafnium, platinum, and iron. Alternatively, a conductive film of these alloys or compounds may be formed by a sputtering method and processed into a desired shape. A material having both characteristics suitable for the TFT gate electrode and characteristics suitable for one electrode of the antifuse-type ROM is selected. In this embodiment, a tungsten film is used. Since the tungsten film reacts with silicon to form silicide, it is suitable for one electrode of the antifuse-type ROM. Further, since the tungsten film is a material having a relatively large work function, the threshold voltage is low and almost symmetric with respect to both the p-channel transistor and the n-channel transistor. One.

Next, in order to add an impurity element imparting n-type conductivity to the semiconductor layer, a first resist mask that covers a region to be a p-channel TFT is formed, and doping is performed using the first resist mask and the first gate electrode 105 as a mask. Perform the process. An impurity element imparting n-type conductivity is added to the semiconductor layer, and an n-type impurity region is formed in a self-aligning manner. This n-type impurity region will later become the source region 108 or the drain region 109 of the n-channel TFT. A region of the semiconductor layer that overlaps with the first gate electrode 105 becomes a channel formation region 112. The doping process may be performed by ion doping or ion implantation. Typically, phosphorus (P) or arsenic (As) is used as the impurity element imparting n-type conductivity to the semiconductor layer.

Next, after removing the first resist mask, in order to add an impurity element imparting p-type conductivity to the semiconductor layer, a second resist mask that covers a region to be an n-channel TFT is formed, and the second resist mask and the second resist mask are formed. The doping process is performed using the gate electrode 106 as a mask. An impurity element imparting p-type conductivity (typically boron) is added to the semiconductor layer, so that a p-type impurity region is formed in a self-aligned manner. This p-type impurity region will later become the source region 111 or the drain region 110 of the p-channel TFT. In addition, a region of the semiconductor layer that overlaps with the second gate electrode 106 becomes a channel formation region 113.

  Thereafter, the second resist mask is removed. Through the above steps, impurity regions having n-type or p-type conductivity are formed in each semiconductor layer. Note that although an example in which the impurity element imparting n-type is added first is shown here, the order of doping is not particularly limited.

Further, before these doping steps, an insulator called a sidewall may be formed on the side wall of the gate electrode to form an LDD region adjacent to the channel formation region. Further, although the number of masks increases, the LDD region may be formed using a new resist mask. A region to which an impurity element is added at a low concentration is provided between a channel formation region and a source region or a drain region formed by adding an impurity element at a high concentration. This region is called an LDD region. . By providing the LDD region, the off-current value of the TFT can be reduced.

If necessary, a small amount of impurity element (boron or phosphorus) may be doped into the semiconductor layer in order to control the threshold value of the TFT.

Next, activation of the impurity element added to the semiconductor layer or hydrogenation of the semiconductor layer is performed using a known technique. Since the activation of the impurity element and the hydrogenation of the semiconductor layer are a high-temperature heat treatment in a furnace or a heat treatment using lamp light or laser light, the first element formed before the activation step or the hydrogenation step is used. The gate electrode 105, the second gate electrode 106, and the first electrode 107 are made of materials that can withstand these processing temperatures. Needless to say, the tungsten film used for the first gate electrode 105, the second gate electrode 106, and the first electrode 107 is a refractory metal and is sufficient for activating the impurity element and hydrogenating the semiconductor layer. It is a material that can withstand.

Next, an interlayer insulating film 114 that covers the first gate electrode 105, the second gate electrode 106, and the first electrode 107 is formed. As the interlayer insulating film 114, an inorganic insulating film is formed by a sputtering method, an LPCVD method, a plasma CVD method, or the like. As the inorganic insulating film, a single layer or a stacked layer of insulating films such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is used. The interlayer insulating film 114 also functions as a partition that insulates adjacent memory elements. Since a voltage is applied to the antifuse-type ROM to cause a silicide reaction, the periphery of the memory element instantaneously becomes a high temperature. Therefore, the interlayer insulating film 114 is preferably made of an inorganic insulating material that can withstand a temperature at which a silicide reaction occurs.

Further, as one layer of the inorganic insulating film, a siloxane resin having high heat resistance obtained by a coating method may be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

Next, a resist mask is formed using a photomask, and the interlayer insulating film 114 or the gate insulating film 104 is selectively etched to form openings. Etching may be wet etching or dry etching, or a combination thereof. Then, the resist mask is removed. There are three types of openings formed here: an opening reaching the semiconductor layer, an opening reaching the gate electrode of the TFT, and an opening reaching the first electrode 107. Further, two types of openings reaching the first electrode 107 are provided. A first opening in which a silicon film is formed later and a second opening in which a wiring electrically connected to the first electrode 107 is formed.

The size of the first opening reaching the first electrode 107 formed in this etching step is such that the diameter of the bottom surface of the opening is about 1 μm to about 6 μm. However, as shown in the graph of FIG. 2, the current consumption increases as the diameter of the first opening increases, so the first opening is preferably smaller. In addition, although the size of the opening is indicated by a diameter, the upper surface shape of the opening is not particularly limited to a circle, and may be an ellipse or a rectangle. In the graph of FIG. 2, the vertical axis indicates the current value immediately before the antifuse ROM is short-circuited, and the horizontal axis indicates the diameter of the first opening. The data in the graph of FIG. 2 is obtained from measurement using an amorphous silicon film having a thickness of 200 nm formed by sputtering as the silicon film of the antifuse ROM. In addition, regarding the amorphous silicon film formed by plasma CVD as the silicon film of the antifuse ROM, the relationship between the opening diameter and the current value immediately before the short circuit showed the same tendency as the amorphous silicon film formed by sputtering.

Further, in order to reduce the number of steps, the etching conditions are adjusted, the opening reaching the semiconductor layer by one etching, the opening reaching the gate electrode of the TFT, the first opening reaching the first electrode 107, and the first opening Two openings can be formed.

In the steps so far, a part of the antifuse-type ROM is formed in the same step as the TFT manufacturing step, so that the number of steps does not increase.

Next, a silicon film 115 is formed so as to cover the first opening reaching the first electrode 107. As the silicon film 115, an amorphous silicon film, a microcrystalline silicon film, or a polysilicon film can be used by a sputtering method, an LPCVD method, a plasma CVD method, or the like. Here, an amorphous silicon film obtained by a plasma CVD method is used.

The thickness of the silicon film 115 is 10 nm to 200 nm. The short voltage of the antifuse-type ROM is proportional to the thickness of the silicon film 115. The graph of FIG. 3 shows the relationship between the short voltage of the antifuse-type ROM in which the diameter of the first opening is 2 μm and the film thickness of the silicon film. Note that the silicon film of the antifuse-type ROM obtained from the graph of FIG. 3 is an amorphous silicon film using a sputtering method. From FIG. 3, it can be read that when the antifuse-type ROM with a low short-circuit voltage is formed, the silicon film 115 should be thin. The short voltage of the antifuse-type ROM can be freely designed by controlling the film thickness of the silicon film 115. In addition, regarding the amorphous silicon film formed by plasma CVD as the silicon film of the antifuse ROM, the relationship between the short voltage and the film thickness of the silicon film showed the same tendency as the amorphous silicon film formed by sputtering.

In addition, oxygen or nitrogen may be intentionally included in the silicon film used for the antifuse-type ROM. In addition, the above-described etching process and the silicon film formation process are not performed continuously without being exposed to the atmosphere, and nitrogen or oxygen is present at the interface between the silicon film 115 and the first electrode 107. More than the other regions of the silicon film 115 are included. In the antifuse-type ROM, at least the silicon film 115 and the first electrode 107 are not continuously stacked. By including oxygen or nitrogen in the silicon film 115, the difference in electrical resistance before and after writing to the antifuse ROM can be increased. Further, when exposed to the atmosphere after the opening is formed, a thin natural oxide film may be formed on the surface of the exposed tungsten film. In addition, even when a natural oxide film of a tungsten film is formed, the natural oxide film can function as a buffer layer, so that it can sufficiently function as an antifuse-type ROM.

One mask is required for patterning the silicon film 115, and the number of steps for film formation and patterning processes increases.

Note that if the silicon film 115 is selectively formed by using a droplet discharge method such as an inkjet method in which a liquid in which a higher order silane compound including hydrogen and silicon is dissolved in an organic solvent is used, the number of silicon films 115 increases. The number of processes that can be reduced can be reduced.

Next, an oxide film on the surface of the semiconductor layer is removed with an etchant containing hydrofluoric acid, and at the same time, the exposed surface of the semiconductor layer is washed. Note that care must be taken so that the silicon film 115 is not etched away in this cleaning step.

Next, after a metal film is stacked by a sputtering method, a mask made of a resist is formed using a photomask, the metal stacked film is selectively etched, and the TFT source electrodes 116, 118, and A drain electrode 117 is formed, an antifuse-type ROM second electrode 120 and a third electrode 119 are formed in the memory portion 130, and a connection electrode 121 is formed in the antenna portion 150. The connection electrode 121 is an electrode that electrically connects an antenna formed later and a power supply formation circuit.

The third electrode 119 is electrically connected to the first electrode 107 to reduce power consumption by routing wiring. In the case of an active matrix memory, the third electrode 119 electrically connects the switching element and the first electrode 107. In the case of a passive matrix memory, the first electrode 107 can be arranged in parallel in a stripe shape (band shape), and the second electrode 120 can be arranged in parallel in a stripe shape so as to be orthogonal to the first electrode 107. That's fine. In the case of a passive matrix memory, the third electrode 119 is provided at an end portion and serves as an extraction electrode.

Note that the metal laminated film here is a three-layer laminated structure of a titanium film with a thickness of 50 to 200 nm, a pure aluminum film with a thickness of 100 to 400 nm, and a titanium film with a thickness of 50 to 200 nm. For at least the layer in contact with the silicon film 115 of the metal laminated film, a material that forms silicide by reacting with silicon is used.

In addition, since this metal laminated film uses a titanium film, the contact resistance with other conductive materials is low, and since a pure aluminum film is used and the wiring resistance value is low, the wiring wiring of the drive circuit section, It is useful to use the lead-out wiring of the memory part and the connection part of the antenna part.

Thus, as shown in FIG. 1A, an antifuse-type ROM is provided in the memory portion 130 and an n-channel TFT is provided in the driver circuit portion 140 through the separation layer 102 and the insulating layer 103 over the substrate 101 having an insulating surface. And a CMOS circuit including a p-channel TFT. The second electrode 120 of the antifuse-type ROM is formed in the same process as the source electrodes 116 and 118 and the drain electrode 117 of the TFT, thereby reducing the number of processes. In addition, the connection electrode 121 of the antenna portion is also formed in the same process as the source electrodes 116 and 118 and the drain electrode 117, thereby reducing contact resistance and noise at the connection portion between the antenna and the power supply forming circuit. Can do.

Here, an electrical characteristic graph of the antifuse-type ROM is shown in FIG. In FIG. 4, the vertical axis represents current and the horizontal axis represents applied voltage. Further, an amorphous silicon film having a thickness of 50 nm formed by plasma CVD is used as the measured silicon film of the antifuse-type ROM. FIG. 4 shows the measurement results of the antifuse-type ROM having the first opening with a diameter of 2 μm. Measurement was performed with 25 elements, and the current value immediately before the short circuit was in the range of 1 μA to 10 μA. In addition, the short circuit of the antifuse ROM can be confirmed when the applied voltage is in the range of 4V to 6V. From the result of FIG. 4, it can be read that this antifuse-type ROM is a memory element which can be written with a low current value and a low voltage.

From the electrical characteristics of the antifuse-type ROM shown in FIG. 4, it can be said that a memory that can be driven within a range of current values and voltage values that can be generated from radio signals can be realized. That is, the antifuse-type ROM shown in FIG. 4 can reduce data writing power. Further, by reducing the write voltage value, the voltage value formed by the booster circuit or the like from the signal obtained by the antenna can be lowered, and the planar area of the memory drive circuit can be reduced. Therefore, when the antifuse-type ROM is mounted on the chip, the area of the drive circuit occupying the chip can be reduced. Further, the antifuse-type ROM shown in FIG. 4 can also reduce power for reading data, reduce power consumption of the memory, and achieve low power consumption of the entire wireless chip.

Further, FIG. 5 shows a cross-sectional photographic view after an antifuse-type ROM is formed on a glass substrate and a voltage is applied to bring it into a short state (conductive state between upper and lower electrodes). An amorphous silicon film having a thickness of 50 nm formed by plasma CVD is used as the silicon film of the antifuse-type ROM that was photographed. FIG. 5 shows a state in which the silicide reaction is performed over the entire region where the silicon film and the first electrode are in contact with each other. Note that the antifuse-type ROM is not particularly required to undergo a silicidation reaction over the entire region where the silicon film and the first electrode are in contact, and a part of the antifuse-type ROM may be brought into a conductive state by the silicidation reaction. The inventor has also confirmed several memory elements that are conductive in part of a region where the silicon film and the first electrode are in contact with each other.

Moreover, the enlarged view on the left side in the cross-sectional photograph of FIG. 5 is shown in FIG. A schematic diagram thereof is shown in FIG. Further, when the composition of each portion of the cross-sectional structure in FIG. 6B was examined by EDX measurement, tungsten was detected in the first electrode 207, silicon in the silicon film 215, and titanium in the second electrode 220. It was. In addition, the silicide reaction occurs from both the first electrode 207 and the second electrode 220. A titanium silicide layer 201 is formed over the entire surface of the silicon film in contact with the second electrode 220. The region 202 in contact with the first electrode 207 is a region where titanium silicide and tungsten silicide are mixed. Titanium silicide and tungsten silicide contained in the region 202 are partially electrically connected to the titanium silicide layer 201 and are in a short state (conductive state).

Then, an insulating film 122 that covers the source electrodes 116 and 118, the drain electrode 117, the second electrode 120, the third electrode 119, and the connection electrode 121 is formed. This insulating film 122 may be an inorganic insulating film, or may be a laminate of an inorganic insulating film and an organic insulating film.

Next, a resist mask is formed, and the insulating film 122 is selectively etched to form an opening reaching the third electrode 119 and an opening reaching the connection electrode 121. Note that the opening reaching the connection electrode 121 has a relatively large size or a plurality of openings in order to ensure electrical connection with an antenna formed later.

Then, the resist mask is removed, and a metal layer 124 and a fourth electrode 123 for improving the adhesion of the antenna are formed. The metal layer 124 and the fourth electrode 123 are formed in the same process, and a titanium film, a copper film, an aluminum film, or the like is used. The metal layer 124 and the fourth electrode 123 are formed by a sputtering method or an inkjet method. In the case of using a sputtering method, after a metal layer is formed, a resist mask is formed, selective etching is performed, and the resist mask is removed.

Next, the antenna 125 is formed by sputtering or printing. When the antenna 125 is formed by a screen printing method or an ink jet method, after selectively printing a conductive paste in which conductive particles having a particle size of several nanometers to several tens of micrometers are dissolved or dispersed in an organic resin, Firing is performed to reduce the electrical resistance value.

Conductor particles include silver (Ag), gold (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo) and titanium (Ti). Any one or more metal particles, silver halide fine particles, or dispersible nanoparticles can be used. In addition, as the organic resin contained in the conductive paste, one or more selected from organic resins functioning as a binder of metal particles, a solvent, a dispersant, and a coating material can be used. Typically, an organic resin such as an epoxy resin or a silicone resin can be given. In forming the conductive film, it is preferable to fire after extruding the conductive paste. For example, when fine particles containing silver as a main component (for example, a particle size of 1 nm or more and 100 nm or less) are used as a material for the conductive paste, the conductive paste can be cured by baking in a temperature range of 150 to 300 ° C. to obtain a conductive film. it can. Further, fine particles mainly composed of solder or lead-free solder may be used. In this case, it is preferable to use fine particles having a particle diameter of 20 μm or less. Solder and lead-free solder have the advantage of low cost.

In the case where the antenna 125 is formed by a screen printing method, it is effective to provide the metal layer 124 as a base film when the adhesion with the insulating film 122 is low. The mounting process can be eliminated by forming the antifuse-type ROM, the drive circuit, and the antenna on the same substrate. “Mounting” here refers to an operation of electrically connecting a base provided with an antenna and a drive circuit by soldering, thermocompression bonding, wire bonding connection, bump connection or the like. For example, mounting is performed when a silicon chip is attached to an antenna provided on a base.

The shape of the antenna 125 is not particularly limited. As a signal transmission method applied to the antenna, an electromagnetic coupling method, an electromagnetic induction method, a microwave method, or the like can be used. The transmission method may be selected by the practitioner in consideration of the intended use, and an antenna having an optimal length and shape may be provided in accordance with the transmission method.

For example, when an electromagnetic coupling method or an electromagnetic induction method (for example, 13.56 MHz band) is applied as a transmission method, a conductive film functioning as an antenna is formed in a ring shape (for example, an electromagnetic induction due to a change in electric field density). , Loop antenna) or spiral (eg, spiral antenna).

In addition, when a microwave method (for example, UHF band (860 to 960 MHz band), 2.45 GHz band, or the like) is applied as a transmission method, a conductive function that functions as an antenna in consideration of the wavelength of a radio wave used for signal transmission. The length and shape of the film may be set as appropriate, and the conductive film functioning as an antenna can be formed, for example, in a linear shape (for example, a dipole antenna) or a flat shape (for example, a patch antenna). Further, the shape of the conductive film functioning as an antenna is not limited to a linear shape, and may be provided in a curved shape, a meandering shape, or a combination thereof in consideration of the wavelength of electromagnetic waves.

An example of the shape of the antenna is shown in FIG. For example, as shown in FIG. 7A, a structure in which one antenna 303A is arranged around the memory portion and the driver circuit 302A may be employed. Further, as shown in FIG. 7B, a structure in which a thin antenna 303B is arranged around the memory portion and the driving circuit 302B around the memory portion and the driving circuit 302B may be employed. Alternatively, as shown in FIG. 7C, the memory portion and the driver circuit 302C may have a shape like an antenna 303C for receiving high-frequency electromagnetic waves. Further, as shown in FIG. 7D, a shape like an antenna 303D that is 180 degrees omnidirectional (receivable from any direction) with respect to the memory portion and the driver circuit 302D may be employed. Further, as shown in FIG. 7E, the memory portion and the driver circuit 302E may be shaped like an antenna 303E that is elongated in a rod shape. The antenna 125 can be a combination of these antennas.

The length required for the antenna varies depending on the frequency used for reception. For example, when the frequency is 2.45 GHz, it may be about 60 mm (1/2 wavelength) if a half-wave dipole antenna is provided, and about 30 mm (1/4 wavelength) if a monopole antenna is provided.

Next, peeling is performed at the interface or the layer of the peeling layer 102, and sealing is performed with the first sheet 100a and the second sheet 100b. The peeling method is not particularly limited, and a known peeling method, for example, a peeling method using a surface oxide film of a tungsten film of a peeling layer (a technique described in JP-A-2004-214281), a peeling method for etching a peeling layer, A peeling method using laser ablation may be used. The sealing may be performed using an adhesive layer such as an epoxy resin. Further, the order of the peeling step and the antenna forming step may be changed, and after peeling, the antenna may be formed using a screen printing method.

The first sheet 100a and the second sheet 100b are made of plastic film or paper. Further, the first sheet 100a and the second sheet 100b may be made of thin ceramics in order to improve pressure resistance, or a sheet in which a resin is impregnated with a carbon fiber or glass fiber woven fabric, a so-called prepreg. It may be used. When a flexible material is used as the material of the first sheet 100a and the second sheet 100b, a wireless chip suitable for being attached to a curved surface of an article can be provided.

Through the above steps, an antifuse-type ROM and a drive circuit are formed on the same substrate. Further, an antifuse-type ROM, a drive circuit, and an antenna can be formed on the same substrate with a small number of steps.

  The present invention having the above-described configuration will be described in more detail with the following examples.

In this embodiment, a method for manufacturing a wireless chip having an active matrix anti-fuse ROM will be described below with reference to FIGS. 8A to 8D and FIGS. 9A to 9C. Explained.

First, a metal layer 502 to be a peeling layer is formed over the substrate 501. A glass substrate is used as the substrate 501. As the metal layer 502, a 30 nm to 200 nm tungsten film, a tungsten nitride film, or a molybdenum film obtained by a sputtering method is used.

Next, the surface of the metal layer 502 is oxidized to form a metal oxide layer (not shown). The method for forming the metal oxide layer may be formed by oxidizing the surface using pure water or ozone water, or by oxidizing with oxygen plasma. Alternatively, the metal oxide layer may be formed by heating in an atmosphere containing oxygen. Further, it may be formed in a later step of forming the insulating film. In this case, when a silicon oxide film or a silicon oxynitride film is formed as the insulating film by a plasma CVD method, the surface of the metal layer 502 is oxidized to form a metal oxide layer.

Next, a first insulating film 503 is formed over the metal oxide layer. As the first insulating film 503, an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO _x N _y ) is used. As a typical example, the first insulating film 503 has a two-layer structure, and a silicon nitride oxide film formed using SiH ₄ , NH ₃ , and N ₂ O as a reactive gas by a PCVD method has a thickness of 50 to 100 nm, SiH ₄ , In addition, a structure in which a silicon oxynitride film formed using N ₂ O as a reactive gas is formed to a thickness of 100 to 150 nm is employed. In addition, a silicon nitride film (SiN film) or a silicon oxynitride film (SiN _x O _y film (X> Y)) having a thickness of 10 nm or less is preferably used as one layer of the first insulating film 503. Alternatively, a three-layer structure in which a silicon nitride oxide film, a silicon oxynitride film, and a silicon nitride film are sequentially stacked may be used. Although an example in which the first insulating film 503 is formed as the base insulating film is shown here, it is not necessary to provide it unless particularly necessary.

Next, a semiconductor layer is formed over the first insulating film 503. After a semiconductor film having an amorphous structure is formed by a known means (sputtering method, LPCVD method, plasma CVD method, etc.), a known crystallization treatment (laser crystallization method, thermal crystallization method, nickel, etc.) A crystalline semiconductor film obtained by performing a thermal crystallization method using a catalyst of (1) is formed with a resist mask using a first photomask, and then patterned into a desired shape to form an island-shaped semiconductor layer A plurality of are formed. Note that when the plasma CVD method is used, the first insulating film and the semiconductor film having an amorphous structure can be continuously stacked without being exposed to the air. The semiconductor film is formed with a thickness of 25 to 80 nm (preferably 30 to 70 nm). There is no limitation on the material of the crystalline semiconductor film, but the crystalline semiconductor film is preferably formed of silicon or a silicon germanium (SiGe) alloy.

In addition, a continuous wave laser may be used as a crystallization process for a semiconductor film having an amorphous structure. In order to obtain a crystal with a large grain size when crystallizing an amorphous semiconductor film, continuous oscillation is possible. It is preferable to use a solid-state laser and apply the second to fourth harmonics of the fundamental wave. Typically, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) may be applied. In the case of using a continuous wave laser, laser light emitted from a continuous wave YVO ₄ laser having an output of 10 W is converted into a harmonic by a non-linear optical element. There is also a method of emitting harmonics by putting a YVO ₄ crystal and a nonlinear optical element in a resonator. Then, it is preferably formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and irradiated to the object to be processed. At this time, the energy density of approximately 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation may be performed by moving the semiconductor film relative to the laser light at a speed of about 10 to 2000 cm / s.

Next, the resist mask is removed. Next, if necessary, a small amount of impurity element (boron or phosphorus) is doped into the semiconductor layer in order to control the threshold value of the TFT. Here, an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation is used.

  Next, the oxide film on the surface of the semiconductor layer is removed with an etchant containing hydrofluoric acid, and at the same time, the surface of the semiconductor layer is washed.

Then, a second insulating film that covers the semiconductor layer is formed. The second insulating film is formed by plasma CVD or sputtering and has a thickness of 1 to 200 nm. It is preferably formed as a single layer or a laminated structure of an insulating film containing silicon by thinning to 10 nm to 50 nm, and then surface nitriding treatment using plasma by microwave is performed. The second insulating film functions as a gate insulator of a TFT formed later.

Next, gate electrodes 504 to 508 and a first electrode 509 to be a lower electrode of the antifuse-type ROM are formed over the second insulating film. A resist mask is formed using a second photomask on a conductive film with a thickness of 100 nm to 500 nm obtained by a sputtering method, and then patterned into a desired shape, whereby the gate electrodes 504 to 508 and the first electrode are patterned. An electrode 509 is formed.

The material of the gate electrodes 504 to 508 and the first electrode 509 may be any material that forms silicide by reacting with silicon. Titanium, tungsten, nickel, chromium, molybdenum, tantalum, cobalt, zirconium, vanadium, palladium Or an element selected from hafnium, platinum, and iron, or a single layer of an alloy material or a compound material containing the element as a main component, or a stacked layer thereof. However, a refractory metal is preferable as the gate electrode of the TFT, and tungsten or molybdenum is used. When the gate electrodes 504 to 508 and the first electrode 509 are stacked, if the upper material layer is the above-described material, the lower material layer is polycrystalline doped with an impurity element such as phosphorus. It may be a silicon layer.

Next, a resist mask is formed using a third photomask so as to cover the semiconductor layer in the region to be the p-channel TFT, and the gate electrode 505 and 507 are used as impurities in the semiconductor layer in the region to be the n-channel TFT. By introducing the element, a low concentration impurity region is formed. As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity can be used. As the n-type impurity element, phosphorus, arsenic, or the like can be used. Here, an n-type impurity region is formed by introducing phosphorus into a semiconductor layer in a region to be an n-channel TFT so as to be contained at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁹ / cm ³ .

Next, the resist mask is removed, a resist mask is formed using a fourth photomask so as to cover the semiconductor layer in the region to be the n-channel TFT, and the gate electrode is formed on the semiconductor layer in the region to be the p-channel TFT. By introducing an impurity element using 504, 506, and 508 as a mask, an impurity region showing p-type is formed. As the p-type impurity element, boron, aluminum, gallium, or the like can be used. Here, an impurity region exhibiting p-type is formed by introducing boron into the semiconductor layer in a region to be a p-channel TFT so as to be contained at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ^3. Can do. As a result, source or drain regions 514 and 515 and a channel formation region 516 are formed in a semiconductor layer in a region to be a p-channel TFT.

Next, sidewalls 510 and 511 are formed on both side surfaces of the gate electrodes 504 to 508 and the first electrode 509. As a method for manufacturing the sidewall 510, first, silicon, a silicon oxide, or silicon is formed by a plasma CVD method, a sputtering method, or the like so as to cover the second insulating film, the gate electrodes 504 to 508, and the first electrode 509. A third insulating film is formed by single-layering or stacking a film containing an inorganic material of nitride or a film containing an organic material such as an organic resin. Next, the third insulating film is selectively etched by anisotropic etching mainly in the vertical direction, so that the insulating films (sidewall 510) that are in contact with the side surfaces of the gate electrodes 504 to 508 and the first electrode 509 are etched. ). Note that a part of the second insulating film is removed by etching simultaneously with the formation of the sidewalls 510. By removing a part of the second insulating film, the remaining gate insulating layer 512 is formed below the gate electrodes 504 to 508 and the sidewalls 510. Further, by removing a part of the second insulating film, the remaining insulating layer 513 is formed below the first electrode 509 and below the sidewalls 511.

Next, a resist mask is formed using a fifth photomask so as to cover the semiconductor layer in the region to be the p-channel TFT, and the gate electrodes 505 and 507 and the sidewalls 510 are formed on the semiconductor layer in the region to be the n-channel TFT. As a mask, an impurity element is introduced to form a high concentration impurity region. The resist mask is removed after the introduction of the impurity element. Here, phosphorus (P) is introduced into a semiconductor layer in a region to be an n-channel TFT so as to be contained at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ³ , thereby providing a high-concentration impurity exhibiting n-type. Regions can be formed. As a result, source or drain regions 517 and 518, LDD regions 519 and 520, and a channel formation region 521 are formed in a semiconductor layer in a region to be an n-channel TFT. LDD regions 519 and 520 are formed below the side wall 510.

Although a structure in which an LDD region is formed in a semiconductor layer included in an n-channel TFT and an LDD region is not provided in a semiconductor layer included in a p-channel TFT is shown, of course, the present invention is not limited to this. LDD regions may be formed in both semiconductor layers of the type TFT.

Next, after the fourth insulating film 522 containing hydrogen is formed by a sputtering method, an LPCVD method, a plasma CVD method, or the like, activation treatment and hydrogenation treatment of the impurity element added to the semiconductor layer are performed. For the activation treatment and hydrogenation treatment of the impurity element, heat treatment in a furnace (heat treatment at 300 to 550 ° C. for 1 to 12 hours) or rapid thermal annealing method (RTA method) using a lamp light source is used. As the fourth insulating film 522 containing hydrogen, a silicon nitride oxide film (SiNO film) obtained by a PCVD method is used. Here, the thickness of the fourth insulating film 522 containing hydrogen is 50 nm to 200 nm. In addition, when the semiconductor film is crystallized using a metal element that promotes crystallization, typically nickel, gettering that reduces nickel in the channel formation region at the same time as activation can be performed. . Note that the fourth insulating film 522 containing hydrogen is a first layer of an interlayer insulating film.

Next, a fifth insulating film 523 which is a second layer of the interlayer insulating film is formed by a sputtering method, an LPCVD method, a plasma CVD method, or the like. As the fifth insulating film 523, a single layer or a stacked layer of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is used. Here, the thickness of the fifth insulating film 523 is set to be 300 nm to 800 nm.

Next, a resist mask is formed over the fifth insulating film 523 using a sixth photomask, and the fourth insulating film 522 and the fifth insulating film 523 are selectively etched to reach the first electrode 509. Forming an opening. Then, the resist mask is removed after the etching. The diameter of the first opening may be about 1 μm to about 6 μm, and in this embodiment, the diameter of the first opening is 2 μm.

A cross-sectional view of the semiconductor device manufactured through the preceding steps corresponds to FIG.

Next, a silicon film is formed by sputtering, LPCVD, plasma CVD, or the like. As the silicon film, any one of an amorphous silicon film, a microcrystalline silicon film, and a polysilicon film is used, and has a thickness of 10 nm to 200 nm. In this embodiment, an amorphous silicon film having a thickness of 100 nm is formed by plasma CVD. Next, a resist mask is formed over the amorphous silicon film using a seventh photomask, and the amorphous silicon film is selectively etched to form a silicon layer 524 that overlaps with the first opening. Then, the resist mask is removed after the etching.

A cross-sectional view of the semiconductor device manufactured through the preceding steps corresponds to FIG.

Next, a resist mask is formed using an eighth photomask, and the fourth insulating film 522 and the fifth insulating film 523 are selectively etched, so that an opening reaching the semiconductor layer, an opening reaching the gate electrode, A second opening reaching the electrode 509 is formed. Then, the resist mask is removed after the etching.

A cross-sectional view of the semiconductor device through the steps up to here corresponds to FIG.

Next, the surface of the exposed semiconductor layer and the exposed first electrode surface are removed simultaneously with the removal of the oxide film on the exposed semiconductor layer surface and the exposed first electrode surface with an etchant containing hydrofluoric acid. Wash.

Next, a conductive film is formed by a sputtering method. This conductive film is made of an element selected from titanium, tungsten, nickel, chromium, molybdenum, tantalum, cobalt, zirconium, vanadium, palladium, hafnium, platinum, iron, aluminum, copper, or an alloy material containing the element as a main component. Alternatively, a single layer of a compound material or a stack of these layers is formed. However, in the case of stacking a conductive film, at least one layer in contact with the silicon layer 524 is formed using a material that forms silicide by reacting with silicon and the material used for the first electrode 509 that serves as a lower electrode of the memory element (this book In the embodiment, a material different from tungsten is used. For example, a three-layer structure of a titanium film, an aluminum film containing a small amount of silicon, and a titanium film, or a three-layer structure of a titanium film, an aluminum alloy film containing nickel and carbon, and a titanium film is used. In this embodiment, a three-layer stack of a titanium film with a thickness of 100 nm, a pure aluminum film with a thickness of 350 nm, and a titanium film with a thickness of 100 nm is used.

Next, a resist mask is formed using a ninth photomask, the conductive film is selectively etched, and source or drain electrodes 525 to 534, gate lead-out wirings 535 to 539, and second antifuse-type ROM The electrode 540, the third electrode 541, and the fourth electrode 542 of the antenna portion are formed. The second electrode 540 overlaps with the first opening and serves as an upper electrode of the memory element. The third electrode 541 overlaps with the second opening and is electrically connected to the first electrode 509. Although not shown here, the fourth electrode 542 is electrically connected to the TFT of the antenna portion and the power supply portion. Then, the resist mask is removed after the etching.

A cross-sectional view of the semiconductor device manufactured through the preceding steps corresponds to FIG. In this embodiment, nine photomasks are used to form the TFT of the logic circuit portion 601, the TFT of the memory portion 602 and the antifuse ROM 600, and the TFT of the antenna portion and the power source portion 603 on the same substrate. Can do.

Next, a sixth insulating film 543 is formed to cover the TFT of the logic circuit portion 601, the TFT of the memory portion 602 and the antifuse-type ROM 600, and the TFT of the antenna portion and the power source portion 603. As the sixth insulating film 543, an insulating film containing silicon oxide or an organic resin film is used. In order to improve the reliability of the wireless chip, it is preferable to use an insulating film containing silicon oxide. In addition, when an antenna to be formed later is formed by a screen printing method, it is desirable to have a flat surface, and thus an organic resin film using a coating method is preferably used. The practitioner may select the sixth insulating film 543 as appropriate. Further, in this embodiment, an example in which an antenna to be formed later overlaps with a driver circuit of the power supply portion 603 is shown, so that the sixth insulating film 543 functions as an interlayer insulating film for insulation from the antenna. In the case of a ring-shaped (for example, loop antenna) or spiral antenna, it is preferable to provide a sixth insulating film 543 in order to draw one of both ends of the antenna with a lower layer wiring. However, when a microwave method is applied to form a linear antenna (for example, a dipole antenna) or a flat antenna (for example, a patch antenna), the antenna to be formed later does not overlap the driver circuit and the memory unit. The sixth insulating film 543 is not necessarily provided.

Next, a resist mask is formed using a tenth photomask, and the sixth insulating film 543 is selectively etched to form a third opening reaching the third electrode 541 and a fourth electrode reaching the fourth electrode 542. 4 openings are formed. Then, the resist mask is removed after the etching.

A cross-sectional view of the semiconductor device manufactured through the preceding steps corresponds to FIG.

Next, a metal film is formed over the sixth insulating film 543. As the metal film, a single layer selected from titanium, nickel, and gold or a laminate thereof is used. Next, a resist mask is formed using an eleventh photomask, and the metal film is selectively etched to form a lead wiring 544 and an antenna base film 545 in the lead wiring portion 604 of the first electrode 509. . Note that the lead-out wiring 544 and the base film 545 here can be selectively formed by a sputtering method using a metal mask without using a resist mask. By providing the antenna base film 545, a wide contact area with the antenna can be secured. In addition, by providing the base film 545 of the antenna, adhesion with the sixth insulating film 543 can be improved. Needless to say, since the base film 545 of the antenna is formed of a conductive material, it functions as a part of the antenna. Further, depending on the layout of the circuit design, the lead wiring 544 may not be particularly formed.

A cross-sectional view of the semiconductor device manufactured through the preceding steps corresponds to FIG.

Next, an antenna 546 is formed over the base film 545 of the antenna. The antenna 546 can be formed by forming a metal film such as aluminum or silver using a sputtering method and then patterning using a photomask, or a screen printing method. If priority is given to reducing the number of photomasks, the antenna 546 may be formed by a screen printing method. The screen printing method is an ink or paste placed on a screen plate in which a predetermined pattern is formed of a photosensitive resin on a base made of metal or a polymer compound fiber mesh. This is a method of transferring to a workpiece placed on the opposite side of the screen plate using a blade. The screen printing method has an advantage that pattern formation in a relatively large area can be realized at low cost.

A cross-sectional view of the semiconductor device manufactured through the preceding steps corresponds to FIG. In this embodiment, eleven photomasks are used, and the TFT of the logic circuit portion 601, the TFT of the memory portion 602 and the anti-fuse ROM 600, the TFT of the antenna portion and the power source portion 603, and the antenna are formed on the same substrate. Can be formed.

In the case where the lead wiring 544 and the base film 545 of the antenna are selectively formed by a sputtering method using a metal mask, the wireless chip in FIG. 9C can be formed using ten photomasks. it can. In addition, in the case where a microwave method is applied to form an antenna having a linear shape or a flat shape, the formation of the sixth insulating film 543 and the base film 545 of the antenna can be omitted; therefore, nine photomasks are used. A wireless chip can be formed. Furthermore, in order to reduce the number of photomasks, if the driver circuit is designed and manufactured using only p-channel TFTs, the number of two photomasks can be eliminated, and a wireless chip is formed with a total of seven masks. can do.

In this embodiment, a resist mask is formed using a photomask. However, the patterning technique is not particularly limited, and a resist material is selectively formed by a droplet discharge method without using a photomask. A resist mask may be formed.

Next, peeling is performed to remove the metal layer 502 and the substrate 501. Separation occurs in the metal oxide film, the interface between the first insulating film 503 and the metal oxide film, or the interface between the metal oxide film and the metal layer 502, and the wireless chip can be peeled off from the substrate 501 with a relatively small force. When removing the metal layer 502 and the substrate 501, a fixed substrate that is bonded to the side where the antenna is provided may be used.

Next, one sheet on which an infinite number of wireless chips are formed is divided by a cutter, dicing, or the like, and cut into individual wireless chips. Further, if a method of picking up and peeling wireless chips one by one is used at the time of peeling, this dividing step is not particularly necessary.

Next, the wireless chip is fixed to the sheet-like substrate. As the sheet-like substrate, plastic, paper, prepreg, ceramic sheet or the like can be used. The wireless chip may be fixed between two sheet-like bases, or may be fixed to one sheet-like base with an adhesive layer. As the adhesive layer, various curable adhesives such as a reactive curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive can be used. In addition, a wireless chip can be arranged in the middle of paper formation, and the wireless chip can be provided inside one sheet of paper.

The wireless chip that has undergone the above steps can realize a write-once memory that can be written at any time after manufacturing the wireless chip. For example, after a wireless chip fixed to a flexible sheet-like substrate is attached to an article having a curved surface, data can be written to an antifuse-type ROM included in the wireless chip.

This embodiment can be freely combined with the embodiment mode.

In this embodiment, an example in which the process is partially different from that in Embodiment 1 is shown in FIGS. 10 (A) to 10 (D) and FIGS. 11 (A) to 11 (C). In addition, the same code | symbol is used for the part which is common in Example 1, and the same description is abbreviate | omitted here for simplification.

First, according to Example 1, the same cross-sectional structure as that in FIG. Note that FIG. 10A is the same as FIG.

Next, a silicon film is formed by sputtering, LPCVD, plasma CVD, or the like, and a metal film is stacked thereon by sputtering or plasma CVD. As the silicon film, any one of an amorphous silicon film, a microcrystalline silicon film, and a polysilicon film is used, and has a thickness of 10 nm to 200 nm. The metal film is made of titanium, W, Ni, Cr, Mo, Ta, Co, Zr, V, Pd, Hf, Pt, Fe or the like, or an alloy or compound thereof, and has a thickness of 10 nm to 100 nm. To do. Note that the metal film is formed using a material different from that used for the first electrode 509 serving as the lower electrode of the memory element. In this embodiment, an amorphous silicon film having a thickness of 50 nm and a titanium nitride film having a thickness of 100 nm are continuously stacked using a sputtering method without being exposed to the atmosphere. That is, in this embodiment, in the memory portion, the silicon layer and the first electrode are not continuously stacked, but the silicon layer and the second electrode are continuously stacked. The formation of the interface between the silicon layer 524 and the second electrode without being exposed to the air in this manner is important for performing silicide writing by writing as a memory. Further, the metal film may be a laminate, for example, a laminate of a titanium film and a titanium nitride film. In the first embodiment, the process of exposing the silicon layer 524 is shown, but in this embodiment, the silicon layer 524 is protected by continuously forming a metal film. In particular, in the case where the silicon layer 524 is 50 nm or less, it is possible to prevent the silicon layer from being thinned by cleaning with hydrofluoric acid or the like performed later.

Next, a resist mask is formed over the metal film using a seventh photomask, and the metal film and the amorphous silicon film are selectively etched, so that the silicon layer 524 and the second electrode 701 which overlap with the first opening are formed. Form. Then, the resist mask is removed after the etching. Note that in the case where the second electrode 701 is formed by selectively removing the metal film by dry etching, the titanium nitride film which is the upper layer of the second electrode 701 is transferred to the silicon layer 524 by plasma when dry etching is performed. Can prevent damage.

A cross-sectional view of the semiconductor device manufactured through the preceding steps corresponds to FIG.

Next, a resist mask is formed using an eighth photomask, and the fourth insulating film 522 and the fifth insulating film 523 are selectively etched, so that an opening reaching the semiconductor layer, an opening reaching the gate electrode, A second opening reaching the electrode 509 is formed. Then, the resist mask is removed after the etching.

A cross-sectional view of the semiconductor device manufactured through the preceding steps corresponds to FIG.

Next, the surface of the exposed semiconductor layer and the exposed first electrode surface are removed simultaneously with the removal of the oxide film on the exposed semiconductor layer surface and the exposed first electrode surface with an etchant containing hydrofluoric acid. Wash. Note that the upper surface of the silicon layer 524 is covered with a second electrode 701. In this embodiment, the second electrode 701 is a stacked layer of a titanium film and a titanium nitride film. A titanium film reacts with silicon more easily than a titanium nitride film to form a silicide. Further, the titanium nitride film can prevent the titanium film from being etched by an etchant containing hydrofluoric acid when cleaning the exposed surface of the semiconductor layer and the exposed first electrode surface.

Next, a conductive film is formed by a sputtering method. The conductive film is formed using an element selected from titanium, tungsten, molybdenum, aluminum, and copper, or a single layer of an alloy material or a compound material containing the element as a main component, or a stacked layer thereof. In this embodiment, a three-layer stack of a titanium film with a thickness of 100 nm, an aluminum film containing a trace amount of silicon with a thickness of 350 nm, and a titanium film with a thickness of 100 nm is used.

Next, a resist mask is formed using a ninth photomask, and the conductive film is selectively etched, so that source or drain electrodes 525 to 534, gate lead-out wirings 535 to 539, and antifuse-type ROM third The first electrode 541 and the fifth electrode 702, and the fourth electrode 542 of the antenna portion are formed. The fifth electrode 702 overlaps with the second electrode 701 and reduces the electrical resistance of the wiring. The third electrode 541 overlaps with the second opening and is electrically connected to the first electrode 509. Although not shown here, the fourth electrode 542 is electrically connected to the TFT of the antenna portion and the power supply portion. Then, the resist mask is removed after the etching.

A cross-sectional view of the semiconductor device through the steps up to here corresponds to FIG. Also in this embodiment, nine photomasks are used to form the TFT of the logic circuit portion 601, the TFT of the memory portion 602, the anti-fuse ROM 600, and the TFT of the antenna portion and the power source portion 603 on the same substrate. Can do.

Next, a sixth insulating film 543 is formed to cover the TFT of the logic circuit portion 601, the TFT of the memory portion 602 and the antifuse-type ROM 600, and the TFT of the antenna portion and the power source portion 603. As the sixth insulating film 543, an insulating film containing silicon oxide or an organic resin film is used. In order to improve the reliability of the wireless chip, it is preferable to use an insulating film containing silicon oxide. In addition, when an antenna to be formed later is formed by a screen printing method, it is desirable to have a flat surface, and thus an organic resin film using a coating method is preferably used. The practitioner may select the sixth insulating film 543 as appropriate.

Next, a resist mask is formed using a tenth photomask, and the sixth insulating film 543 is selectively etched, so that a fourth opening reaching the fourth electrode 542 is formed. Then, the resist mask is removed after the etching.

A cross-sectional view of the semiconductor device through the steps up to here corresponds to FIG.

Next, an antenna base film 545 is formed over the sixth insulating film 543 by a sputtering method using a metal mask or a droplet discharge method. As the base film 545 for the antenna, a single layer selected from titanium, nickel, and gold or a stacked layer thereof is used. Note that the base film 545 here may be formed by forming a resist mask using a photomask and selectively etching a metal film.

A cross-sectional view of the semiconductor device through the steps up to here corresponds to FIG.

Next, an antenna 546 is formed over the base film 545. For the antenna 546, a metal film is formed by a sputtering method, and then a patterning method using a photomask or a screen printing method can be used. If priority is given to reducing the number of photomasks, an antenna may be formed by a screen printing method.

A cross-sectional view of the semiconductor device through the steps up to here corresponds to FIG. In this embodiment, using ten photomasks, the TFT of the logic circuit portion 601, the TFT of the memory portion 602 and the antifuse ROM 600, the TFT of the antenna portion and the power supply portion 603, and the antenna are formed on the same substrate. Can be formed.

In addition, in order to reduce the number of photomasks, if the driver circuit is designed and manufactured using only p-channel TFTs, the number of two photomasks can be eliminated, and a wireless chip is formed with a total of eight masks. can do.

In the subsequent steps, the wireless chip may be completed according to the first embodiment.

In this embodiment, a resist mask is formed using a photomask. However, the patterning technique is not particularly limited, and a resist material is selectively formed by a droplet discharge method without using a photomask. A resist mask may be formed.

In addition, this embodiment can be freely combined with the embodiment mode or Embodiment 1.

The configuration of the semiconductor device of this example will be described with reference to FIG. As shown in FIG. 12, the semiconductor device 1520 of the present invention has a function of communicating data without contact, and controls to control a power supply circuit 1511, a clock generation circuit 1512, a data demodulation / modulation circuit 1513, and other circuits. The circuit 1514 includes an interface circuit 1515, a memory circuit 1516, a data bus 1517, an antenna 1518, a sensor 1523a, and a sensor circuit 1523b. In FIG. 12, a drive circuit indicates a power supply circuit 1511, a clock generation circuit 1512, a data demodulation / modulation circuit 1513, a control circuit 1514 for controlling other circuits, and an interface circuit 1515.

The power supply circuit 1511 is a circuit that generates various power supplies to be supplied to each circuit inside the semiconductor device 1520 based on the AC signal input from the antenna 1518. The clock generation circuit 1512 is a circuit that generates various clock signals to be supplied to each circuit inside the semiconductor device 1520 based on the AC signal input from the antenna 1518. The data demodulation / modulation circuit 1513 has a function of demodulating / modulating data communicated with the reader / writer 1519. The control circuit 1514 has a function of controlling the memory circuit 1516. The antenna 1518 has a function of transmitting and receiving radio waves. The reader / writer 1519 controls communication with the semiconductor device, control, and processing related to the data. The semiconductor device is not limited to the above-described configuration, and may be a configuration in which other elements such as a power supply voltage limiter circuit and hardware dedicated to cryptographic processing are added.

The memory circuit 1516 includes a memory portion as shown in Embodiment Mode 1, that is, a plurality of memory elements in which a silicon film that undergoes a silicidation reaction by an external electric action is sandwiched between a pair of conductive layers. Note that the memory circuit 1516 may include only a memory element in which a silicon film is sandwiched between a pair of conductive layers, or may include a memory circuit having another structure. The memory circuit having another configuration corresponds to, for example, one or more selected from DRAM, SRAM, FeRAM, mask ROM, PROM, EPROM, EEPROM, and flash memory.

The sensor 1523a is formed of a semiconductor element such as a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, or a diode. The sensor circuit 1523b detects a change in impedance, reactance, inductance, voltage, or current, performs analog / digital conversion (A / D conversion), and outputs a signal to the control circuit 1514.

In addition, this embodiment can be freely combined with the embodiment mode, embodiment 1, or embodiment 2.

According to the present invention, a semiconductor device functioning as a wireless chip can be formed. Applications of wireless chips are wide-ranging. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 13A), recording media (DVD software and video tape) Etc., see FIG. 13 (B)), packaging containers (wrapping paper, bottles, etc., see FIG. 13 (C)), vehicles (bicycles, etc., see FIG. 13 (D)), personal items (bags, glasses, etc.) ), Products such as foods, plants, animals, clothing, daily necessities, electronic devices, etc. and goods such as luggage tags (see FIGS. 13E and 13F) may be used. it can. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (also simply referred to as televisions, television receivers, television receivers), mobile phones, and the like.

The semiconductor device 1520 of the present invention is mounted on a printed board, and is fixed to the article by being attached to the surface of the article or embedded in the article. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin. Since the semiconductor device 1520 of the present invention is small, thin, and lightweight, it does not impair the design of the article itself even after being fixed to the article. In addition, by providing the semiconductor device 1520 of the present invention for bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and if this authentication function is utilized, forgery can be prevented. Can do. In addition, by providing the semiconductor device of the present invention in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved.

Next, one mode of an electronic device in which the semiconductor device of the present invention is mounted will be described with reference to the drawings. The electronic device illustrated here is a mobile phone, which includes housings 2700 and 2706, a panel 2701, a housing 2702, a printed wiring board 2703, operation buttons 2704, and a battery 2705 (see FIG. 14). The panel 2701 is detachably incorporated in the housing 2702, and the housing 2702 is fitted on the printed wiring board 2703. The shape and dimensions of the housing 2702 are changed as appropriate in accordance with the electronic device in which the panel 2701 is incorporated. A plurality of packaged semiconductor devices are mounted on the printed wiring board 2703, and the semiconductor device of the present invention can be used as one of them. The plurality of semiconductor devices mounted on the printed wiring board 2703 have any one function of a controller, a central processing unit (CPU), a memory, a power supply circuit, a sound processing circuit, a transmission / reception circuit, and the like.

The panel 2701 is electrically connected to the printed wiring board 2703 through the connection film 2708. The panel 2701, the housing 2702, and the printed wiring board 2703 are housed in the housings 2700 and 2706 together with the operation buttons 2704 and the battery 2705. A pixel region 2709 included in the panel 2701 is arranged so as to be visible from an opening window provided in the housing 2700.

As described above, the semiconductor device of the present invention is characterized in that it is small, thin, and lightweight, and the limited space inside the housings 2700 and 2706 of the electronic device can be effectively used due to the above characteristics. .

In addition, since the semiconductor device of the present invention includes a memory element having a simple structure in which a silicon film that undergoes a silicidation reaction by an external electric action is sandwiched between a pair of conductive layers, an electronic device using an inexpensive semiconductor device is provided. Can be provided. In addition, since the semiconductor device of the present invention can be easily integrated, an electronic device using the semiconductor device including a large-capacity memory circuit can be provided.

In addition, a memory device included in the semiconductor device of the present invention writes data by an external electric action, is nonvolatile, and can additionally write data. With the above feature, forgery due to rewriting can be prevented, and new data can be added and written. Therefore, an electronic device using a semiconductor device that achieves high functionality and high added value can be provided.

Note that the housings 2700 and 2706 are examples of the appearance of a mobile phone, and the electronic device according to the present embodiment can be transformed into various modes depending on the function and application.

In addition, this embodiment can be freely combined with the embodiment mode, Embodiment 1, Embodiment 2, or Embodiment 3.

By manufacturing using a large-area glass substrate, a large number of wireless chips can be provided at a time, and the unit price per unit can be reduced. Further, the antenna can be formed on the same substrate, and the mounting process can be eliminated.

The figure which shows process sectional drawing of this invention. The graph which shows the relationship between the electric current value just before the short circuit of antifuse ROM, and the diameter of opening. The graph which shows the relationship between the short voltage of antifuse type ROM, and the film thickness of a silicon film. Electrical characteristic graph of antifuse ROM. Sectional photograph figure of antifuse type ROM. The cross-sectional enlarged photograph figure of the antifuse type ROM, and its schematic diagram. The top view which shows an antenna. Sectional drawing which shows the manufacturing process of a wireless chip. Sectional drawing which shows the manufacturing process of a wireless chip. Sectional drawing which shows the manufacturing process of a wireless chip. Sectional drawing which shows the manufacturing process of a wireless chip. The figure which shows a block diagram. FIG. 14 illustrates an example of an electronic device. FIG. 14 illustrates an example of an electronic device. The figure which shows a prior art example.

Explanation of symbols

100a: first sheet 100b: second sheet 101: substrate 102 having an insulating surface: peeling layer 103: insulating layer 104: gate insulating film 105: first gate electrode 106: second gate electrode 107: first Electrode 108: source region 109: drain region 110: drain region 111: source region 112: channel formation region 113: channel formation region 114: interlayer insulating film 115: silicon film 116: source electrode 117: drain electrode 118: source electrode 119 : Third electrode 120: Second electrode 121: Connection electrode 122: Insulating film 123: Fourth electrode 124: Metal layer 125: Antenna 302A: Memory unit and drive circuit 302B: Memory unit and drive circuit 302C: Memory unit And driving circuit 302D: memory unit and driving circuit 302E: memory unit and driving circuit 03A: Antenna 303B: Antenna 303C: Antenna 303D: Antenna 303E: Antenna 501: Substrate 502: Metal layer 503: First insulating films 504 to 508: Gate electrode 509: First electrode 510: Side wall 511: Side wall 512: Gate insulating layer 513: insulating layer 514: source region or drain region 515: source region or drain region 516: channel formation region 517: source region or drain region 518: source region or drain region 519: LDD region 520: LDD region 521: Channel formation region 522: fourth insulating film 523: fifth insulating film 524: silicon layers 525-534: source or drain electrodes 535-539: gate lead-out wiring 540: second electrode 541: third electrode 542: first 4 electrode 543: 6 insulating film 544: lead wire 545: antenna base film 546: Antenna 600: antifuse-type ROM
601: Logic circuit portion 602: Memory portion 603: Antenna portion and power supply portion 604: First electrode lead-out wiring portion 701: Second electrode 702: Fifth electrode 1511 Power supply circuit 1512 Clock generation circuit 1513 Data demodulation / modulation Circuit 1514 Control circuit 1515 Interface circuit 1516 Memory circuit 1517 Data bus 1518 Antenna (antenna coil)
1519 Reader / Writer 1520 Semiconductor Device 1523a Sensor 1523b Sensor Circuit 2700 Housing 2701 Panel 2702 Housing 2703 Printed Wiring Board 2704 Operation Button 2705 Battery 2706 Housing 2708 Connection Film 2709 Pixel Area

Claims (11)

A driver circuit including a plurality of thin film transistors over a substrate having an insulating surface, and a plurality of memory elements;
The memory element is
A first electrode capable of reacting with silicon to form a silicide;
A silicon film on the first electrode;
A second electrode capable of reacting with silicon to form silicide on the silicon film;
Have
The gate electrode of the thin film transistor is the same material as the first electrode of the memory element,
The semiconductor device is characterized in that a source electrode or a drain electrode of the thin film transistor is made of the same material as the second electrode of the memory element. A driver circuit including a plurality of thin film transistors over a substrate having an insulating surface, a plurality of memory elements, and an antenna;
The memory element is
A first electrode capable of reacting with silicon to form a silicide;
A silicon film on the first electrode;
A second electrode capable of reacting with silicon to form silicide on the silicon film;
Have,
A connecting electrode below the prior SL antenna,
The antenna is electrically connected to the connection electrode;
The connection electrode is electrically connected with the thin film transistor,
The gate electrode of the thin film transistor is the same material as the first electrode of the memory element,
The semiconductor device is characterized in that the connection electrode is made of the same material as the source electrode and the drain electrode of the thin film transistor and is made of the same material as the second electrode of the memory element. In claim 1 or 2,
The semiconductor device, wherein the silicon film contains oxygen or nitrogen. A semiconductor device having a memory element and a thin film transistor,
Having a first semiconductor layer over a substrate having an insulating surface;
A first insulating film on the substrate and the first semiconductor layer;
A first electrode having a region overlapping with the first semiconductor layer through the first insulating film;
A second electrode on the first insulating film;
A second insulating film on the first electrode and the second electrode;
A first opening provided in a region overlapping the first semiconductor layer of the second insulating film;
A second opening provided in a region overlapping the second electrode of the second insulating film;
A second semiconductor layer in contact with the second electrode in the second opening;
A third electrode on the second insulating film;
A fourth electrode on the second insulating film;
The third electrode is electrically connected to the first semiconductor layer through the first opening;
The fourth electrode has a region overlapping with the second electrode through the second semiconductor layer,
The memory element includes the second electrode, the second semiconductor layer, and the fourth electrode,
The thin film transistor includes the first semiconductor layer, the first electrode, and the third electrode,
The first electrode is the same material as the second electrode,
The semiconductor device, wherein the third electrode is made of the same material as the fourth electrode. In claim 4,
The second semiconductor layer is a silicon film;
The semiconductor device, wherein the silicon film contains oxygen or nitrogen. In any one of Claims 1 thru | or 5 ,
The semiconductor device is characterized in that the first electrode contains one element selected from titanium, tungsten, nickel, chromium, molybdenum, tantalum, cobalt, zirconium, vanadium, palladium, hafnium, platinum, and iron. In any one of Claims 1 thru | or 6 ,
The semiconductor device, wherein the second electrode includes one element selected from titanium, tungsten, nickel, chromium, molybdenum, tantalum, cobalt, zirconium, vanadium, palladium, hafnium, platinum, and iron. In any one of Claims 1 thru | or 7 ,
The semiconductor device is characterized in that the substrate is one of a glass substrate, a plastic film, and paper. In any one of Claims 1 thru | or 8 ,
Said first electrode and said second electrode wherein a is different materials. A drive circuit including a plurality of thin film transistors on the same substrate, a method for manufacturing a semiconductor device having a plurality of memory devices,
Forming a first semiconductor layer over a substrate having an insulating surface;
Forming a first insulating film on the first semiconductor layer;
Forming a first electrode overlying the first semiconductor layer on the first insulating film, and a second electrode over the first insulating film;
Forming a second insulating film covering the first electrode and the second electrode;
Etching the second insulating film to form a first opening reaching the second electrode;
Forming a second semiconductor layer covering the first opening;
Etching the second insulating film to form a second opening reaching the first semiconductor layer;
Forming a third electrode overlapping the first opening and a fourth electrode overlapping the second opening on the second insulating film;
The memory element includes the second electrode, the second semiconductor layer, and the third electrode,
The method for manufacturing a semiconductor device, wherein the thin film transistor includes the first semiconductor layer, the first electrode, and the fourth electrode. In claim 10 ,
After the first opening is formed, the second semiconductor layer is formed by exposure to the atmosphere, and a method for manufacturing a semiconductor device is provided.