JPH08316324A - Method of manufacturing semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To reduce manufacturing steps by breaking down the insulation of the antii-fuse insulating films of selected anti-fuse elements and forming conductor paths that electrically connect between lower electrodes and upper electrodes. CONSTITUTION: The steps of forming anti-fuse elements F include the steps of forming lower electrode 7, forming anti-fuse connecting holes 9F, forming anti-fuse insulating films 10 and forming upper electrodes 11 at least. Breaking down the insulation of the selected anti-fuse insulating films 10 of the anti-fuse elements F, conductor paths 14 between the lower electrodes 7 and the upper electrodes 11 are formed. The step of forming wiring connection holes 9C serve as the step of forming the anti-fuse connecting holes 9F. Therefore, the number of steps of manufacturing semiconductor integrated circuit device are reduced by the step equivalent to the step of forming anti-fuse connecting holes 9F.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device having an antifuse element. In particular, the present invention relates to a field programmable gate array (hereinafter,
The present invention relates to a method for manufacturing a semiconductor integrated circuit device having an anti-fuse element, such as an FPGA or a programmable read only memory (hereinafter referred to as PROM).

[0002]

2. Description of the Related Art In a gate array, an anti-fuse element described in the following document is arranged in a semiconductor integrated circuit device such as FPGA and PROM which can be programmed in the field by a user. IEEE, Electron Device Let
ter, Vol. 12, No. 4, April 1991 pp. 151-153,
IEEE, Electron Device Letter, Vol. 13, N
o.9, September 1992 pp.488-490.

In a conductive state where no program is written or no data is written, each of the lower layer electrode, the anti-fuse insulating film, and the upper layer electrode is sequentially laminated to form the anti-fuse element. The anti-fuse insulating film is destroyed in a conductive state in which a program is written or data is written, and a conductive path for electrically connecting the lower layer electrode and the upper layer electrode is formed in the antifuse element. It Usually, a plurality of antifuse elements are arranged in a matrix, and a conduction path is formed in any of the plurality of antifuse elements. That is, in the FPGA, the antifuse element can be arbitrarily turned on and off after the manufacturing process is completed, and programming can be freely performed. On the other hand, P
Similarly, in the ROM, after the manufacturing process is completed, the antifuse element can be arbitrarily turned on and off, and data can be freely written.

A high voltage for writing is used to destroy the insulating film for antifuse. This writing voltage is applied between the lower layer electrode and the upper layer electrode of the antifuse element.

[0005]

In the semiconductor integrated circuit device having the antifuse element described above, the step of forming the antifuse element is incorporated in the manufacturing process of the semiconductor integrated circuit device. The step of forming the antifuse element requires a step of forming a lower layer electrode, a step of forming an antifuse connection hole, a step of forming an antifuse insulating film, and a step of forming an upper layer electrode.
Therefore, the number of manufacturing steps of the semiconductor integrated circuit device increases. The increase in the number of manufacturing steps significantly reduces the manufacturing yield of semiconductor integrated circuit devices.

The present invention has been made to solve the above problems, and an object of the present invention is to reduce the number of manufacturing steps in a method of manufacturing a semiconductor integrated circuit device having an antifuse element.

[0007]

In order to achieve the above object, the invention according to claim 1 comprises a step of forming a plurality of first wirings and a plurality of lower layer electrodes of an anti-fuse element on a substrate. A step of forming an interlayer insulating film covering the first wiring and the lower layer electrode, and forming a wiring connection hole in the interlayer insulating film on the first wiring and simultaneously forming an interlayer insulating film on the lower layer electrode for antifuse. Forming a connection hole; forming an anti-fuse insulating film on at least the lower layer electrode in the anti-fuse connection hole; and electrically connecting the first wiring to the first wiring through the wiring connection hole on the interlayer insulating film. A second wiring that is electrically connected and an upper electrode of an antifuse element that is connected to the lower electrode through an antifuse insulating film through the antifuse connection hole. For example, to destroy the anti-fuse insulating film of any of the anti-fuse element of the plurality, and forming a conductive path for electrically connecting between the lower electrode and the upper electrode.

In the invention according to claim 1, the anti-fuse connection hole for connecting the lower layer electrode and the upper layer electrode of the antifuse element has a wiring connection for connecting the first wiring and the second wiring. The holes are formed at the same time in the process of forming the holes. That is, the step of forming the anti-fuse connection hole can also be used as the step of forming the wiring connection hole. Therefore, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of forming the anti-fuse connection hole.

According to a second aspect of the invention, in the method of manufacturing a semiconductor integrated circuit device according to the first aspect, the steps of forming the first wiring and the lower electrode of the antifuse element are the same step. This is a step of simultaneously forming the first wiring and the lower layer electrode in the wiring layer.

In the invention according to claim 2, the first wiring and the lower wiring of the anti-fuse element are simultaneously formed in the same step. That is, the step of forming the lower electrode of the anti-fuse element can also be used as the step of forming the first wiring. Therefore, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of forming the lower layer electrode of the antifuse element.

According to a third aspect of the invention, in the method of manufacturing a semiconductor integrated circuit device according to the first or second aspect, the steps of forming the second wiring and the upper electrode of the antifuse element are the same. In the step, the second wiring and the upper layer electrode are simultaneously formed in the second wiring layer.

In the invention according to claim 3, the second wiring and the upper wiring of the anti-fuse element are simultaneously formed in the same step. That is, the step of forming the upper layer electrode of the anti-fuse element can also be used as the step of forming the second wiring. Therefore, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of forming the upper layer electrode of the anti-fuse element.

According to a fourth aspect of the present invention, a step of forming a plurality of first wirings and a plurality of lower layer electrodes of an anti-fuse element on a substrate, and an interlayer insulating film that covers the first wirings and the lower layer electrodes are formed. A step of forming a wiring connecting hole in the interlayer insulating film on the first wiring and at the same time forming an antifuse connecting hole in the interlayer insulating film on the lower layer electrode; Forming an anti-fuse insulating film on the entire surface of the interlayer insulating film including on the lower layer electrode, and connecting to the lower layer electrode through the anti-fuse insulating film in the formation region of the anti-fuse element through the anti-fuse insulating film Forming an upper electrode of the antifuse element and removing at least the antifuse insulating film on the first wiring in the wiring connection hole in the same step. And a step of forming, on the interlayer insulating film, a second wiring electrically connected to the first wiring through the wiring connection hole, the antifuse of any one of the plurality of antifuse elements. It is characterized in that the insulating film is destroyed to form a conduction path for electrically connecting the lower layer electrode and the upper layer electrode.

In the invention according to claim 4, in addition to the function and effect obtained by the invention according to claim 1, the inside of the wiring connection hole is formed in the same step as the step of forming the upper layer electrode of the anti-fuse element. The anti-fuse insulating film on the first wiring is removed. That is, the step of removing the antifuse insulating film on the first wiring in the wiring connection hole can also be used as the step of forming the upper layer electrode of the antifuse element. Therefore, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of removing the antifuse insulating film on the first wiring in the wiring connection hole.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor integrated circuit device according to the fourth aspect, the step of forming the first wiring and the lower electrode of the anti-fuse element is the uppermost layer. First having metal silicide film
Forming a wiring and a lower layer electrode, and forming the upper layer electrode of the antifuse element and removing at least the antifuse insulating film on the first wiring in the wiring connection hole in the same step. A step of forming an upper layer electrode of the fuse element and removing at least the anti-fuse insulating film on the first wiring and the uppermost metal silicide film of the first wiring in the wiring connection hole in the same step And

According to the invention of claim 5, the following effects can be obtained in addition to the effects of the invention of claim 4. First, the antifuse insulating film on the first wiring and the uppermost metal silicide film of the first wiring in the wiring connection hole are removed in the same step as the step of forming the upper layer electrode of the antifuse element. It That is,
The step of removing the anti-fuse insulating film on the first wiring in the wiring connection hole and the metal silicide film of the uppermost layer of the first wiring can be combined with the step of forming the upper electrode of the anti-fuse element. Therefore, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of removing the anti-fuse insulating film on the first wiring and the uppermost metal silicide film of the first wiring in the wiring connection hole. . Secondly, since the metal silicide film is formed on the uppermost layer of the lower electrode of the anti-fuse element, when the anti-fuse insulating film of any anti-fuse element is destroyed to form a conductive path, the conductive path is formed in the conductive path. The characteristics are improved based on the metal silicide film. For example, when the metal silicide film has atoms having excellent electromigration (EM) resistance, the EM resistance can be improved in the conductive path. In addition, when the formation temperature of the metal silicide film is controlled to a low temperature, the grain size is finely controlled, or the like, the quality of the anti-fuse insulating film of the anti-fuse element is improved. On the other hand, since the metal silicide film of the first wiring is removed, the connection resistance value corresponding to the metal silicide film can be reduced in the electrical connection between the first wiring and the second wiring.

According to a sixth aspect of the present invention, a step of forming a plurality of first wirings each having a metal silicide film as an uppermost layer and a plurality of lower layer electrodes of an anti-fuse element on a substrate, the first wiring and Forming an interlayer insulating film covering the lower electrode, etching the interlayer insulating film on the first wiring until the uppermost metal silicide film of the first wiring is removed, and forming a wiring connecting hole; At the same time, the anti-fuse having an opening size smaller than the opening size of the wiring connection hole is formed in a state where the interlayer insulating film on the lower electrode is simultaneously etched under the same condition and the uppermost metal silicide film of the lower electrode is not removed. A step of forming a connection hole, and a step of forming an antifuse insulating film on at least the lower layer electrode in the antifuse connection hole;
The first through-hole for wiring is formed on the interlayer insulating film.
A second wiring electrically connected to the wiring and a step of forming an upper layer electrode of an antifuse element connected to the lower layer electrode through the antifuse insulating film through the antifuse connection hole, The anti-fuse insulating film of any anti-fuse element among the plurality is destroyed,
It is characterized in that a conduction path for electrically connecting the lower layer electrode and the upper layer electrode is formed.

In the invention according to claim 6, the following effects can be obtained in addition to the effects obtained by the invention according to claim 1. First, the opening size of the anti-fuse connecting hole is set smaller than the opening size of the wiring connecting hole, and the wiring connecting hole and the anti-fuse connecting hole are formed under the same etching condition. The smaller the opening size of the connection hole, the lower the reaction medium supply efficiency and the reaction product discharge efficiency. Therefore, when forming the anti-fuse connection hole as compared with the etching rate when forming the wiring connection hole. The etching rate can be slowed. That is, the uppermost metal silicide film of the first wiring can be removed and the uppermost metal silicide film of the lower electrode can be left without a mask process. Therefore, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced because the masking step is not required. Secondly, since the metal silicide film is formed on the uppermost layer of the lower electrode of the anti-fuse element, when the anti-fuse insulating film of any anti-fuse element is destroyed to form a conductive path, the conductive path is formed in the conductive path. The characteristics are improved based on the metal silicide film. In addition, the opening size of the anti-fuse connection hole is set to be small,
The number of defects generated in the anti-fuse insulating film in one anti-fuse connection hole can be reduced. On the other hand, since the metal silicide film of the first wiring is removed, the connection resistance value corresponding to the metal silicide film can be reduced in the electrical connection between the first wiring and the second wiring.

[0019]

EXAMPLES The structure of the present invention will be described below with reference to examples.

Embodiment 1 FIGS. 1 to 7 are cross-sectional views showing the essential part of each step for explaining a method of manufacturing a semiconductor integrated circuit device having an anti-fuse element according to Embodiment 1 of the present invention. In this embodiment, an FPGA or PROM is mounted on the semiconductor integrated circuit device. This FPGA or PROM (including peripheral circuits) has a complementary MISFET (Metal Insulator Semiconductor).
ctor Field Effect Transistor) is adopted.

First, in the first step, as shown in FIG. 1, a MISFET (right side in FIG. 1) and an antifuse element lower layer electrode 7 (FIG. 1) constituting an FPGA or PROM are formed on the main surface of the semiconductor substrate 1. Middle, left) is formed. In this embodiment, a single crystal silicon substrate is used as the semiconductor substrate 1, and the single crystal silicon substrate is set to p type.

FIG. 1 shows an n-channel MISFET of the complementary MISFETs, and the p-channel MISFET is not shown because the channel conductivity type is different but the basic structure is the same. The n-channel MISFET is formed on the main surface of the p-type well region 2 in a region surrounded by the element isolation body 3 and the p-type channel stopper region 4. Although not shown, the p-channel MISFET is formed on the main surface of the n-type well region in the region surrounded by the element isolation body 3. The p-type well region 2 and the n-type well region are formed on the semiconductor substrate 1, and the semiconductor substrate 1 has a twin well structure. The element isolation body 3 is formed of a thick field insulating film (silicon oxide film) obtained by oxidizing the surface of the semiconductor substrate 1 by a selective oxidation method.

The n-channel MISFET includes a p-type well region 2 serving as a channel forming region, a gate insulating film 5, a gate electrode 6, a source region 7 and a drain region 7. Similarly, the p-channel MISFET serves as a channel forming region.
It includes a mold well region, a gate insulating film 5, a gate electrode 6, a source region and a drain region. Which MISFET
Although not limited to this structure, LDD (Lightly Dop)
ed Drain) structure is adopted. LD is not attached
In the MISFET adopting the D structure, the sidewall spacer is formed on the side wall of the gate electrode 6, and the impurity concentration is set low on the channel formation region side of the drain region 7. Since the manufacturing method of the MISFET adopting the LDD structure is well known, the description of the manufacturing method is omitted.

In this embodiment, the semiconductor substrate 1 has a twin well structure having the p-type well region 2 and the n-type well region, but the structure is not limited to this.
That is, for example, the semiconductor substrate 1 may be configured as a p-type and the semiconductor substrate 1 may be configured as a single well structure in which the p-type well region 2 is omitted.

Further, a salicide structure is adopted in each of the complementary MISFETs described above. That is, in the n-channel MISFET, the gate electrode 6 is formed of the polycrystalline silicon film 6A and the metal silicide film 6B laminated thereon, and the source region 7 and the drain region 7 are both n-type semiconductor regions (diffusion regions) 7A. And the metal silicide film 7B laminated thereover. The metal silicide films 6B and 7B are simultaneously formed in the same manufacturing process as described below.

First, the polycrystalline silicon film 6A of the gate electrode 6,
The n-type semiconductor region 7A of the source region 7 or the drain region 7
After each is formed, a metal film is formed on the entire surface of the substrate including the polycrystalline silicon film 6A and the n-type semiconductor region 7A. The polycrystalline silicon film 6A is formed by either a CVD method or a sputtering method and has a film thickness of 400 nm, for example. In the n-type semiconductor region 7A, n-type impurities are introduced by the ion implantation method, and the introduced n-type impurities are activated. In this embodiment, a Ti film is used as the metal film. For example, a Ti film is deposited by a sputtering method and has a film thickness of 40
nm. After the Ti film is formed, for example, the first lamp heating (Rapid Thermal Annealing) is performed on the Ti film.
A silicidation process is performed by. Lamp heating is 65
It is performed at 0 ° C. for about 30 seconds. By this silicidation treatment, Si of the polycrystalline silicon film 6A of the gate electrode 6 and Ti of the Ti film are formed.
React with each other to form a metal silicide film (titanium silicide film) 6B on the polycrystalline silicon film 6A. Similarly, S of the n-type semiconductor region 7A of the source region 7 or the drain region 7 is
i reacts with Ti of the Ti film to form a metal silicide film (titanium silicide film) 7B on the n-type semiconductor region 7A. After that, the unreacted Ti film is changed to the metal silicide film 6
B and 7B are selectively removed. Unreacted Ti
A H ₂ SO ₄ solution is used to remove the film. Then, the metal silicide films 6B and 7B are subjected to the second lamp heating. Lamp heating is 800 to reduce resistance
It is performed at 30 ° C. for about 30 seconds.

In the present embodiment, Ti is used for the metal film, but in the present invention, materials other than Ti, such as Ta, Nb, Zr, Y, Hf, Al, W, M are used for the metal film.
Any of o, Cr, V, Mn, Fe, Co, Ni, Pd, and Pt can be used.

The lower layer electrode 7 of the antifuse element is n
It is formed of the type semiconductor region 7A and the metal silicide film 7B. The n-type semiconductor region 7A of the lower layer electrode 7 is formed in the same manufacturing process as the n-type semiconductor region 7A of the source region 7 or the drain region 7 of the n-channel MISFET. Similarly, the metal silicide film 7B of the lower electrode 7 is an n-channel M
It is formed in the same manufacturing process as the metal silicide film 7B of the source region 7 or the drain region 7 of the ISFET. That is, since the lower layer electrode 7 of the anti-fuse element is formed in the same manufacturing process as the source region 7 or the drain region 7 of the n-channel MISFET, the number of manufacturing processes of the semiconductor integrated circuit device is increased by the number of processes used. Can be reduced.

In the second step, the complementary MISF is used.
An interlayer insulating film 8 is formed on the entire surface of the substrate including the ET and the lower electrode 7 of the anti-fuse element, and a wiring connecting hole 9C and an anti-fuse connecting hole 9F are formed in the interlayer insulating film 8 as shown in FIG. To be done. The wiring connection hole 9C is shown in FIG.
Inside, it is respectively formed on the source region 7 and the drain region 7 of the n-channel MISFET. The anti-fuse connection hole 9F is formed on the lower layer electrode 7 in the formation region of the anti-fuse element. Antifuse connection hole 9F
Are simultaneously formed in the same manufacturing process as the process of forming the wiring connection hole 9C. Therefore, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of forming the anti-fuse connection hole 9F.

The interlayer insulating film 8 is formed of, for example, a silicon oxide film and has a film thickness of, for example, 1.0 μm. The wiring connecting hole 9C and the anti-fuse connecting hole 9F are both formed by photolithography and etching, and the opening size is, for example, a square having one side of 1.0 μm.

In the third step, although not shown, the inside of the wiring connecting hole 9C and the anti-fuse connecting hole 9F are formed.
A wet process is performed on the surface of the metal silicide film 7B, which is the uppermost layer of the lower electrode 7, in the inside of the antifuse connection hole 9F. The wet treatment is performed by removing oxides or nitrides formed on at least the surface of the metal silicide film 7B during film formation or during exposure to the atmosphere, and the metal silicide film 7
It is performed for the purpose of removing a part of the film thickness from the surface of B in the depth direction. In the present embodiment, the wet treatment is performed with ammoniacal hydrogen peroxide solution (NH ₄ OH: H ₂
O ₂ : H ₂ O = 1: 1: 5, 70 ° C.) was used (AP
M cleaning is used), for example, a treatment for 5 minutes is performed. When the wet treatment is performed, oxides having poor film quality or nitrides having sharp projections are removed. Further, when the wet treatment is performed, a part of the metal silicide film 7B is removed, and the protrusions formed on the surface of the metal silicide film 7B due to the removal of the oxide or nitride are removed. As a result, planarization is promoted on the surface of the metal silicide film 7B.

If the same effect is obtained, a dry process can be used instead of the wet process. Specifically, an isotropic chemical dry etching process (Chemical Dry Etching) using a fluorine-based gas can be used. The isotropic chemical dry etching process is a non-plasma treatment method using Cl F ₃ gas (Cl F ₃ cleani).
ng), non-plasma processing method using F ₂ gas (F
₂ cleaning) can be used. In the non-plasma treatment method using Cl F ₃ system gas, for example, Ar: Cl F ₃
= 9: 1, 100 torr and 1 minute. In the non-plasma treatment method using F ₂ gas, for example, F ₂ : He = 3: 97, 1000 sccc
Processing is performed under conditions of m, 1 torr, substrate temperature of 200 ° C. and 3 minutes.

Further, the isotropic chemical dry treatment is performed by a plasma treatment method (NF ₃ cl) using an NF ₃ gas.
eaning), plasma processing method using a BCl3-containing gas (BCl ₃ cleaning), a plasma processing method using a mixed gas of CF ₄ based gas and O ₂ gas (CF ₄ cleaning)
Can be used. In a plasma treatment method using a BCl ₃ system gas, for example, BCl ₃ : Ar = 4: 1, 100
The processing is performed under the conditions of sccm, 0.1 torr, high frequency output 13.56 MHz, substrate temperature 200 ° C. and 3 minutes. In a plasma processing method using a mixed gas, for example, CF ₄ : O ₂ = 8: ₂ , 100 sccm, 0.1 torr,
The treatment is performed under the conditions of a high frequency output of 13.56 MHz, a substrate temperature of 30 ° C. and 2 minutes.

Further, CF ₄ and C ₂ F are used as the processing gas.
Fluorine-based gas such as ₆ , CH ₂ F ₂ , CH ₃ F and SF ₆ can be used.

In the fourth step, as shown in FIG.
At least the lower layer electrode 7 in the anti-fuse connection hole 9F
The anti-fuse insulating film 10 is formed thereon. In this embodiment, the anti-fuse insulating film 10 is formed on the entire surface of the interlayer insulating film 8 including the surface of the lower layer electrode 7 in the anti-fuse connecting hole 9F. As the antifuse insulating film 10, a silicon nitride film is used in this embodiment. The silicon nitride film is deposited by a plasma CVD method using a gas phase reaction of silane, ammonia and nitrogen gas, and has a film thickness of 10 nm, for example. In the anti-fuse connection hole 9F, since the sharp protrusions are reduced and the flatness is promoted on the surface of the metal silicide film 7B of the lower electrode 7, the defect density in the anti-fuse insulating film 10 is reduced and uniform. Good film quality can be obtained.

The anti-fuse insulating film 10 includes a silicon nitride film, a single layer film of a silicon oxide film or a tantalum oxide film, or a silicon nitride film, a silicon oxide film, or a tantalum oxide film, and they are stacked. Composite membranes can be used.

In the fifth step, as shown in FIG. 4, an upper layer electrode 11 of the antifuse element is formed on the entire surface of the substrate on the surface of the antifuse insulating film 10. In this embodiment, a TiN film is used for the upper electrode 11. The TiN film is formed by, for example, a sputtering method and has a film thickness of 4
It is formed at 0-60 nm. The upper electrode 11 is made of Ti
Not limited to the N film, refractory metals such as Ti and W, Al, A
It is possible to use a single layer film such as an Al alloy (at least one of Si and Cu is added to Al) or a composite film including these films.

In the sixth step, the upper electrode 11 and the anti-fuse insulating film 10 are sequentially patterned as shown in FIG. 5, and the anti-fuse element F is formed in this step. That is, the anti-fuse element F includes the lower electrode 7, the anti-fuse insulating film 10 and the upper electrode 1.
1 is formed. The anti-fuse element F shown in FIG. 5 is in a non-conductive state in which programming or data writing is not performed, and the anti-fuse insulating film 10 is interposed between the lower layer electrode 7 and the upper layer electrode 11.

Photolithography and etching are used for patterning the upper electrode 11 and the anti-fuse insulating film 10. In etching, anisotropic etching using a chlorine-based or fluorine-based etching gas is used. Also, isotropic etching may be used. In the patterning of the upper layer electrode 11 of the anti-fuse element F, the upper layer electrode 11 of the area other than the anti-fuse element F, that is, the complementary MISFET forming area is simultaneously removed in the same manufacturing process. That is, the step of removing the unnecessary upper layer electrode 11 also serves as the step of patterning the upper layer electrode 11 of the anti-fuse element F. Therefore, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of removing the unnecessary upper layer electrode 11. Similarly, in the patterning of the anti-fuse insulating film 10 of the anti-fuse element F, a region other than the anti-fuse element F, that is, a complementary MIS.
The anti-fuse insulating film 10 in the FET formation region is simultaneously removed in the same manufacturing process. That is, the step of removing the unnecessary anti-fuse insulating film 10 is also used as the step of patterning the anti-fuse insulating film 10 of the anti-fuse element F. Therefore, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of removing the unnecessary anti-fuse insulating film 10.

In the seventh step, the wiring 12 is formed on the interlayer insulating film 8 as shown in FIG. Complementary MISF
In the ET formation region, the wiring 12 is electrically connected to either the source region 7 or the drain region 7 through the wiring connection hole 9C. The wiring 12 is electrically connected to the upper layer electrode 11 of the antifuse element F in the antifuse element formation region. In this embodiment, the wiring 12 is the Ti film 12
A, TiN film 12B, Al (Al-Cu) film 12C, T
It is formed of a composite film in which the iN film 12D is sequentially stacked.

In the eighth step, although not shown, a final passivation film is formed on the entire surface of the substrate. When these series of steps are completed, the semiconductor integrated circuit device having the anti-fuse element F is completed.

In the ninth step, as shown in FIG. 7, an optional anti-fuse element F in the semiconductor integrated circuit device is used.
A program or data is written in the. That is, the lower electrode 7 and the upper electrode 11 of the anti-fuse element F are
The anti-fuse insulating film 10 is destroyed by the high write voltage applied between and. The destruction of the anti-fuse insulating film 10 forms a conduction path (filament) 14 between the lower layer electrode 7 and the upper layer electrode 11 to electrically connect them.

As described above, in the method of manufacturing the semiconductor integrated circuit device having the antifuse element F according to this embodiment, the antifuse connecting the lower layer electrode 7 and the upper layer electrode 11 of the antifuse element F is connected. Connection hole 9
F is a wiring connection hole 9C for connecting the source region 7 or the drain region 7 (first wiring) and the wiring (second wiring) 12
Are formed simultaneously in the step of forming. That is, the step of forming the anti-fuse connection hole 9F includes the wiring connection hole 9C.
Can also be used in the step of forming. Therefore, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of forming the anti-fuse connection hole 9F.

Further, in the same step as the step of forming the upper layer electrode 11 of the antifuse element F, the antifuse insulating film 1 on the source region 7 in the wiring connection hole 9C is formed.
0 is removed. That is, the step of removing the antifuse insulating film 10 on the source region 7 and the like in the wiring connection hole 9C can also be used in the step of forming the upper layer electrode 11 of the antifuse element F. Therefore, 9C in the wiring connection hole
The number of manufacturing steps of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of removing the anti-fuse insulating film 10 on the source region 7 and the like.

Embodiment 2 This embodiment is a second embodiment of the present invention in which an anti-fuse element is formed in the wiring layer of a semiconductor integrated circuit device.

FIGS. 8 to 12 are sectional views showing the principal part of each step for explaining the method of manufacturing the semiconductor integrated circuit device having the anti-fuse element according to the second embodiment of the present invention.

First, in the first step, as shown in FIG. 8, a plurality of wirings 12 and a lower electrode 12F of the antifuse element are formed on the interlayer insulating film 8, that is, on the first wiring layer above the complementary MISFET. It In this embodiment, the wiring 12 and the lower electrode 12F are both made of TiN film 12e and Al.
The composite film is formed by sequentially stacking the alloy film 12f, the TiN film 12g, and the WSix film 12h. The bottom TiN film 12e is used as a barrier metal film. The Al alloy film 12f is formed as a main body of wiring. TiN film 12g
Is used as an antireflection film. The top layer, WSix
The film 12h is mainly used to improve the film quality of the anti-fuse insulating film (17) of the anti-fuse element.

In this embodiment, the WSix film 12h is deposited by, for example, the sputtering method and has a film thickness of 50 to 200 nm. When the deposition temperature of the WSix film 12h is set to a low temperature of 800 ° C. or lower, the WSix film 12h is formed with an amorphous structure and has no grain boundary.
The surface of 2h is promoted to be flat. As a result, WSix
The anti-fuse insulating film (17) formed on the film 12h has fewer defects and can be improved in film quality. Further, when the WSix film 12h is formed at a low temperature, it is about 20n.
Fine crystal grains of m or less are formed, and similarly, the film quality of the anti-fuse insulating film can be improved. The metal silicide film of Ti or the like described in the first embodiment can be used for the uppermost layer of the lower electrode 12.

The wiring 12 and the lower layer electrode 12F are simultaneously formed in the same manufacturing process. That is, the step of forming the lower layer electrode 12F of the anti-fuse element is also used as the step of forming the wiring 12, and the number of manufacturing steps of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of forming the lower layer electrode 12F.

In the second step, the interlayer insulating film 15 is formed on the entire surface of the substrate including the wiring 12 and the lower electrode 12F of the anti-fuse element. As shown in FIG. 9, the interlayer insulating film 15 is used for wiring. The connection hole 16T and the anti-fuse connection hole 16F are formed. The wiring connection hole 16T is formed on the wiring 12, and the anti-fuse connection hole 16F is formed in the lower fuse electrode 12F in the formation region of the anti-fuse element.
Formed on top. Similar to the first embodiment, the wiring connection hole 16T and the anti-fuse connection hole 16F are formed in the same manufacturing process.

Further, in this embodiment, the opening size of the wiring connecting hole 16T is set larger than the opening size of the anti-fuse connecting hole 16F. Then, anisotropic etching is used first and isotropic etching is used finally to form the wiring connection hole 16T and the anti-fuse connection hole 16F. That is, the wiring connection hole 16T
In the formation of, since the opening size is large and the reaction medium supply capacity and the reaction product discharge capacity are high, the etching rate of anisotropic etching is increased. That is, etching of the uppermost layer of the wiring 12 is started before reaching the uppermost layer of the lower layer electrode 12F. Therefore, in the wiring 12, the uppermost layer WSix film 12h is removed when the wiring connection hole 12 is formed, and the surface of the intermediate TiN film 12g is exposed. The WSix film 12 which is the uppermost layer of the wiring 12.
By removing h, the number of intervening layers of a film having a higher specific resistance than Al or an Al alloy can be reduced between the wiring 12 and the upper wiring (19), so that the connection resistance value between the wirings can be reduced.

On the other hand, in the formation of the anti-fuse connection hole 16F, the etching rate of anisotropic etching is slow because the opening size is small and the reaction medium supply capacity and reaction product discharge capacity are low. That is, at the stage when the etching of the uppermost layer of the wiring 12 is started, the lower electrode 12
The etching of the uppermost layer of F has not started. That is,
In the lower electrode 12F, the uppermost layer is the WSix film 1
With 2 h remaining, anisotropic etching is completed and switched to isotropic etching. And the lower layer electrode 1
The uppermost surface of the 2F, the WSix film 12h, isotropically etched to promote planarization of the surface. For the isotropic etching, the wet process described in the first embodiment is used.

In this embodiment, one side of the wiring connection hole 16T has a width of 1.0 μm due to the difference in etching rate.
And one side of the anti-fuse connection hole 16F is set to 0.8 μm. In this way, the wiring connection hole 16
Since the etching rate can be controlled by making a difference between the opening size of T and the opening size of the anti-fuse connection hole 16F, the etching depth of the wiring connection hole 16T and the anti-fuse connection hole 16F are changed. The number of steps can be reduced. Specifically, at least one mask forming process can be reduced.

In the third step, as shown in FIG. 10, the anti-fuse insulating film 17 is formed on the entire surface of the interlayer insulating film 15 including the surface of the lower layer electrode 12F in the anti-fuse connecting hole 16F. It A silicon nitride film is used for the anti-fuse insulating film 10 as in the first embodiment.

In the fourth step, the upper layer electrode 18 of the antifuse element is formed on the surface of the antifuse insulating film 17, as shown in FIG. Example 1 described above
Similarly to the above, when the upper layer electrode 18 is formed, the unnecessary upper layer electrode 18 and the anti-fuse insulating film 17 other than the formation region of the anti-fuse element are removed. In the present embodiment, the upper electrode 18 is formed of a composite film of an Al alloy (Al—Cu) film 18A and a TiN film 18B laminated thereon. The Al alloy film 18A of the upper electrode 18 is formed by, for example, a sputtering method and has a film thickness of 10-100 nm.
When a program or data is written and a conductive path is formed, Al atoms of the Al alloy film 18A are taken into the conductive path, and the resistance value of the conductive path can be reduced.
The TiN film 18B is formed by the sputtering method and has a film thickness of 20-
It is formed at 50 nm. The TiN film 18B has a function as a barrier metal film and an antireflection film. Upper layer wiring 18
Since the film thickness of is higher than that of the wiring (19) formed in the upper layer, it does not affect the step coverage of the wiring in the upper layer.

When the step of forming the upper electrode 18 is completed, the anti-fuse element F is completed. The antifuse element F includes the lower electrode 12F and the antifuse insulating film 17
And the upper electrode 18.

In the fifth step, the wiring 19 is formed on the interlayer insulating film 15 as shown in FIG. Complementary MI
In the SFET formation region, the wiring 19 is the wiring connection hole 16
It is electrically connected to the wiring 12 through T. The wiring 19 is electrically connected to the upper electrode 18 of the antifuse element F in the antifuse element formation region. In this embodiment, the wiring 19 is made of TiN film 19A and Al (Al-Cu).
It is formed of a composite film in which a film 19B and a TiN film 19C are sequentially laminated.

In the sixth step, although not shown, a final passivation film is formed on the entire surface of the substrate. When these series of steps are completed, the semiconductor integrated circuit device having the anti-fuse element F is completed.

In the seventh step, programming or data writing is performed on any antifuse element F.

In the present invention, the unnecessary antifuse insulating film 17 is removed in the same step as the patterning for forming the upper layer electrode 18 of the antifuse element F shown in FIG. The uppermost WSix film 12h of the wiring 12 can be removed.

As described above, in the method of manufacturing the semiconductor integrated circuit device having the anti-fuse element F according to this embodiment, the following effects can be obtained in addition to the effects obtained in the first embodiment.

First, in the same step as the step of forming the upper electrode 18 of the anti-fuse element F, the anti-fuse insulating film 17 on the wiring 12 in the wiring connection hole 16T and the uppermost WSix of the wiring 12 are formed. The film 12h is removed.
That is, the anti-fuse insulating film 17 on the wiring 12 in the wiring connection hole 16T and the uppermost WSi of the wiring 12 are formed.
The step of removing the x film 12h can also be used as the step of forming the upper layer electrode 18 of the anti-fuse element F. Therefore, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of removing the anti-fuse insulating film 17 on the wiring 12 in the wiring connection hole 16T and the uppermost WSix film 12h of the wiring 12. .

Second, since the WSix film 12h is formed on the uppermost layer of the lower electrode 12 of the anti-fuse element F,
When the anti-fuse insulating film 17 of any anti-fuse element F is destroyed and a conduction path is formed, the characteristics are improved in the conduction path based on the WSix film 12h. For example, since the WSix film 12h has W atoms having excellent EM resistance, the EM resistance can be improved in the conductive path. Also,
When the formation temperature of the WSix film 12h is controlled to a low temperature and the grain size is finely controlled, the quality of the anti-fuse insulating film 17 of the anti-fuse element F is improved. On the other hand, since the WSix film 12h of the wiring 12 is removed, the connection resistance value corresponding to the WSix film 12h can be reduced in the electrical connection between the wiring 12 and the wiring 19.

Thirdly, the opening size of the anti-fuse connecting hole 16F is set smaller than the opening size of the wiring connecting hole 16T, and the wiring connecting hole 16T and the anti-fuse connecting hole 16F are respectively etched under the same etching condition. It is formed. The smaller the opening size of the connection hole, the lower the reaction medium supply efficiency and the reaction product discharge efficiency. Therefore, the anti-fuse connection hole 16F is formed as compared with the etching rate when the wiring connection hole 16T is formed. The etching rate can be slowed down. That is, the uppermost WSix film 12h of the wiring 12 can be removed and the uppermost WSix film 12h of the lower layer electrode 12F can be left without a mask process. Therefore, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced because the masking step is not required.

Fourthly, since the opening size of the anti-fuse connecting hole 16F of the anti-fuse element F is set small, the number of defects generated in the anti-fuse insulating film 17 in one anti-fuse connecting hole 16F is small. Can be reduced.

Example 3 In this example, in the method of manufacturing a semiconductor integrated circuit device described in Example 2, the metal silicide film is formed on the uppermost layer of the lower electrode of the anti-fuse element, and the uppermost layer of wiring is formed. This is a third embodiment of the present invention in which a metal silicide film is not formed on the substrate.

FIGS. 13 to 17 are sectional views showing the essential part of each step for explaining the method of manufacturing the semiconductor integrated circuit device having the antifuse element according to the third embodiment of the present invention.

First, in the first step, the above-mentioned Example 2 was used.
Similar to the step shown in FIG. 8, the plurality of wirings 12 and the lower layer electrodes 12F of the anti-fuse element are formed on the first wiring layer on the interlayer insulating film 8. The wiring 12 and the lower electrode 12F are all made of a TiN film 12e, an Al alloy film 12f, and a TiN film 12
g and a WSix film 12h are sequentially laminated to form a composite film. The wiring 12 and the lower layer electrode 12F are simultaneously formed in the same manufacturing process.

In the second step, the uppermost WSix film 12h of the wiring 12 is removed as shown in FIG.
Lower layer electrode 12F in the formation region of the anti-fuse element
The WSix film 12h is left. The WSix film 12h can be selectively removed by forming an etching mask formed by the photolithography technique in the formation region of the anti-fuse element and performing etching.

In the present invention, the WSix film 12h is removed in advance in the region where the wiring 12 is formed before patterning the wiring 12 and the lower electrode 12F of the anti-fuse element, and then the wiring 12 and the lower electrode 12F are formed.
Patterning may be performed.

In the third step, the interlayer insulating film 15 is formed on the entire surface of the substrate including the wiring 12 and the lower electrode 12F of the anti-fuse element. As shown in FIG. 14, the interlayer insulating film 15 is connected to the wiring for wiring. The hole 16T and the anti-fuse connection hole 16F are formed. Similar to the second embodiment, the wiring connection hole 16T is formed on the wiring 12, and the anti-fuse connection hole 16F is formed on the lower layer electrode 12F in the formation region of the anti-fuse element. Connection hole for wiring 1
6T and anti-fuse connection hole 16F are formed in the same manufacturing process.

In the fourth step, as shown in FIG. 15, the anti-fuse insulating film 17 is formed on the entire surface of the interlayer insulating film 15 including the surface of the lower layer electrode 12F in the anti-fuse connecting hole 16F. It A silicon nitride film is used for the anti-fuse insulating film 10 as in the second embodiment.

In the fifth step, as shown in FIG. 16, an upper electrode 18 of the antifuse element is formed on the surface of the antifuse insulating film 17. Example 2 described above
Similarly to the above, when the upper layer electrode 18 is formed, the unnecessary upper layer electrode 18 and the anti-fuse insulating film 17 other than the formation region of the anti-fuse element are removed. A for the upper electrode 18
A composite film of the 1-alloy film 18A and the TiN film 18B is used. Then, when the process of forming the upper electrode 18 is completed, the anti-fuse element F is completed.

In the sixth step, the wiring 19 is formed on the interlayer insulating film 15 as shown in FIG. Complementary MI
In the SFET formation region, the wiring 19 is the wiring connection hole 16
It is electrically connected to the wiring 12 through T. The wiring 19 is electrically connected to the upper electrode 18 of the antifuse element F in the antifuse element formation region. Similar to the above-described second embodiment, the wiring 19 includes the TiN film 19A and the Al film 19
B and a TiN film 19C are sequentially laminated to form a composite film.

In the seventh step, although not shown, a final passivation film is formed on the entire surface of the substrate. When these series of steps are completed, the semiconductor integrated circuit device having the anti-fuse element F is completed.

In the eighth step, programming or data writing is performed on any antifuse element F.

As described above, in the method of manufacturing the semiconductor integrated circuit device having the anti-fuse element F according to this embodiment, the same effects as those obtained in the second embodiment can be obtained.

The present invention is not limited to the above-mentioned embodiment, and various modifications can be made without departing from the scope of the invention.

For example, the present invention can be applied to a wiring forming technique such as a printed wiring board having an antifuse structure.

[0080]

According to the present invention, the number of manufacturing steps can be reduced in a semiconductor integrated circuit device having an antifuse element.

[Brief description of drawings]

FIG. 1 is a first diagram illustrating a method for manufacturing a semiconductor integrated circuit device having an anti-fuse element according to a first embodiment of the present invention.
It is sectional drawing in a process.

FIG. 2 is a sectional view in a second step.

FIG. 3 is a sectional view in a third step.

FIG. 4 is a sectional view in a fourth step.

FIG. 5 is a sectional view in a fifth step.

FIG. 6 is a sectional view in a sixth step.

FIG. 7 is a sectional view in a seventh step.

FIG. 8 is a first diagram illustrating a method of manufacturing a semiconductor integrated circuit device having an antifuse element according to a second embodiment of the present invention.
It is sectional drawing in a process.

FIG. 9 is a sectional view in a second step.

FIG. 10 is a sectional view in a third step.

FIG. 11 is a sectional view in a fourth step.

FIG. 12 is a sectional view in a fifth step.

FIG. 13 is a sectional view in a first step illustrating a method for manufacturing a semiconductor integrated circuit device having an anti-fuse element according to the third embodiment of the present invention.

FIG. 14 is a sectional view in a second step.

FIG. 15 is a sectional view in a third step.

FIG. 16 is a sectional view in a fourth step.

FIG. 17 is a sectional view in a fifth step.

[Explanation of symbols]

1 semiconductor substrate, 7 source region, drain region or lower layer electrode, 8 and 15 interlayer insulating film, 10 and 17 anti-fuse insulating film, 11 and 18 upper layer electrode and 12, 19
Wiring, 9C, 16T wiring connection hole, 9F, 16F antifuse connection hole, 14 conduction path.

Claims (6)

[Claims] 1. A step of forming a plurality of first wirings and a plurality of lower layer electrodes of an anti-fuse element on a substrate; a step of forming an interlayer insulating film covering the first wirings and the lower layer electrodes; Forming a wiring connecting hole in the interlayer insulating film on the wiring and simultaneously forming an anti-fuse connecting hole in the interlayer insulating film on the lower layer electrode; and at least forming an anti-fuse connecting hole on the lower layer electrode in the anti-fuse connecting hole. A step of forming a fuse insulating film; and a step of passing the wiring connection hole on the interlayer insulating film.
A second wiring electrically connected to the wiring and a step of forming an upper layer electrode of an antifuse element connected to the lower layer electrode through the antifuse insulating film through the antifuse connection hole, Manufacturing of a semiconductor integrated circuit device, characterized in that an anti-fuse insulating film of any of the plurality of anti-fuse elements is destroyed to form a conductive path electrically connecting the lower layer electrode and the upper layer electrode. Method. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the step of forming the first wiring and the lower layer electrode of the anti-fuse element is the same step in which the first wiring layer is firstly formed. A method of manufacturing a semiconductor integrated circuit device, which is a step of simultaneously forming a wiring and a lower layer electrode. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the step of forming the second wiring and the upper layer electrode of the anti-fuse element is the same step of the second wiring. A method of manufacturing a semiconductor integrated circuit device, comprising the step of simultaneously forming a second wiring and an upper layer electrode on a layer. 4. A step of forming a plurality of first wirings and a plurality of lower layer electrodes of an anti-fuse element on a substrate; a step of forming an interlayer insulating film covering the first wirings and the lower layer electrodes; A step of forming a wiring connection hole in the interlayer insulating film on the wiring and simultaneously forming an antifuse connection hole in the interlayer insulating film on the lower layer electrode; and the step of forming an antifuse connection hole on the lower layer electrode in the antifuse connection hole. A step of forming an antifuse insulating film on the entire surface of the interlayer insulating film, and a step of forming an antifuse element which is connected to the lower layer electrode through the antifuse insulating film in the formation region of the antifuse element via the antifuse insulating film. Forming an upper layer electrode and removing at least the anti-fuse insulating film on the first wiring in the wiring connection hole in the same step; Wherein through the wiring connection hole on the first
Forming a second wiring electrically connected to the wiring;
A semiconductor integrated circuit, wherein an antifuse insulating film of any of the plurality of antifuse elements is destroyed to form a conductive path electrically connecting the lower layer electrode and the upper layer electrode. Device manufacturing method. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein the step of forming the first wiring and the lower electrode of the anti-fuse element has a metal silicide film as an uppermost layer. Forming a first wiring and a lower layer electrode, and forming an upper layer electrode of the antifuse element and removing at least the antifuse insulating film on the first wiring in the wiring connection hole in the same step. Is a step of forming an upper electrode of the antifuse element and removing at least the antifuse insulating film on the first wiring in the wiring connection hole and the uppermost metal silicide film of the first wiring in the same step. A method for manufacturing a semiconductor integrated circuit device, characterized by: 6. A step of forming a plurality of first wirings each having a metal silicide film as an uppermost layer and a plurality of lower layer electrodes of an anti-fuse element on a substrate, and an interlayer insulation covering the first wirings and the lower layer electrodes. A step of forming a film, and etching the interlayer insulating film on the first wiring until the uppermost metal silicide film of the first wiring is removed to form a wiring connection hole, and at the same time, on the lower electrode. Etching the interlayer insulating film under the same condition to form an antifuse connection hole having an opening size smaller than that of the wiring connection hole without removing the uppermost metal silicide film of the lower electrode. And a step of forming an antifuse insulating film on at least the lower electrode in the antifuse connecting hole, and forming the wiring connecting hole on the interlayer insulating film. It said in the first
A second wiring electrically connected to the wiring and a step of forming an upper layer electrode of an antifuse element connected to the lower layer electrode through the antifuse insulating film through the antifuse connection hole, Manufacturing of a semiconductor integrated circuit device, characterized in that an anti-fuse insulating film of any of the plurality of anti-fuse elements is destroyed to form a conductive path electrically connecting the lower layer electrode and the upper layer electrode. Method.