JP2008112988A5 - - Google Patents
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- JP2008112988A5 JP2008112988A5 JP2007260681A JP2007260681A JP2008112988A5 JP 2008112988 A5 JP2008112988 A5 JP 2008112988A5 JP 2007260681 A JP2007260681 A JP 2007260681A JP 2007260681 A JP2007260681 A JP 2007260681A JP 2008112988 A5 JP2008112988 A5 JP 2008112988A5
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- electrode
- semiconductor device
- insulating film
- thin film
- semiconductor layer
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Claims (18)
前記メモリ素子は、シリコンと反応してシリサイド形成する第1の電極と、前記第1の電極上にシリコン膜と、前記シリコン膜上にシリコンと反応してシリサイド形成する第2の電極と、を有し、
前記薄膜トランジスタのゲート電極は、前記メモリ素子の前記第1の電極と同じ材料であり、前記薄膜トランジスタのソース電極またはドレイン電極は、前記メモリ素子の前記第2の電極と同じ材料であることを特徴とする半導体装置。 A driver circuit including a plurality of thin film transistors over a substrate having an insulating surface, and a plurality of memory elements;
The memory element includes: a first electrode that forms silicide by reacting with silicon; a silicon film on the first electrode; and a second electrode that forms silicide by reacting with silicon on the silicon film. Have
The gate electrode of the thin film transistor is the same material as the first electrode of the memory device, the source electrode or the drain electrode of the thin film transistor, and characterized in that the same material as the second electrode of the memory device semiconductor device.
前記メモリ素子は、シリコンと反応してシリサイド形成する第1の電極と、前記第1の電極上にシリコン膜と、前記シリコン膜上にシリコンと反応してシリサイド形成する第2の電極と、を有し、
前記薄膜トランジスタのゲート電極は、前記メモリ素子の前記第1の電極と同じ材料であり、
前記アンテナの下方に接続電極を有し、前記アンテナは、前記接続電極と電気的に接続し、
前記接続電極は前記薄膜トランジスタと電気的に接続し、
前記接続電極は、前記薄膜トランジスタのソース電極及びドレイン電極と同じ材料であり、且つ、前記メモリ素子の前記第2の電極と同じ材料であることを特徴とする半導体装置。 A driver circuit including a plurality of thin film transistors over a substrate having an insulating surface, a plurality of memory elements, and an antenna;
The memory element includes: a first electrode that forms silicide by reacting with silicon; a silicon film on the first electrode; and a second electrode that forms silicide by reacting with silicon on the silicon film. Have
The gate electrode of the thin film transistor is the same material as the first electrode of the memory element,
Having a connection electrode below the antenna, the antenna is electrically connected to the connection electrode;
The connection electrode is electrically connected to the thin film transistor;
The connection electrode is the same material as a source electrode and a drain electrode of the thin film transistor, and a semiconductor device which is a same material as the second electrode of the memory element.
絶縁表面を有する基板上に薄膜トランジスタを有し、
前記薄膜トランジスタは、前記基板上に形成された島状の半導体と、前記基板上に形成された絶縁膜と、前記絶縁膜の一部は、前記半導体上に形成されたゲート絶縁体であり、
前記半導体上に前記ゲート絶縁体を介して形成されたゲート電極とを有し、
前記基板上に第1の電極と、前記基板上に形成された少なくとも前記薄膜トランジスタ及び前記第1の電極を覆う層間絶縁膜と、前記層間絶縁膜は、前記薄膜トランジスタのソース領域またはドレイン領域上に第1の開口と、前記第1の電極上に第2の開口とを有し、
前記第1の電極上の前記第2の開口に形成された半導体層と、前記層間絶縁膜上に前記第1の開口を介して前記薄膜トランジスタの前記ソース領域または前記ドレイン領域と電気的に接続する第2の電極と、前記層間絶縁膜上に形成された第3の電極と、前記第3の電極は、前記半導体層が前記第1の電極と前記第3の電極の間に挟まれるように前記第2の開口に形成され、
前記メモリ素子は、前記第1の電極と前記第3の電極と、前記第1の電極と前記第2の電極の間に挟まれた前記半導体層を有し、前記第3の電極と前記第2の電極は同じ材料で形成され、
前記第1の電極は、前記ゲート電極と同じ材料であることを特徴とする半導体装置。 A semiconductor device including a memory element;
A thin film transistor over a substrate having an insulating surface;
The thin film transistor is an island-shaped semiconductor formed on the substrate, an insulating film formed on the substrate, a part of the insulating film is a gate insulator formed on the semiconductor,
A gate electrode formed on the semiconductor via the gate insulator;
A first electrode on the substrate, an interlayer insulating film covering at least the thin film transistor and the first electrode formed on the substrate, and the interlayer insulating film are formed on a source region or a drain region of the thin film transistor. 1 opening and a second opening on the first electrode,
Said second semiconductor layer formed in the opening on the first electrode, is connected via the first opening on the interlayer insulating film and the source region or the drain region electrically to the thin film transistor The second electrode, the third electrode formed on the interlayer insulating film, and the third electrode are arranged such that the semiconductor layer is sandwiched between the first electrode and the third electrode. Formed in the second opening;
The memory element includes the first electrode, the third electrode, and the semiconductor layer sandwiched between the first electrode and the second electrode, and the third electrode and the third electrode The two electrodes are made of the same material,
The first electrode, wherein a is the same material as the gate electrode.
絶縁表面を有する基板上に第1の半導体層を形成し、
前記第1の半導体層上に第1の絶縁膜を形成し、
前記第1の絶縁膜上に前記第1の半導体層と重なる第1の電極と、前記第1の絶縁膜上に第2の電極とを形成し、
前記第1の電極及び前記第2の電極を覆う第2の絶縁膜を形成し、
前記第2の絶縁膜をエッチングして前記第2の電極に達する第1の開口を形成し、
前記第1の開口を覆う第2の半導体層を形成し、
前記第2の絶縁膜をエッチングして前記第1の半導体層に達する第2の開口を形成し、
前記第2の絶縁膜上に前記第1の開口と重なる第3の電極と、前記第2の開口と重なる第4の電極とを形成し、
前記メモリ素子は、前記第2の電極と、前記第2の半導体層と、前記第3の電極とを有し、
前記薄膜トランジスタは、前記第1の半導体層と、前記第1の電極と、前記第4の電極とを有することを特徴とする半導体装置の作製方法。 A method for manufacturing a semiconductor device having a driving circuit including a plurality of thin film transistors over a same substrate and a plurality of memory elements,
Forming a first semiconductor layer over a substrate having an insulating surface;
Forming a first insulating film on the first semiconductor layer;
Forming a first electrode overlying the first semiconductor layer on the first insulating film, and a second electrode over the first insulating film;
Forming a second insulating film covering the first electrode and the second electrode;
Etching the second insulating film to form a first opening reaching the second electrode;
Forming a second semiconductor layer covering the first opening;
Etching the second insulating film to form a second opening reaching the first semiconductor layer;
Forming a third electrode overlapping the first opening and a fourth electrode overlapping the second opening on the second insulating film;
The memory element includes the second electrode, the second semiconductor layer, and the third electrode.
The thin film transistor, wherein the first semiconductor layer, wherein a first electrode, a method for manufacturing a semiconductor device, characterized by chromatic and said fourth electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007260681A JP5296360B2 (en) | 2006-10-04 | 2007-10-04 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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JP2006273394 | 2006-10-04 | ||
JP2006273394 | 2006-10-04 | ||
JP2007260681A JP5296360B2 (en) | 2006-10-04 | 2007-10-04 | Semiconductor device and manufacturing method thereof |
Publications (3)
Publication Number | Publication Date |
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JP2008112988A JP2008112988A (en) | 2008-05-15 |
JP2008112988A5 true JP2008112988A5 (en) | 2010-11-11 |
JP5296360B2 JP5296360B2 (en) | 2013-09-25 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2007260681A Expired - Fee Related JP5296360B2 (en) | 2006-10-04 | 2007-10-04 | Semiconductor device and manufacturing method thereof |
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JP (1) | JP5296360B2 (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5415713B2 (en) * | 2008-05-23 | 2014-02-12 | 株式会社半導体エネルギー研究所 | Semiconductor device |
US8044499B2 (en) | 2008-06-10 | 2011-10-25 | Semiconductor Energy Laboratory Co., Ltd. | Wiring substrate, manufacturing method thereof, semiconductor device, and manufacturing method thereof |
JP5473413B2 (en) | 2008-06-20 | 2014-04-16 | 株式会社半導体エネルギー研究所 | Wiring substrate manufacturing method, antenna manufacturing method, and semiconductor device manufacturing method |
JP2010041045A (en) | 2008-07-09 | 2010-02-18 | Semiconductor Energy Lab Co Ltd | Semiconductor device and method for producing the same |
WO2010032599A1 (en) | 2008-09-19 | 2010-03-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
JP5583951B2 (en) | 2008-11-11 | 2014-09-03 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
JP5470054B2 (en) | 2009-01-22 | 2014-04-16 | 株式会社半導体エネルギー研究所 | Semiconductor device |
JP7088133B2 (en) | 2019-07-12 | 2022-06-21 | 味の素株式会社 | Manufacturing method of printed wiring board and resin sheet with inorganic layer |
Family Cites Families (4)
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JP3559580B2 (en) * | 1993-12-17 | 2004-09-02 | 財団法人国際科学振興財団 | Semiconductor device |
JP3501416B2 (en) * | 1994-04-28 | 2004-03-02 | 忠弘 大見 | Semiconductor device |
JPH08316324A (en) * | 1995-05-16 | 1996-11-29 | Kawasaki Steel Corp | Method of manufacturing semiconductor integrated circuit device |
JP4912641B2 (en) * | 2004-08-23 | 2012-04-11 | 株式会社半導体エネルギー研究所 | Manufacturing method of wireless chip |
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2007
- 2007-10-04 JP JP2007260681A patent/JP5296360B2/en not_active Expired - Fee Related
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