CN102160175B - 采用超材料的阻抗受控制的电性内连线 - Google Patents

采用超材料的阻抗受控制的电性内连线 Download PDF

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CN102160175B
CN102160175B CN2008801312380A CN200880131238A CN102160175B CN 102160175 B CN102160175 B CN 102160175B CN 2008801312380 A CN2008801312380 A CN 2008801312380A CN 200880131238 A CN200880131238 A CN 200880131238A CN 102160175 B CN102160175 B CN 102160175B
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connection line
internal connection
electric internal
connection
electric
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CN102160175A (zh
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克里斯多夫·威兰德
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了一种改善二个电性元件(510，550)之间的电性内连线的方法，其是借由提供与电性内连线(530)相结合的一超材料覆盖物(700)来实现。该超材料覆盖物被设计为使得电性信号经由电性内连线传播时表现得如同其内形成有电性内连线的介电介质的介电系数与导磁系数与电性内连线周围的介电介质的实部的介电系数与导磁系数不同。在某些情况下，该超材料所造成的介电系数与导磁系数会使信号犹如在介电系数与导磁系数为负值之下传播。因此，本方法提供的电性内连线能够强化阻抗控制与稳定度，减少噪声，并减小损耗。该超材料覆盖物的可替换的实施例则强化了传统的分离的焊线接合，同时促进了与带状实现相兼容的单一集成设计。

Description

采用超材料的阻抗受控制的电性内连线
技术领域
本发明大致涉及电子器件的制造与封装，尤其涉及阻抗受控制的电性焊线内连线的设计。
背景技术
集成电路通常包括用来密封一电子电路或多个电子电路的塑料或陶瓷封装，每一电子电路均形成在半导体基板上。通常是借由焊线接合(wirebonding)、倒装芯片(flip chip)焊接(soldering)、或卷带式自动接合(tapeautomated bonding；TAB)来提供电子电路之间的电性内连线与封装的外部连线。随着电子电路的复杂度与功能的增加，这些电性内连线通常需要横跨半导体芯片的表面并位于半导体芯片的周边区。此外，在多芯片模块(multi-chip module；MCM)(其中多个电子电路被一起封装)中的电子电路之间的电性内连线需要的是类似于在整个封装的占用面积(footprint)内实现的电性内连线，而不是在周边区实现的电性内连线。
考虑至集成电路的任何部分的电性内连线容易实现并且低频功能良好的焊线接合。这种焊线的形状(圆形或平的)、宽度(通常为15μm至200μm)、与长度(通常为100μm至1000μm)是可改变的。这些焊线对在其内传播的信号表现为高特征阻抗传输线段(transmission line segment)。然而，由于电感、电容、与电阻的寄生现象(parasitics)再加上由制造过程与设备所引起的变化，随着数据速率(data rate)与信号频率的提高，这些焊线接合的电性内连线问题增多。随着信号频率的提高，该寄生现象会表现为焊线的过度或可变阻抗。由于从封装电性迹线(trace)或电子电路的阻抗受控制的环境到焊线的反射，这种阻抗不匹配(impedance mismatch)会导致传播中的信号产生显著衰减。这种反射信号也会导致电子电路内的性能下降，并导致信号波形扭曲以及噪声增多。
通常，现有技术的解决方案是借由设计器件减少焊线长度来减少焊线电感，以控制或减少寄生效应。其中将焊线连线设在器件边缘是可取的，这样可实现较短的焊线长度并具有实用性。然而，有的器件应用中，焊线需要设在器件内部。令人惊讶的是，尽管全世界有非常多的电子电路、封装形式、半导体芯片技术、业务需求、与制造商，对于提供高性能的连接至电子电路的电性内连线的问题的公知解决方案却相对有限，并在电子电路与封装的设计或是其再现性与产能上遭遇到重大的障碍，特别是对于具有大量电性内连线的器件。现今的封装包括从单一晶体管封装(例如可自NXP Semiconductors取得的4管脚的SOT(封装标识号为SOT343F))到多芯片封装(multiple chip packages；MCP)(例如可自Renesas Technology取得的2116管脚的高密度BGA(封装标识号为PRBG2116FA-A))。因此，一个电性内连线或所有的电性内连线都需要阻抗控制。
同样地，对于受控制、可再现的电性内连线的需求存在于大范围的封装形式、管脚数目、与信号频率的现今电子电路中。这种器件的例子包括：NXP Semiconductors的BFG424F NPN型宽带晶体管，其以模拟输入和输出端口运行，可达25GHz，是4管脚的SOT封装；模拟器件(AnalogDevices)的AD6534Othello-G单芯片直接变频(direct conversion)GSM/GPRS接收器，其封装在32引脚的超低四方形式的引脚架构芯片级封装(LFCSP-VQ)中，具有以标准移动电话频率800MHz/900MHz/1800MHz/1900MHz运行的双模拟输入端口以及提供64kb/s的数字音频(digital audio)的数字输出端口；以及
Figure BPA00001331527200021
4超级处理器(Extremeprocessor)，其在0.13μm的硅上实现，内核以3.5GHz运行，封装在具有以1066MHZ运行的64比特数字数据总线的775管脚LAND封装中。
对于焊线问题的一般的解决方案是借由倒装芯片的概念或球栅阵列(ballgrid array；BGA)封装来减小转接(transition)尺寸，其中半导体电路的接触点是直接接合于邻近的电路或基板。另一个已知的解决方案是以高介电常数材料(例如含陶瓷的环氧树脂)来填充转接区。虽然这些解决方案是有效的，但无法应用于所有的情况。例如，转接中的高频信号可能只涉及到转接中少数的内连线的情况，这些解决方案的效率就不高。因此，当只有少数的转接内连线需要针对高频寄生效应作特殊处理、或是半导体电路中的材料禁不起来自上述倒装芯片与球栅阵列解决方案中进行焊球回焊操作的温度时，现存的解决方案会变得昂贵且效率差。
减少或控制焊线架构中的寄生效应的技术包括提供多个平行层的焊线，例如Grellman等人(美国专利4,686,492)所提出的，这样，借由上述平行焊线的电容电抗(capacitive reactance)来补偿焊线的电感电抗(inductivereactance)。然而，此技术需要焊线每一端的焊盘要可以支持三、四或更多道的焊线接合，从而造成焊盘非常大并增加了半导体芯片的占用面积与成本。同样地，提供这种长距离平行层，半导体芯片的占用面积达25平方毫米或更大，会造成内连线脆弱而无法禁得起电子封装所需要的环境需求。最后，Grellman等人所描述的具有四层焊线架构的2116管脚的封装需要设置8464根焊线，并需要16928个独立的落到封装和半导体芯片的焊线接合工具的接合着陆区(landings)，造成了产量降低、制造时间增加以及成本增加。
由Kwark等人(美国专利申请2005/0,116,013)所提出的一替代技术是在主要的焊线接合下方，使用一较宽且平的接合(一般称为带状接合(ribbonbonding))提供一第二接合。所形成的电性连接提供一微带(microstrip)结构。如同Grellman等人那样，此方法的缺点在于：需要增加芯片的占用面积，通常在用于高速内连线的尺寸敏感区；需要在以微带结构为特征的每个焊盘的邻接处提供额外的接地焊盘；以及使机械性接合操作的数量加倍。
由Kwark与Grellman所教示的每个解决方案是解决单独地控制每个焊线的阻抗的问题。相反地，Wyland(美国专利7,217,997)是教示在焊线接合的上方提供一宽的电性平面，并在二者之间具有一介电间隔物，以防止信号焊线接合与宽的电性平面之间电性短路。如Wyland所教示的，借由提供距离焊线接合约32μm的宽的电性平面，焊线的阻抗能够从分离焊线的约125Ω减少到模拟信号输入/输出的典型的50Ω。Wyland所教示的方法的优点是提供了一单一结构，也就是宽的电性平面，可同时管理多个焊线接合。
然而，Wyland教示焊线接合上方的宽的电性平面可将阻抗减低至50Ω，但未明显地降低，这是因为32μm已经是小间距，会导致此间距内的小变异或误差而造成的阻抗的紧密公差与实质变异。另外，此类阻抗受控制的结构的提供最适于焊线仅连接于半导体电路的周边区并且直接接合于封装的电性迹线(trace)的设计。而且很明显地，此结构不允许半导体电路设计者自由地将不同阻抗的焊线紧密地放在一起，例如可能需要提供不同阻抗(例如50Ω与75Ω)的多个输出；或是将非常低阻抗的电子电路的内连线(例如一多芯片模块(MCM)中数欧姆的放大器增益阶(gain stage))非常靠近一50Ω的输出端口。
因此，提供一种与焊线在半导体芯片或封装内的位置无关的焊线阻抗控制的提供方法是有利的。若该方法容许单独建立不同焊线的阻抗并同时允许在制造与组装的过程中提供一单一附加元件，则更加有利。如果该附加元件可以与一电性信号内连线集成而提供作为一单片构件的焊线，以减少半导体电路、多芯片模块(MCM)等的封装工艺的复杂度，则可获得额外的益处。另外，允许预先制造所需的结构并包括出现在完成的器件例如封胶体的附加的介电材料的效果的方法，会具有优点。
发明内容
根据本发明，提供一种方法，提供多个电性内连线的至少一电性内连线至一第一器件，每一电性内连线以至少一内连线长度为特征。此方法还包括提供一覆盖物，所述覆盖物包括至少一第一超材料结构，并对于所述内连线长度的至少一既定部分被设置为大致平行于多个电性内连线的所述至少一电性内连线。
根据本发明的另一实施例，提供一种电路，包括：至一第一器件的多个电性内连线的至少一电性内连线，每一电性内连线以至少一内连线长度为特征。此电路还包括一覆盖物，所述覆盖物包括至少一第一超材料结构，并对于所述内连线长度的至少一既定部分被设置为大致平行于多个电性内连线的所述至少一电性内连线。
根据本发明的另一实施例，提供一种计算机可读介质，其内储存按照一既定的运算装置格式的数据，且借由适当的运算装置执行所述数据来提供一电性内连接一电路的方法。所述方法包括：提供多个电性内连线的至少一电性内连线至一第一器件，每一电性内连线以至少一内连线长度为特征；以及提供一覆盖物，所述覆盖物包括至少一第一超材料结构，并对于所述内连线长度的至少一既定部分被设置为大致平行于多个电性内连线的所述至少一电性内连线。
根据本发明的另一实施例，提供一种计算机可读介质，其内储存按照一既定的运算装置格式的数据，且借由适当的运算装置执行所述数据来提供一电性内连接一电路的电路，所述电路包括：至一第一器件的多个电性内连线的至少一电性内连线，每一电性内连线以至少一内连线长度为特征；以及一覆盖物，所述覆盖物包括至少一第一超材料结构并对于所述内连线长度的至少一既定部分被设置为大致平行于多个电性内连线的所述至少一电性内连线。
附图说明
以下会将本发明示例的实施例结合下列的图来作说明，其中：
图1是示出一般现有技术中使用传统焊线接合的二个电子元件之间的电性内连线。
图2是示出根据Grellman等人所提出的现有技术中控制焊线接合阻抗的层积焊线接合方法。
图3是示出根据Kwark等人所提出的现有技术中用以形成微带转接的共分配(co-dispensed)接地平面的方法。
图4是示出根据Wyland所提出的现有技术中接地拱(ground arch)的方法。
图5是示出用以对一焊线接合阵列提供一超材料(meta-material)覆盖物(overlay)的本发明的一示例实施例。
图6是示出根据图5的超材料覆盖物结构的一示例实施例。
图7A是示出根据图5与图6的超材料覆盖物的一示例的剖面图。
图7B是示出超材料覆盖物的另一示例实施例。
图8是示出根据本发明的一实施例的一示例的六层超材料覆盖物，其相对于图6与图7所示的一焊线接合阵列设置。
图9是示出一示例的电性内连线，其使用集成了六层超材料结构与焊线接合的二个七层超材料覆盖物，以提供一单一内连线元件。
图10是示出从图9的示例的七层超材料覆盖物至一半导体电路或封装的示例的电性内连线。
图11是示出根据本发明的一实施例的一示例的十三层超材料覆盖物，其中电性信号内连线是夹设于二个六层超材料结构之间。
图12是示出关于一封装内的一半导体电路的一超材料覆盖物的三个示例的布局。
图13是示出与现有技术的解决方案比较的根据本发明的一实施例的具有超材料覆盖物的一焊线的传输特性。
具体实施方式
示出于图1的是一般现有技术中使用传统焊线接合150的二个电子元件110与120之间的电性内连线100。如图所示，第一电子元件110具有置于其表面上、接近于其物理周边区的多个第一焊盘130。类似地，第二电子元件120具有置于其表面上、接近于其物理周边区的多个第二焊盘140。传统焊线接合150被制造于每个第一焊盘130与第二焊盘140之间。焊线接合150的形成通常是以直径15μm至50μm的金线、铝线、或铜线并使用热超声波接合(thermosonic bonding)、球形接合(ball bonding)或楔形接合(wedge bonding)而成。第一焊盘130与第二焊盘140之间的一般的分离间隔L160为100μm至250μm。
根据Grellman等人所提出的一现有技术的用于控制焊线接合阻抗的层积焊线接合方法如图2中的层积内连线200所示。如图所示，具有第一焊盘240的第一器件210电性内连接于具有第二焊线接合230的第二器件220。每个电性内连线是从一个第一焊盘240至一个第二焊盘230的平行的层叠焊线接合堆叠250。平行的层叠焊线接合堆叠250包括具有可类比于图1中的焊线接合150的第一接合201、第二接合202、第三接合203、与第四接合204。第二～第四接合202～204中的每一个均分别设置，使得这些焊线接合分别平行于第一接合201，垂直位于其上方并具有间隔。平行的层叠焊线接合堆叠250中的每个后续的焊线提供有限的电容值来补偿第一接合201的电感。如同前面描述的那样，Grellman等人的方法增加了包括第一与第二器件210、220的电子电路的制造复杂度与成本，因为每一电性内连线均需要多个焊线接合操作，多焊脚导致占用面积增加，尤其是在楔形焊接时。
现在请参考图3，其示出的是根据Kwark等人所提出的现有技术的方法中用以形成一微带转接370的共分配接地平面内连线300。所示的是具有第一焊盘340与第一带状垫345的第一器件310，其紧密地接近于具有第二焊盘330与第二带状垫335的第二器件320。每一个微带转接包括第一焊盘340与第二焊盘330之间的焊线接合350，并带有第一带状垫345与第二带状垫335之间的带状接合360。虽然可获得的标准的带状物可达宽1000μm及厚100μm(请见例如美国宾夕法尼亚州(Pennsylvania)华盛顿堡(FortWashington)的Kulicke and Soffa Industries所制造的接合带状物(BondingRibbon))，然而用于形成带状接合360的带状物的一般尺寸是宽20μm至100μm及厚6μm至20μm。如同前述Grellman等人的方法那样，Kwark等人的方法对于每个所需的焊线350需要多个接合，并需要增加占用面积来容纳每个焊线焊垫与带状焊垫。带状焊垫335与345明显地宽于焊盘330与340，这会限制焊盘间距L380的缩减。在实现阻抗受控制的焊线内连线方面，相对于Grellman的方法，这种限制增加了Kwark的方法的缺点。
如上分别示于图2与图3的Kwark与Grellman的方法中每个焊线对于多个接合的需求借由根据Wyland所提出的接地拱结构400而得以改善。所示的是封装的基底405，为了清楚起见未示出其余的部分，其上已设置了半导体芯片410，半导体芯片410的表面上设置有器件焊盘420。封装迹线(trace)440与接地平面连线450也是置于基底405的表面上。与前述的其他现有技术相同的是，借由在每个器件焊盘420与封装迹线440之间的焊线接合430来将半导体芯片420电性内连接于封装。
然而，目前在焊线接合430的上方设置接地拱470为焊线430的电感阻抗(inductive impedance)提供一电容式修正(capacitive correction)。介电质480已置于接地拱470的下内表面上，以避免如果发生接地拱470变形或焊线接合430的脱落时接地拱470与焊线接合430短路。接地拱470是借由导电环氧树脂460而电性连接于接地平面连线450。如前所述，为了对焊线接合提供50Ω的阻抗而不是没有接地拱470的情况下的120Ω，焊线接合430与接地拱470之间的分离间隔L490是32μm。如前所述，接地拱470并未提供同时实现多个焊线阻抗的灵活性，不会在半导体芯片410的占用面积内支持多个焊盘位置，除非以距离半导体芯片410的周边区的固定距离以固定的间隔排成一行；并且不支持非常低的阻抗，例如，这种非常低的阻抗在内连接多个高频半导体器件时需要用到(例如微波MCM内的低噪声GaAs、InP或SiGe放大器)。
如图5所示，本发明的一示例实施例提供针对现有技术的缺点与限制的解决方案：超材料覆盖物560覆盖于焊线接合530的阵列。与图1类似，图中所示的第一器件510具有多个第一焊盘520，同样地第二器件550具有多个第二焊盘540。每个第一焊盘520经由焊线接合530而电性连接于第二焊盘540的其中之一。覆盖焊线接合530的阵列的是超材料覆盖物560，其提供焊线接合530环境的适当修正与控制，以使焊线接合530的阻抗符合预期的目标值。超材料覆盖物560是多个这样的材料之一，即，被设计用来使信号表现得像是使信号的波形如同介电系数与导磁系数(permittivity and permeability)不同于所使用的绝缘体的实部介电系数与导磁系数的材料。应注意，相对介电系数与相对导磁系数包括实部与虚部，即εR＝εR+jεR与μR＝μR+jμR。可以设计超材料，以使信号的响应犹如介电系数与导磁系数具有负值。在示例的实施例中的超材料，例如超材料覆盖物560，是将导体排列在绝缘体中，而减少信号上的线的共振响应(resonant response)。这些超材料设计，可选择性地以其他超材料设计来替代。
虽然目前阻抗匹配方法依赖于正阻抗，但也可使用负阻抗来实行阻抗匹配。在美国物理学会(American Physical Society)的Physical Review B 70，113102(2004)，A.F.Starr等人所撰写的标题为“负折射率复合超材料的制造与特性”(Fabrication and Characterization of a Negative-Refractive-IndexComposite Meta-Material)的文章中提到：“虽然对于有效折射率是负值的材料的设计并无许多建议的路径，然而严谨的方法是去设计介电系数(ε)与导磁系数(μ)同时是负值的材料。虽然无已知的自然产生的材料或化合物表现出同时是负值的ε与μ，但是可设计出这样的材料所提供的有效ε与μ，其从有效的介质参数(effective medium arguments)推导出在一有限的频带(frequency band)的有效ε与μ是有一个是负值或二者都是负值”(“While there are no known naturally occurring materials or compounds thatexhibit simultaneously negative εandμ，such materials can be designed toprovide effective εandμ，as derived from effective medium arguments，whichare singly or both negative over a finite frequency band.”)。
与前述图4中的Wyland的方法不同，在超材料覆盖物560中，焊线接合530的介电系数与导磁系数是在负方向受到影响，如果需要可允许焊线接合530的阻抗实质上低于50Ω，而与接地拱结构400的接地拱470相比，增加了焊线接合530与超材料覆盖物560之间的间隔的裕度(tolerance)；且允许将超材料覆盖物560用在任何位置的需要的第一与第二焊盘520与540之间的焊线接合530，而与其在半导体芯片或封装中的位置无关。
请参考图6，所示的是适于提供图5的超材料覆盖物560的第一示例的超材料结构600。基板610被配置为超材料。位于基板610内的是排列成同心的“方形环”625(在后文称为类长方形)的导电材料635的图形(例如为一单位花样(motif))。这些形状包括但不限于长方形与正方形。金属630的直线段的图形与超材料导体平面615也位于基板610中，如图所示是位于基板610的表面上。根据本发明的实施例，考虑到基板610及其内的超材料导体平面615在y方向的长度是14mm，且超材料的设计是借由控制阻抗而减少反射、强化电力转移与降低信号噪声，来强化信号传输线(transmission line)，例如图5的焊线接合530。类长方形635的总长度，是可比得上(且常可匹配于)超材料导体平面615的长度。超材料导体平面615的长度可选择性地为焊线接合530的长度的整除值(integer division)或是其四分之一。金属630的直线段与类长方形635的宽度相匹配。在本实施例中，开放式的类长方形635在本质上是正方形，并具有2.5mm的“直径”；导电材料635的每个部分的特征为具有0.1mm的导体宽度与25m的导体厚度。类长方形625中的间隔645与650是0.2mm。超材料导体平面615的厚度是25μm。在该超材料结构600内的金属通常是金、铜或铝，但可选择性地选自包括其他金属、金属合金与导电聚合物的一系列材料。在该超材料结构600中的绝缘体通常是高耐热的热固性树脂，例如双马来亚酰胺-三氮杂苯(bismaleimide triazine；BT)树脂，其为适用于电路板的玻璃型覆铜层压板(glass type copper clad laminates)所使用的树脂。
第一示例的超材料基板700的剖面图是示于图7A，是沿着图6的超材料基板600的AA-AA区段的剖面图。超材料基板600可由多层755所建构。层1(755L1)是接地平面730，其等效于图6的超材料导体平面615，厚度为25μm。置于接地平面730上的是层2(755L2)，其为厚度100μm的绝缘材料750。层3(755L3)是位于金属720的直线段实施于超材料基板700内的地方，且厚度也为25μm。层4(755L4)是另一个层厚为100μm的绝缘材料750。层5(755L5)包括形成图6的同心的类长方形625的金属导体725的排列，且具有25μm的厚度。
在层5(755L5)之上有厚度为100μm的绝缘材料750的另外的层6(755L6)。因此，对一示例的实施例而言，超材料是实现为在传统的接地平面730(755L1)与铜带的绝缘材料750中所加入的二个金属层755L3与755L5。
减小或增加工艺复杂度的替代的实施例可以选择性地实现，从而提供超材料基板700。其中一个替代的实施例是示于图7B的超材料基板700B，其在绝缘材料上具有信号导体平面790。在信号导体平面790的下方的一预定距离定义出具有同心的矩形的隔离金属结构760。与前述的实施例相反，该矩形是没有金属的区域。
图8是示出根据本发明实施例布局的示例的六层超材料基板700：超材料覆盖物以相对于根据图5的焊线接合阵列设置。因此，如图所示是具有多个第一焊盘520的第一器件510、以及同样地具有多个第二焊盘540的第二器件550。每个第一焊盘520经由焊线接合530而电性连接于第二焊盘540的其中之一。取代超材料覆盖物560，设置有六层超材料基板700，包括(依序列出)：绝缘材料750的层755L6、由金属导体725的排列所构成的层755L5、绝缘材料750的层755L4、包括金属720的直线段的层755L3、绝缘材料750的层755L2、与作为接地平面730的层755L1。
在前述的示例的实施例中，超材料覆盖物(例如超材料覆盖物700、600或560)是与焊线分离的。可替代地，超材料覆盖物也可实现为完整的电性内连线。这样的配置是示于图9，其中七层超材料覆盖物910与920是对阵列式的内连线提供阻抗受控制的电性内连线。因此，如图所示是具有多个第一焊盘520的第一器件510、以及具有多个第二焊盘540的第二器件550。内连接第一焊盘520与第二焊盘540的阵列的是第一七层超材料基板910，其最初由电性迹线层917组成，其中置于该层中的多个电性迹线取代前述的多个分离的焊线接合530。第一七层超材料基板910的其余的层是：第一绝缘层916、第一导体层915中的金属导体725、第二绝缘层914、第二导体层913中的金属720的直线段、第三绝缘层912、与信号导体平面911。第一七层超材料基板910具有长度L910，其足以分别覆盖多个第一与第二焊盘520与540。
图中也示出长度为L920的第二七层超材料920，其对第一焊盘520与第二焊盘540之间的单一电性内连线提供内连线。可选择地，第二七层超材料920的厚度、组成、以及关于第一七层超材料910的层911～916的布局可以变动。该第二设计可选择地为：借由只处理特定的内连线来减低材料的消耗；提供特定的带宽性能；或提供不同于第一七层超材料910的特定的阻抗特征、超材料覆盖物形状特征或内连线距离特征。
示例的七层超材料910与920需要将置于电性迹线层917内的电性迹线(该电性迹线取代分离的焊线530)分别连接于第一及第二焊盘520及540。类似地，信号导体平面911需要电性内连接于至少第一及第二器件510及550内设置的二个接地接触点的至少一个。提供从图9的示例的七层超材料覆盖物至半导体电路或封装的这些电性内连线的示例方法示于图10。示例的七层超材料内连线1000示于相关的剖面图1000A～1000C。
请参考第一剖面图1000A，其示出的七层超材料覆盖物910是覆盖在焊盘上(第一焊盘520或第二焊盘540)，其包括在基板1020上的金属化物1010。所示出的电性迹线层917与金属化物1010接触，这样的接触是借由包括导电黏着剂与焊料(solder)的标准技术来实现。第二剖面图1000B是显示七层超材料覆盖物910的信号导体平面911至基板1020上的金属化物1010的第一电性内连线。如图所示，从金属化物1010至七层超材料覆盖物910的直接连接是通孔(via)金属化物1030，其形成电性迹线层917的分离的部分。通孔金属化物1030是经由通孔(via)1040而电性连接于信号导体平面911，通孔1040穿过第一绝缘层916、第一导体层915、第二绝缘层914、第二导体层913、第三绝缘层912、与信号导体平面911。
通孔金属化物1030至金属化物1010的接触是借由例如前述的标准技术来实现。前述的通孔1040的形成与用以制造卷带式自动接合(tapeautomated bonding；TAB)中使用的卷带的变形的七层超材料覆盖物910的工业标准技术兼容。七层超材料覆盖物910的一替代的实施例是示于第三剖面图1000C，其移除了通孔金属化物1030，为信号导体平面911提供简化的内连线。如图所示，在本实施例中，七层超材料覆盖物910以类似于第一剖面图1000A中所示的方式，将电性迹线层917内连接于基板1020上的焊盘1010。信号导体平面911并非如同前述剖面图一样终止于接近焊盘1010之处，而是以自由区1050来延伸，自由区1050的形成是用来与信号平面焊盘1060内连接。此内连线是经由标准的技术来制造，例如前述用来提供电性迹线层917至焊盘1010的内连线的技术，但是可选择性地包括热压式的楔形接合或接合的其他变化形式。
前述示例实施例使用六层或七层超材料，后者是将电性迹线层并入层配置中，从而不需要分离的焊线。在某些情况下，电性信号对来自接近覆盖物的电性内连线的耦合所产生的噪声敏感，或是其上覆盖有覆盖物的电性内连线是对来自覆盖物电性迹线的耦合所产生的噪声敏感。另外，在某些情况下，用于实现覆盖物的公差或所需的阻抗的绝对值达到阈值，在该阈值处可以适当地实现可替代的覆盖物。在这些情况中，十三层超材料覆盖物1100(例如图11所示)提供额外的电性迹线的屏蔽、设计灵活度或较宽的公差。
如图所示，十三层超材料覆盖物1100包括下层的六层超材料结构1155A、电性迹线层1110、与上层的六层超材料结构1155B。下层的六层超材料结构1155A是由第一信号导体平面1155L1A、第一绝缘层1155L2A、第一导体层1155L3A中的金属720的直线段、第二绝缘层1155L4A、第二导体层1155L5A中的金属导体725、与第三绝缘层1155L6A所形成。
上层的六层超材料结构1155B是由第二信号导体平面1155L1B、第四绝缘层1155L2B、第三导体层1155L3B中的金属720的直线段、第五绝缘层1155L4B、第四导体层1155L5B中的金属导体725、与第六绝缘层1155L6B所形成。
在前述的示例实施例中，已示出了关于替代第一与第二器件的周边区之间的焊线接合的每个超材料覆盖物的布局方案，其中上述第一与第二器件包括但不限于半导体芯片、封装、与印刷电路板。可替代地，超材料覆盖物被配置为向封装、半导体芯片等的占用面积内的电性内连线提供覆盖物。封装内半导体电路的超材料覆盖物的这三个示例的实施例借由剖面图1200A～1200C而示于图12。
第一剖面图1200A描述的情况是：超材料覆盖物1210直接落在半导体芯片550的上表面上，其始于电路封装(为了描述清楚而未示出)的左上表面510A，终止于电路封装的右上表面510B。像这样该超材料覆盖物1210是形成二个拱形表面，其下方是焊线530。每个拱形表面1210A与1210B是在焊线530长度的基本部分(substantial portion)大致平行于各自的焊线530。虽然此示例的剖面图1200A描述形成二个拱形表面的超材料覆盖物1210，然而可替代的实施例可提供三个或更多的此类区域，以对跨越单一芯片或多芯片模块的焊线的接口(interface)提供所需的阻抗控制。另外，上述覆盖物可选择性地在根据设计需求来作布局之前成形，或是在置放与接合的过程中成形。而且，超材料覆盖物可选择性地被设计而不内连接至半导体芯片550的上表面，而是与其相隔一空气间隔(air gap)。
可替代的实施例提供数个拱形表面以根据位置来改变，使得对于内连线的一部分而言，具有单一的拱形表面，而对其他部分而言则有二个、三个或更多的拱形表面。而且，虽然所示的超材料覆盖物1210是六层超材料覆盖物(例如六层超材料覆盖物560)，替代物包括但不限于前述七层与十三层超材料覆盖物，例如七层超材料覆盖物910与十三层超材料覆盖物1100。
在第二剖面图1200B中，再次采用超材料覆盖物1220来进行半导体芯片550的上表面与电路封装(为了描述清楚而未示出)的左上及右上表面510A之间的焊线的阻抗控制。半导体芯片550的上表面包括着陆区1230，在其上的超材料覆盖物1220与半导体芯片550的上表面互连而不是直接界面接合(interfacing)到半导体芯片550的上表面。着陆区1230将超材料覆盖物1220垂直支撑在半导体芯片550上方，借此修改拱形表面1220A与1220B的形状。根据半导体芯片550的需求以及是否在着陆区1230中制作连接至超材料覆盖物的信号导体平面的电性内连线，按照标准半导体工艺由一系列介电材料与金属而形成着陆区1230。用于着陆区的典型材料包括二氧化硅、氮化硅、氧氮化硅、旋涂玻璃(spin-on-glass)、双苯基环丁烯(bisbenzocyclobutene)、金、与铝，可以选择性地分开采用这些材料中的每一个，或者可以结合使用。
现在请参考第三剖面图1200C，超材料覆盖物1240再次为左边的焊线接合540A提供覆盖物，该覆盖物始于电路封装的左上表面510A，跨越半导体芯片550的上方，终止于电路封装的右上表面510B，并为右边的焊线接合540B提供覆盖物。与第一与第二剖面图1200A与图1200B相反，超材料覆盖物1240提供单一的拱形表面，其中左边与右边表面部分1240A与1240B是在每一个的预定区域大致上平行于焊线接合540A与540B。因此，虽然分别与第一与第二剖面图1200A与1200B的超材料覆盖物1220与1210相比，超材料覆盖物1240通常未为焊线接合540A与540B提供受控制的阻抗环境，但是就地(in situ)形成此结构降低了复杂度。因此，第三剖面图1200C中的示例的布局实施例是示出一种与第一与第二剖面图1200A与1200B均不同的实现成本与性能之间的权衡(tradeoff)。
现在请参考图13，其示出了根据现有技术的解决方案与具有超材料覆盖物的焊线的本发明实施例的电性内连线的传输特性的模拟结果1300。针对每个结果，在电性内连线的末端所接收的电性信号比上所施加的电性信号的比值显示为频率的函数。第一曲线1310描绘针对根据现有技术的长度为14500μm的单一、分离的焊线，其本质上提供随着频率增加的电性内连线线性衰减的传输，其在约1.3GHz对于14500μm的焊线长度具有1dB的损耗，在约2.4GHz为2dB的损耗，在约3.3GHz为3dB的损耗。
第二曲线1320描绘根据Wyland(美国专利7,217,997)的现有技术中单一的14500μm的焊线长度的结果，其中接地拱是置于焊线的上方，并具有空气介电质。与单一、分离的焊线相比，第二曲线1320几乎线性下降至2GHz为止，然后变得较平坦，在2.6GHz达到约1.6dB的最大损耗。最后显示的是第三曲线1330，其代表根据本发明实施例的示例的电性内连线，其中采用超材料覆盖物与14500μm的焊线相结合。目前损耗是大致上为线性增加，在2.2GHz达到约为1dB的最大损耗，再继续则损耗减少，在4GHz损耗为0.6dB。
示例的实施例与现有技术的效果的比较是相当明确的。例如在3.3GHz，第三曲线1330仅显示0.75dB的损耗，对比于第一曲线1310中的分离焊线的3dB，有2.25dB的改善；当与用于具有一电性接地平面的焊线的第二曲线1320相比时，第三曲线1330显示了从1.55dB至0.95dB的0.6dB的改善。
在不偏离本发明的精神与范围的情况下，可设想多个实施例。

Claims (18)

1.一种改善二个电性元件之间的电性内连线的方法，包括：
提供多个电性内连线的至少一电性内连线至一第一器件，每一电性内连线以至少一内连线长度为特征；
提供一覆盖物，所述覆盖物包括至少一第一超材料结构，并对于所述内连线长度的至少一既定部分被设置为大致平行于多个电性内连线的所述至少一电性内连线；以及
提供一衬垫物，所述衬垫物包括至少一第二超材料结构，并对于所述内连线长度的至少另一既定部分被设置为大致平行于所述电性内连线。
2.如权利要求1所述的方法，其中：
提供所述第一超材料结构包括提供至少一连续的导体层与一介电层，所述介电层具有嵌入其内的多个隔离的导体中的至少一隔离的导体。
3.如权利要求1所述的方法，其中：
提供所述电性内连线与覆盖物包括提供一单一结构。
4.如权利要求1所述的方法，其中：
提供多个电性内连线的一电性内连线包括提供终止于所述第一器件的至少一个大致上的周边区并在所述第一器件的占用面积内的一电性内连线。
5.如权利要求4所述的方法，其中：
所述多个电性内连线的至少一第一既定部分的终止位置是不同于所述多个电性内连线的一第二既定部分的终止位置。
6.如权利要求1所述的方法，其中：
提供所述覆盖物、衬垫物、与多个电性内连线的至少一电性内连线包括提供一单一集成结构。
7.如权利要求1所述的方法，其中：
提供所述第二超材料包括提供该第一超材料、与该第一超材料具有一既定关系的一超材料、以及不同于该第一超材料的一超材料中的至少之一.
8.如权利要求1所述的方法，其中：
提供所述覆盖物还包括提供至少所述第一超材料与一第二超材料，其中所述第一超材料与所述多个电性内连线的一第一既定部分相关联，所述第二超材料与所述多个电性内连线的一第二既定部分相关联。
9.如权利要求1所述的方法，其中：
提供所述第一超材料包括提供具有被选择以改善所述多个电性内连线的至少一电性内连线的一电性特性的材料性质的一第一超材料，所述电性特性选自包括如下特性的组：阻抗、传播损耗、辐射损耗、频率响应、上升时间与下降时间。
10.一种二个电性元件之间的电路，包括：
至一第一器件的多个电性内连线的至少一电性内连线，每一电性内连线以至少一内连线长度为特征；
一覆盖物，所述覆盖物包括至少一第一超材料结构，并对于所述内连线长度的至少一既定部分被设置为大致平行于多个电性内连线的所述至少一电性内连线；以及
一衬垫物，所述衬垫物包括至少一第二超材料结构，并对于所述内连线长度的至少另一既定部分被设置为大致平行于所述电性内连线。
11.如权利要求10所述的电路，其中：
提供所述第一超材料结构包括提供至少一连续的导体层与一介电层，所述介电层具有嵌入其内的多个隔离的导体中的至少一隔离的导体。
12.如权利要求10所述的电路，其中：
提供所述电性内连线与覆盖物包括提供一单一集成结构。
13.如权利要求10所述的电路，其中：
提供多个电性内连线的一电性内连线包括提供终止于所述第一器件的至少一个大致上的周边区并在所述第一器件的占用面积内的一电性内连线。
14.如权利要求13所述的电路，其中：
所述多个电性内连线的至少一第一既定部分的终止位置是不同于所述多个电性内连线的一第二既定部分的终止位置。
15.如权利要求10所述的电路，其中：
提供所述覆盖物、衬垫物、与多个电性内连线的至少一电性内连线包括提供一单一集成结构。
16.如权利要求10所述的电路，其中：
提供所述第二超材料包括提供所述第一超材料、与所述第一超材料具有一既定关系的一超材料、以及不同于所述第一超材料的一超材料中的至少之一。
17.如权利要求10所述的电路，其中：
提供所述覆盖物还包括提供至少所述第一超材料与一第二超材料，其中所述第一超材料与所述多个电性内连线的一第一既定部分相关联，所述第二超材料与所述多个电性内连线的一第二既定部分相关联。
18.如权利要求10所述的电路，其中：
提供所述第一超材料包括提供具有被选择以改善所述多个电性内连线的至少一电性内连线的一电性特性的材料性质的一第一超材料，所述电性特性选自包括如下特性的组：阻抗、传播损耗、辐射损耗、频率响应、上升时间与下降时间。
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CN102160175A (zh) 2011-08-17
US9006098B2 (en) 2015-04-14
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