CN102157484B - Lead frame and chip packaging body - Google Patents
Lead frame and chip packaging body Download PDFInfo
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- CN102157484B CN102157484B CN201110047717.8A CN201110047717A CN102157484B CN 102157484 B CN102157484 B CN 102157484B CN 201110047717 A CN201110047717 A CN 201110047717A CN 102157484 B CN102157484 B CN 102157484B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Packaging Frangible Articles (AREA)
Abstract
The invention discloses a lead frame and a chip packaging body. The lead frame comprises a framework, a chip carrier, a plurality of connecting rods and a plurality of pins. The chip carrier is configured in a packaging region surrounded by the framework. The chip carrier is provided with an open groove. The open groove extends along the length direction of the chip carrier, and the width of the open groove is less than or equal to one third of the width of the chip carrier. The connecting rods are connected for connecting the chip carrier with the framework. The pins are positioned in the packaging region and configured at the periphery of the chip carrier, and one end of each pin is connected with the framework.
Description
Technical field
The present invention relates to a kind of potted element, and particularly relate to a kind of lead frame and chip packing-body.
Background technology
Generally speaking, the production of integrated circuit is mainly divided into three phases: the encapsulation of the manufacture of silicon, the making of integrated circuit and integrated circuit.In integrated antenna package process, lead frame is to provide the medium of the electrical connection between chip and printed circuit board (PCB).
Lead frame comprises framework (frame), chip carrier (die pad), multiple connecting rod (tie bar) and multiple pin (lead).Connecting rod is connected between framework and chip carrier, with the relative position between fixed core bar and framework.After chip electrical is connected to pin by chip configuration on chip carrier and via routing manufacture craft (wire bonding process), generally can first by adhesive material mold forming on lead frame, with the part of the part of coating chip, chip carrier, connecting rod adjacent chips seat and pin adjacent chips seat.Afterwards, then by framework excision chip packing-body is completed.
But the routing position on chip and chip set-up mode have multiple change usually in order to meet user demand, and chip also has various different size, therefore must use the lead frame of different kenel, thus causes the problem that cost improves.
Summary of the invention
The object of the present invention is to provide a kind of lead frame, it is applicable to chip and the various chip installing mode of various sizes.
Another object of the present invention is to provide a kind of chip packing-body, and it has lower production cost.
For reaching above-mentioned purpose, the present invention proposes a kind of lead frame, and it comprises framework, chip carrier, multiple connecting rod and multiple pin.Chip carrier is configured in the packaging area that framework surrounds.Chip carrier has fluting (slot).Fluting extends along the length direction of chip carrier, and the width of fluting is less than or equal to 1/3rd of the width of chip carrier.Connecting rod connects chip carrier and framework.Pin is positioned at packaging area and is configured at around chip carrier, and one end connecting frame of each pin.
According to the lead frame described in the embodiment of the present invention, two carrier strip that above-mentioned chip carrier comprises side by side (side by side).Fluting is between two carrier strip.Article two, the two ends of carrier strip are connected, and to form connecting portion respectively, and connecting rod is connected between framework and corresponding connecting portion.
According to the lead frame described in the embodiment of the present invention, multiple strengthening bar can also be had.These strengthening bars are configured in fluting, and extend along the Width of chip carrier and connect two carrier strip.
According to the lead frame described in the embodiment of the present invention, above-mentioned strengthening bar is such as that contiguous connecting portion is arranged.
According to the lead frame described in the embodiment of the present invention, above-mentioned connecting rod such as extends along the length direction of chip carrier.
According to the lead frame described in the embodiment of the present invention, above-mentioned pin is such as divided into Liang Ge group and is arranged at the relative both sides of chip carrier abreast.In each group, the area in the region that outermost pin and framework enclose accounts in fact 20% to 40% of the area of packaging area.
The present invention proposes a kind of chip packing-body, and it comprises chip carrier, multiple connecting rod, multiple pin, many first wires, the first chip and packing colloids.Chip carrier has first surface and the second surface relative to first surface.In addition, chip carrier has fluting.Fluting extends along the length direction of chip carrier, and the width of fluting is less than or equal to 1/3rd of the width of chip carrier.Connecting rod connects chip carrier and framework.Pin configuration is around chip carrier.First chip configuration on chip carrier, and is electrically connected with pin via the first wire.Coated first chip of packing colloid, the first wire, chip carrier, a part for each connecting rod and a part for each pin.In addition, the width of chip carrier is more than or equal to 1/3rd of the width of the first chip, and the length of chip carrier is more than or equal to 1.5 times of the length of the first chip.
According to the chip packing-body described in the embodiment of the present invention, above-mentioned chip carrier comprises two carrier strip side by side.Fluting is between two carrier strip, and the two ends of two carrier strip are connected, and to form connecting portion respectively, and connecting rod is connected between framework and corresponding connecting portion.
According to the chip packing-body described in the embodiment of the present invention, the first above-mentioned chip is such as configured on the first surface of chip carrier.First chip have the 3rd surface, relative to the 3rd surface the 4th surface and multiple first connection pad.The first surface of the 4th surperficial object chip seat.First connection pad is positioned at the periphery on the 3rd surface, and the first wire is connected between the first connection pad and corresponding pin.
According to the chip packing-body described in the embodiment of the present invention, can also have the second chip and many second wires, wherein the second chip configuration is on the second surface of chip carrier.Second chip have the 5th surface, relative to the 5th surface the 6th surface and multiple second connection pad.The second surface of the 6th surperficial object chip seat of the second chip.Second connection pad is positioned at the periphery on the 5th surface, and the second wire is connected between the second connection pad and corresponding pin.
According to the chip packing-body described in the embodiment of the present invention, the first above-mentioned chip is such as configured on the second surface of chip carrier, and the first chip have the 3rd surface, relative to the 3rd surface the 4th surface and multiple first connection pad.The second surface of the 3rd surperficial object chip seat.First connection pad is positioned at the central authorities on the 3rd surface, and the first wire is connected to the first connection pad and corresponding pin through fluting.
According to the chip packing-body described in the embodiment of the present invention, the first above-mentioned chip such as has multiple first connection pad.These first connection pads are positioned at the periphery on the 3rd surface.Have gap between pin and chip carrier, this gap exposes these the first connection pads, and the first wire is connected to through gap the first connection pad and corresponding pin.
According to the chip packing-body described in the embodiment of the present invention, the second chip and many second wires can also be had, wherein the second chip configuration in the first chip the 4th on the surface.Second chip have the 5th surface, relative to the 5th surface the 6th surface and multiple second connection pad.The second surface of the 6th surperficial object chip seat.Second connection pad is positioned at the periphery on the 5th surface, and the second wire is connected between the second connection pad and corresponding pin.
Based on above-mentioned, in the present invention, because chip carrier has fluting, therefore lead frame of the present invention can be applicable to the chip package of different kenel.In other words, lead frame of the present invention can be made or is purchased in large quantities, and reaches the object reduced costs thus.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended accompanying drawing to be described in detail below.
Accompanying drawing explanation
The upper schematic diagram of lead frame of Figure 1A for illustrating according to the embodiment of the present invention;
The generalized section of lead frame of Figure 1B for illustrating along the I-I ' section in Figure 1A;
The chip packing-body generalized section of Fig. 2 for illustrating according to the first embodiment of the present invention;
The chip packing-body generalized section of Fig. 3 for illustrating according to the second embodiment of the present invention;
The chip packing-body generalized section of Fig. 4 for illustrating according to the third embodiment of the present invention;
The chip packing-body generalized section of Fig. 5 for illustrating according to the fourth embodiment of the present invention;
The chip packing-body generalized section of Fig. 6 for illustrating according to the fifth embodiment of the present invention;
The chip packing-body generalized section of Fig. 7 for illustrating according to the sixth embodiment of the present invention.
Main element symbol description
10,20,30,40,50,60,70: lead frame
100: framework
100a: packaging area
102: chip carrier
102a: carrier strip
102b: connecting portion
103a: first surface
103b: second surface
104: connecting rod
106,106a: pin
108: fluting
110: strengthening bar
112: gap
114a, 114b: region
200: the first chips
200a: the three surface
200b: the four surface
202: the first wires
204: packing colloid
206: sticky material
208: the first connection pads
300: the second chips
300a: the five surface
300b: the six surface
302: the second wires
304: the second connection pads
306: adhesion coating
L1: length
W1, W2, W3: width
Embodiment
The upper schematic diagram of lead frame of Figure 1A for illustrating according to the embodiment of the present invention.The generalized section of lead frame of Figure 1B for illustrating along the I-I ' section in Figure 1A.Referring to Figure 1A and Figure 1B, lead frame 10 comprises framework 100, chip carrier 102, connecting rod 104 and pin 106.Chip carrier 102 is configured in the packaging area 100a that framework 100 surrounds.In the present embodiment, chip carrier 102 comprises two carrier strip 102a side by side.Article two, the two ends of carrier strip 102a are connected, to form connecting portion 102b respectively.The visual actual demand of connecting portion 102b and be various shape, is not limited to the shape shown in Figure 1A.Connecting rod 104 is connected between framework 100 and corresponding connecting portion 102b, with the relative position between fixed core bar 102 and framework 100.Connecting rod 104 such as extends along the length direction of chip carrier 102.The visual actual demand of connecting rod 104 and be various shape, is not limited to the shape shown in Figure 1A.
In addition, chip carrier 102 has fluting 108.Fluting 108 is between two carrier strip 102a.Fluting 108 extends along the length direction of chip carrier 102, and the width W 3 of fluting 108 is less than or equal to 1/3rd of the width W 1 of chip carrier 102.In the present embodiment, multiple strengthening bar 110 is also configured with in fluting 108.Strengthening bar 110 extends along the Width of chip carrier 102, and connects two carrier strip 102a, to increase the support force of chip carrier 102.Strengthening bar 110 is such as that contiguous connecting portion 102b is arranged, and thus, can have a perforate, and this perforate is being carried out making mould stream comparatively uniform, smooth in sealing process, improves the quality of formed chip packing-body between strengthening bar 110 and connecting portion 102b.
Pin 106 is positioned at packaging area 100a, and is configured at chip carrier 102 around.One end connecting frame 100 of each pin 106, and the other end does not contact with chip carrier 102, and and between chip carrier 102, there is gap 112.In the present embodiment, these pins 106 are divided into Liang Ge group, and are arranged at the relative both sides of chip carrier 102 abreast.In addition, in each group, the gross area of region 114a and the 114b that outermost pin 106a and framework 100 enclose accounts in fact 20% to 40% of the area of packaging area 100a.In the present embodiment, lead frame 10 is made up of metal material, such as copper or other metallic conduction materials.Further, depending on actual demand, the surface of pin 106 can also have one deck electrodeposited coating (not illustrating).This electrodeposited coating is such as silver layer, nickel dam or layer gold.
Special one carries, and in the present embodiment, framework 100, chip carrier 102, connecting rod 104 are in the same plane with pin 106, and therefore lead frame 10 can be applicable to pin (lead-on-chip, LOC) packaging manufacturing process on chip.
In the present embodiment, because chip carrier 102 has fluting 108, therefore lead frame 10 can be applicable to the chip package of different kenel.For example, when the connection gasket on chip is positioned at chip peripheral, chip can be installed in the front of lead frame 10, and connection gasket is electrically connected with pin 106 via wire.Or, when the connection gasket on chip is positioned at chip central, chip can be installed in the back side of lead frame 10 and makes fluting 108 expose connection gasket, connection gasket can be electrically connected with pin 106 through the wire of fluting 108.
Explain to the chip packing-body using the lead frame 10 of the present embodiment to be formed below.Due to after formation packing colloid, framework can be excised, therefore will not there is framework 10 in following figure.In addition, in following embodiment, identical element represents with identical label.
The chip packing-body generalized section of Fig. 2 for illustrating according to the first embodiment of the present invention.Referring to Figure 1A, Figure 1B and Fig. 2, chip packing-body 20 comprises chip carrier 102, connecting rod (not illustrating), pin 106, first chip 200, first wire 202 and packing colloid 204.Chip carrier 102 has first surface 103a and the second surface 103b relative to first surface 103a.First chip 200 has the 3rd surperficial 200a and the 4th surperficial 200b relative to the 3rd surperficial 200a.First chip 200 is configured on chip carrier 102 in the mode of the first surface 103a of the 4th surperficial 200b object chip seat 102.In addition, between the first chip 200 and chip carrier 102, there is sticky material 206, be fixed on chip carrier 102 to make the first chip 200.Sticky material 206 is such as two-sided tape.First chip 200 has multiple first connection pad 208.First connection pad 208 is positioned at the periphery of the 3rd surperficial 200a, and the first wire 202 is connected between the first connection pad 208 and corresponding pin 106, is electrically connected with pin 106 to make the first chip 200.Coated first chip 200, first wire 202 of packing colloid 204, chip carrier 102, a part for each connecting rod and a part for each pin 106.
In addition, in the present embodiment, the width W 1 of chip carrier 102 is more than or equal to 1/3rd of the width W 2 of the first chip 200, and the length L1 of chip carrier 102 is more than or equal to 1.5 times of the length (length that vertical drawing extends) of the first chip 200.
The chip packing-body generalized section of Fig. 3 for illustrating according to the second embodiment of the present invention.Referring to Figure 1A, Figure 1B and Fig. 3, in the present embodiment, chip packing-body 30, except comprising all elements in Fig. 2, also comprises the second chip 300 and the second wire 302.Second chip 300 has the 5th surperficial 300a and the 6th surperficial 300b relative to the 5th surperficial 300a.Second chip 300 is configured on chip carrier 102 in the mode of the second surface 103b of the 6th surperficial 300b object chip seat 102.In addition, between the second chip 300 and chip carrier 102, also there is sticky material 206, be fixed on chip carrier 102 to make the second chip 300.Second chip 300 has multiple second connection pad 304.Second connection pad 304 is positioned at the periphery of the 5th surperficial 300a, and the second wire 302 is connected between the second connection pad 304 and corresponding pin 106, is electrically connected with pin 106 to make the second chip 300.Coated first chip 200, first wire 202, second chip 300, second wire 302 of packing colloid 204, chip carrier 102, a part for each connecting rod and a part for each pin 106.
In addition, in the present embodiment, the width W 1 of chip carrier 102 is more than or equal to 1/3rd of the width W 4 of the second chip 300, and the length L1 of chip carrier 102 is more than or equal to 1.5 times of the length (length that vertical drawing extends) of the second chip 300.
The chip packing-body generalized section of Fig. 4 for illustrating according to the third embodiment of the present invention.Please refer to Fig. 4, chip packing-body 40 is with the difference of chip packing-body 20: in chip packing-body 40, be configured on chip carrier 102 in the mode of the second surface 103b of the 3rd surperficial 200a object chip seat 102.Between the first chip 200 and chip carrier 102, there is sticky material 206, be fixed on chip carrier 102 to make the first chip 200.In addition, first connection pad 208 is positioned at the central authorities of the 3rd surperficial 200a, and slot and 108 expose the first connection pad 208, and the first wire 202 is connected to the first connection pad 208 and corresponding pin 106 through fluting 108, is electrically connected with pin 106 to make the first chip 200.
In the present embodiment, because the first wire 202 is connected to the first connection pad 208 and corresponding pin 106 through fluting 108, the length of the first wire 202 can therefore effectively be shortened.
The chip packing-body generalized section of Fig. 5 for illustrating according to the fourth embodiment of the present invention.Please refer to Fig. 5, chip packing-body 50 is with the difference of chip packing-body 40: in chip packing-body 50, more include the second chip 300 and the second wire 302.Second chip 300 is configured on the 4th surperficial 200b of the first chip 200 in the mode of the second surface 103b of the 6th surperficial 300b object chip seat 102.Second chip 300 has multiple second connection pad 304.Second connection pad 304 is positioned at the periphery of the 5th surperficial 300a, and the second wire 302 is connected between the second connection pad 304 and corresponding pin 106.In addition, be configured with adhesion coating 306 between the first chip 200 and the second chip 300, be fixed on the first chip 200 to make the second chip 300.In addition, coated first chip 200, first wire 202, second chip 300, second wire 302 of packing colloid 204, chip carrier 102, a part for each connecting rod and a part for each pin 106.
The chip packing-body generalized section of Fig. 6 for illustrating according to the fifth embodiment of the present invention.Please refer to Fig. 6, chip packing-body 60 is with the difference of chip packing-body 40: in chip packing-body 40, first wire 202 is connected to the first connection pad 208 and corresponding pin 106 through fluting 108, and in chip packing-body 60, the first 202, wire is through the gap 112 between chip carrier 102 to pin 106 and is connected between the first connection pad 208 and corresponding pin 106.
The chip packing-body generalized section of Fig. 7 for illustrating according to the sixth embodiment of the present invention.Please refer to Fig. 7, chip packing-body 70 is with the difference of chip packing-body 50: in chip packing-body 50, first wire 202 is connected to the first connection pad 208 and corresponding pin 106 through fluting 108, and in chip packing-body 70, the first 202, wire is through the gap 112 between chip carrier 102 to pin 106 and is connected between the first connection pad 208 and corresponding pin 106.
Although disclose the present invention in conjunction with above embodiment; but itself and be not used to limit the present invention; this operator is familiar with in any art; without departing from the spirit and scope of the present invention; a little change and retouching can be done, therefore being as the criterion of should defining with the claim of enclosing of protection scope of the present invention.
Claims (10)
1. a lead frame, comprising:
Framework;
Chip carrier, be configured in the packaging area that this framework surrounds, this chip carrier comprises two carrier strip side by side, and the two ends of this two carrier strip are connected, to form a junction respectively, and this chip carrier has fluting, and wherein this fluting is between this two carrier strip, and extend between this two connecting portion along the length direction of this chip carrier, and wherein the width of this fluting is less than or equal to 1/3rd of the width of this chip carrier;
Multiple connecting rod, connects this chip carrier and this framework, and wherein those connecting rods are connected between this framework and this corresponding connecting portion;
Multiple pin, is positioned at this packaging area, and is configured at around this chip carrier, and respectively one end of this pin connects this framework; And
Multiple strengthening bar, is configured in this fluting, and extends along the Width of this chip carrier and connect this two carrier strip, and wherein those strengthening bars those connecting portions contiguous are arranged, and have perforate between those strengthening bars and those connecting portions,
The width of wherein said chip carrier equals 1/3rd of the width of the chip being configured at described chip carrier, and the length of described chip carrier is more than or equal to 1.5 times of the length of described chip.
2. lead frame as claimed in claim 1, wherein those connecting rods extend along the length direction of this chip carrier.
3. lead frame as claimed in claim 1, wherein those pins are divided into Liang Ge group and are arranged at the relative both sides of this chip carrier abreast, and respectively in this group, the area in the region that those pins outermost and this framework enclose accounts for 20% to 40% of the area of this packaging area.
4. a chip packing-body, comprising:
Chip carrier, there is first surface and the second surface relative to this first surface, and this chip carrier comprises two carrier strip side by side, and the two ends of this two carrier strip are connected, to form a junction respectively, and this chip carrier has fluting, wherein this fluting is between this two carrier strip, and extends between this two connecting portion along the length direction of this chip carrier, and wherein the width of this fluting is less than or equal to 1/3rd of the width of this chip carrier;
Multiple connecting rod, can connect this chip carrier and a framework, and wherein those connecting rods are connected between this framework and this corresponding connecting portion;
Multiple pin, is configured at around this chip carrier;
Many first wires;
First chip, is configured on this chip carrier, and is electrically connected with those pins via those first wires;
Packing colloid, a part for the part of this first chip coated, those first wires, this chip carrier, respectively those connecting rods and each this pin; And
Multiple strengthening bar, is configured in this fluting, and this Width along chip carrier extends and connects this two carrier strip, and those strengthening bars those connecting portions contiguous are arranged, and have perforate between those strengthening bars and those connecting portions,
Wherein the width of this chip carrier equals 1/3rd of the width of this first chip, and the length of this chip carrier is more than or equal to 1.5 times of the length of this first chip.
5. chip packing-body as claimed in claim 4, wherein this first chip configuration is on this first surface of this chip carrier, and this first chip have the 3rd surface, relative to the 3rd surface the 4th surface and multiple first connection pad, wherein, 4th surface is towards this first surface of this chip carrier, those first connection pads are positioned at the periphery on the 3rd surface, and those first wires are connected between those the first connection pad and those corresponding pins.
6. chip packing-body as claimed in claim 5, also comprise the second chip and many second wires, wherein this second chip configuration is on this second surface of this chip carrier, this second chip have the 5th surface, relative to the 5th surface the 6th surface and multiple second connection pad, wherein, 6th surface of this second chip towards this second surface of this chip carrier, those second connection pads in the periphery on the 5th surface and those the second wires be connected between those the second connection pad and those corresponding pins.
7. chip packing-body as claimed in claim 4, wherein this first chip configuration is on this second surface of this chip carrier, and this first chip have the 3rd surface, relative to the 3rd surface the 4th surface and multiple first connection pad, wherein, 3rd surface is towards this second surface of this chip carrier, those first connection pads are positioned at the central authorities on the 3rd surface, and those first wires are connected to those the first connection pad and those corresponding pins through this fluting.
8. chip packing-body as claimed in claim 7, also comprise the second chip and many second wires, wherein this second chip configuration in this first chip the 4th on the surface, this second chip have the 5th surface, relative to the 5th surface the 6th surface and there is multiple second connection pad, wherein, 6th surface is towards this second surface of this chip carrier, those second connection pads are positioned at the periphery on the 5th surface, and those second wires are connected between those the second connection pad and those corresponding pins.
9. chip packing-body as claimed in claim 4, wherein this first chip has multiple first connection pad, those first connection pads are positioned at the periphery on the 3rd surface, and there is between those pins and this chip carrier gap, this gap exposes those the first connection pads, and those first wires are connected to those the first connection pad and those corresponding pins through this gap.
10. chip packing-body as claimed in claim 9, also comprise the second chip and many second wires, wherein this second chip configuration in this first chip the 4th on the surface, this second chip have the 5th surface, relative to the 5th surface the 6th surface and multiple second connection pad, wherein, 6th surface is towards this second surface of this chip carrier, and those second connection pads are positioned at the periphery on the 5th surface, and those second wires are connected between those the second connection pad and those corresponding pins.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110047717.8A CN102157484B (en) | 2011-02-28 | 2011-02-28 | Lead frame and chip packaging body |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110047717.8A CN102157484B (en) | 2011-02-28 | 2011-02-28 | Lead frame and chip packaging body |
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| Publication Number | Publication Date |
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| CN102157484A CN102157484A (en) | 2011-08-17 |
| CN102157484B true CN102157484B (en) | 2015-05-06 |
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| CN201110047717.8A Active CN102157484B (en) | 2011-02-28 | 2011-02-28 | Lead frame and chip packaging body |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104465599B (en) * | 2014-12-19 | 2018-03-23 | 日月光封装测试(上海)有限公司 | Lead frame bar and the semiconductor package body using the lead frame bar |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1354518A (en) * | 2000-11-17 | 2002-06-19 | 矽品精密工业股份有限公司 | Multiwafer integrated circuit package structure |
| US6600335B2 (en) * | 2000-05-16 | 2003-07-29 | Micron Technology, Inc. | Method for ball grid array chip packages having improved testing and stacking characteristics |
| CN1466197A (en) * | 2002-06-18 | 2004-01-07 | 矽品精密工业股份有限公司 | Sequare shape pin-free planar semiconductor package structure and mfg. method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07153896A (en) * | 1993-11-29 | 1995-06-16 | Toshiba Corp | Resin-sealed semiconductor device and manufacture thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6600335B2 (en) * | 2000-05-16 | 2003-07-29 | Micron Technology, Inc. | Method for ball grid array chip packages having improved testing and stacking characteristics |
| CN1354518A (en) * | 2000-11-17 | 2002-06-19 | 矽品精密工业股份有限公司 | Multiwafer integrated circuit package structure |
| CN1466197A (en) * | 2002-06-18 | 2004-01-07 | 矽品精密工业股份有限公司 | Sequare shape pin-free planar semiconductor package structure and mfg. method |
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