CN102148245A - Intrinsic MOS (metal oxide semiconductor) transistor and forming method thereof - Google Patents
Intrinsic MOS (metal oxide semiconductor) transistor and forming method thereof Download PDFInfo
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Abstract
The invention discloses an intrinsic MOS (metal oxide semiconductor) transistor and a forming method thereof. The forming method of the intrinsic MOS transistor comprises the following steps: providing a semiconductor substrate on which a gate medium layer and a gate are arranged in sequence, the semiconductor substrate on one side of the gate is a source region, and the semiconductor substrate on the other side is a drain region; performing first ion implantation on the source region and the drain region so as to directly form a source and a drain in the semiconductor substrate; and performing second ion implantation on the gate, wherein the ion type of the second ion implantation is opposite to that of the first ion implantation. According to the invention, the threshold voltage of the intrinsic MOS transistor is increased.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of intrinsic MOS transistor and forming method thereof.
Background technology
Along with the raising of integrated circuit integrated level, device size is progressively scaled, and characteristic size has reached the 32nm magnitude at present.Metal oxide semiconductor field effect tube (MOS) is modal semiconductor device, is the elementary cell that constitutes various complicated circuits.MOS transistor basic structure comprises three main region: source electrode (source), drain electrode (drain) and gate electrode (gate).Wherein source electrode and drain electrode according to the type of device difference, can be divided into n type doping (NMOS) and p type doping (PMOS) by highly doped formation.
Because the threshold voltage of MOS transistor is relevant with substrate doping, for the threshold voltage (threshold voltage) that improves MOS transistor, MOS transistor of the prior art is formed in the well region (well) in the Semiconductor substrate mostly, with the nmos pass transistor is example, its forming process comprises: Semiconductor substrate is carried out P type ion inject, form P trap (P-well); On described P trap, form gate dielectric layer and gate electrode successively; With the gate electrode is that mask carries out the injection of N type ion, formation source/drain electrode to described Semiconductor substrate.
In addition, one type MOS transistor is arranged also in the prior art, it is not to be formed in the well region, but is formed directly in the Semiconductor substrate, and this type of MOS transistor is called intrinsic MOS transistor (native MOS).Be example with the nmos pass transistor still, its forming process comprises: form gate dielectric layer and gate electrode on the P type semiconductor substrate successively; With the gate electrode is that mask carries out the injection of N type ion, formation source/drain electrode to described Semiconductor substrate.Because the intrinsic MOS transistor is formed directly in the Semiconductor substrate, its forming process does not comprise the ion implantation process of well region.Because do not form the ion implantation process of well region, the doping content of described P type semiconductor substrate is more much lower than the substrate (being well region) of the common MOS transistor that is formed with well region, thereby its threshold voltage is also much lower accordingly.Still be example with the nmos pass transistor, the transistorized threshold voltage of intrinsic NMOS approaches 0, for " often opening " (already on) state, belongs to depletion-type mos transistor; The threshold voltage that is formed at the nmos pass transistor in the well region then is positive voltage, is reinforcing MOS transistor.
Because the intrinsic MOS transistor has higher response speed, thereby more being applied in low voltage circuit and the current mirroring circuit.But, because its threshold voltage is lower, belong to depletion-type mos transistor, be normally open, limited its range of application.
About the intrinsic MOS transistor, it is 200310109233.7 Chinese patent application that more detailed contents please refer to disclosed application number.
Summary of the invention
The problem that the present invention solves provides a kind of intrinsic MOS transistor and manufacture method thereof, improves the threshold voltage of intrinsic MOS transistor.
For addressing the above problem, the invention provides a kind of intrinsic MOS transistor, comprising:
Semiconductor substrate;
Gate dielectric layer is formed on the described Semiconductor substrate;
Gate electrode is formed on the described gate dielectric layer;
Source electrode and drain electrode directly are formed in the Semiconductor substrate of described gate electrode both sides respectively;
The doping type of described gate electrode is opposite with the doping type of source electrode and drain electrode.
Optionally, the doping type of described Semiconductor substrate is a P type ion, and the doping type of described source electrode and drain electrode is a N type ion, and the doping type of described gate electrode is a P type ion.
Optionally, the doping type of described Semiconductor substrate is a N type ion, and the doping type of described source electrode and drain electrode is a P type ion, and the doping type of described gate electrode is a N type ion.
Optionally, the doping content scope of described Semiconductor substrate is 1E16/cm
3To 10E16/cm
3
Optionally, the doping content scope of described source electrode and drain electrode is 1E19/cm
3To 10E19/cm
3
Optionally, the doping content scope of described gate electrode is 1E19/cm
3To 10E19/cm
3
Optionally, described intrinsic MOS transistor also comprises side wall, is formed on the Semiconductor substrate of described gate electrode and gate dielectric layer both sides.
For addressing the above problem, the invention provides a kind of formation method of intrinsic MOS transistor, comprising:
Semiconductor substrate is provided, is formed with gate dielectric layer and gate electrode on the described Semiconductor substrate successively, the Semiconductor substrate of described gate electrode one side is the source region, and the Semiconductor substrate of opposite side is the drain region;
The injection of first ion is carried out in described source region and drain region, in described Semiconductor substrate, directly formed source electrode and drain electrode;
Described gate electrode is carried out second ion inject, the ionic type that described second ion injects is opposite with the ionic type that described first ion injects.
Optionally, the doping type of described Semiconductor substrate is a P type ion, and the ionic type that described first ion injects is a N type ion, and the ionic type that described second ion injects is a P type ion.
Optionally, the ion that described first ion injects is P ion or As ion, and the ion that described second ion injects is B ion or In ion.
Optionally, the doping type of described Semiconductor substrate is a N type ion, and the ionic type that described first ion injects is the P type, and the ionic type that described second ion injects is the N type.
Optionally, the ion that described first ion injects is B ion or In ion, and the ion that described second ion injects is P ion or As ion.
Optionally, the doping content scope of described Semiconductor substrate is 1E16/cm
3To 10E16/cm
3
Optionally, the dosage of described first ion injection is 1E15/cm
2To 10E15/cm
2, energy is 50KeV to 70KeV.
Optionally, the dosage of described second ion injection is 1E15/cm
2To 10E15/cm
2, energy is 30KeV to 50KeV.
Optionally, described source region and drain region are being carried out also comprising before first ion injects: the injection of light dope ion is carried out in described source region and drain region, formed lightly doped source electrode and drain electrode.
Optionally, the dosage of described light dope ion injection is 1E13/cm
2To 10E13/cm
2, energy is 50KeV to 70KeV.
Optionally, described source region and drain region are carried out the light dope ion inject after and carry out first ion and also comprise before injecting: at the both sides of described gate electrode and gate dielectric layer formation side wall.
Compared with prior art, technique scheme has the following advantages: the intrinsic MOS transistor of the technical program directly is formed in the Semiconductor substrate, do not form well region, and the doping type of gate electrode is opposite with the doping type of source electrode and drain electrode, thereby has improved the threshold voltage of intrinsic MOS transistor.
Description of drawings
Fig. 1 is the schematic flow sheet of formation method of the intrinsic MOS transistor of the embodiment of the invention;
Fig. 2 to Fig. 6 is the cross-sectional view of each step of the transistorized forming process of intrinsic NMOS of the embodiment of the invention;
Fig. 7 is the transistorized structural representation of intrinsic NMOS that the embodiment of the invention forms.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public concrete enforcement.
Intrinsic MOS transistor of the prior art directly is formed in the Semiconductor substrate, do not form well region, and in the process of formation source/drain electrode, with the gate electrode is that mask carries out the ion injection, in formation source/drain electrode, the scope that ion injects has also comprised gate electrode simultaneously, makes that the doping type of gate electrode is identical with the doping type of source/drain electrode.With the intrinsic NMOS transistor is example, its source/drain to the N type mixes, and gate electrode also mixes for the N type, and corresponding semiconductor substrate is the P type semiconductor substrate, does not inject the formation well region owing to carry out ion, and the doping content of described Semiconductor substrate is lower.Because doping content and the material of gate electrode and the threshold voltage that doping type can influence MOS transistor of Semiconductor substrate, and the doping type of the gate electrode of the intrinsic MOS transistor of prior art is identical with Semiconductor substrate, therefore the work function difference (work function difference) of gate electrode and Semiconductor substrate is less, cause the threshold voltage of intrinsic MOS transistor of prior art less, approach 0, be normally open, influenced its range of application.
The formation method of intrinsic MOS transistor provided by the invention, the ion injection is carried out in source/drain electrode and gate electrode respectively, make that the doping type of gate electrode is opposite, identical with Semiconductor substrate with source/drain electrode, thereby increased the work function difference between gate electrode and the Semiconductor substrate, improved the threshold voltage of intrinsic MOS transistor.
Fig. 1 is the schematic flow sheet of the transistorized formation method of the intrinsic NMOS of the embodiment of the invention.As shown in Figure 1, comprising: execution in step S101, Semiconductor substrate is provided, be formed with gate dielectric layer and gate electrode on the described Semiconductor substrate successively, the Semiconductor substrate of described gate electrode one side is the source region, the Semiconductor substrate of opposite side is the drain region; Execution in step S102 carries out the injection of first ion to described source region and drain region, directly forms source electrode and drain electrode in described Semiconductor substrate; Execution in step S103 carries out second ion to described gate electrode and injects, and the ionic type that described second ion injects is opposite with the ionic type that described first ion injects.
Below in conjunction with Fig. 2 to Fig. 6 the transistorized formation method of the intrinsic NMOS of the embodiment of the invention is elaborated.
With reference to figure 1 and Fig. 2, execution in step S101 provides Semiconductor substrate, is formed with gate dielectric layer and gate electrode on the described Semiconductor substrate successively, and the Semiconductor substrate of described gate electrode one side is the source region, and the Semiconductor substrate of opposite side is the drain region.
Specifically comprise in the present embodiment: Semiconductor substrate 100 is provided, and described Semiconductor substrate 100 is the P type semiconductor substrate, and doping content is 1E16/cm
3To 10E16/cm
3, preferred 5E16/cm in the present embodiment
3, its material can be the silicon or the SiGe of monocrystalline, polycrystalline or non crystalline structure, also can be silicon-on-insulator (SOI).The material that perhaps can also comprise other, for example III-V compounds of group such as GaAs.
Be formed with gate dielectric layer 101 on the surface of described Semiconductor substrate 100, its material is a silica, thickness is tens of to the hundreds of dust, its deposition process can be conventional vacuum coating technology, for example boiler tube thermal oxidation, ald (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) technology, present embodiment specifically adopts the boiler tube thermal oxidation technology.
Form the gate electrode layer (not shown) afterwards on gate dielectric layer 101, the material of described gate electrode layer is a polysilicon, and its formation method is low-pressure chemical vapor phase deposition (LPCVD), and the thickness of described gate electrode layer is between hundreds of extremely several thousand dusts.Then described gate electrode layer is carried out graphically, form the transistorized gate electrode 102 of intrinsic NMOS.So far, the device architecture of formation as shown in Figure 2.Above technological process is all consistent with existing intrinsic NMOS transistor process flow.
After described gate electrode 102 forms, described Semiconductor substrate 100 is divided into three parts, wherein first is positioned at gate electrode 102 and the part of gate dielectric layer below 101, be the transistorized channel region of intrinsic NMOS, second and third part for being positioned at the part of described gate electrode 102 both sides, is respectively source region and drain region shown in I district among Fig. 2 and II district, from structure source region and drain region is equivalent, can distinguish source region and drain region but vary in size according to applied voltage polarity in physical circuit.The I district is the source region in the present embodiment, and the II district is the drain region.
In the present embodiment, after forming gate electrode 102, also comprise the injection of light dope ion is carried out in described source region and drain region.As shown in Figure 3, the type that the ion of light dope described in the present embodiment injects is the N type, and dopant ion is selected from phosphorus (P) ion or arsenic (As) ion; The dosage that described light dope ion injects is 1E13/cm
2To 10E13/cm
2, energy is 50KeV to 70KeV, preferred dosage is 5E13/cm in the present embodiment
2, preferred energy is 60KeV.After described light dope ion injection, lightly doped source electrode 103 and lightly doped drain electrode 104 have been formed.Need to prove, before described light dope ion injects, be formed with photoresist figure (not shown) on the surface of described gate electrode 102, the scope that therefore described light dope ion injects does not comprise described gate electrode 102.After described light dope ion injects, described photoresist figure is removed.Need to prove, in other embodiment of the technical program, also can not carry out described light dope ion and inject.
As shown in Figure 4, after described light dope ion injects, form side wall 105 in described gate electrode 101 both sides.Specifically comprise: dielectric layer (not shown) on the gate dielectric layer of described Semiconductor substrate 100, present embodiment is a silica material, generation type can be low-pressure chemical vapor phase deposition (LPCVD), thickness is higher than the height of described gate electrode 102, and described dielectric layer also can be selected oxide layer-silicon nitride-oxide layer (ONO) structure for use.Described dielectric layer is returned (etch back) technology at quarter, form side wall (spacer) 105 in described gate electrode 102 both sides.
In conjunction with Fig. 1 and Fig. 5, execution in step S102 carries out the injection of first ion to described source region and drain region, directly forms source electrode and drain electrode in described Semiconductor substrate.
In the present embodiment at first on described Semiconductor substrate 100 and gate electrode 102 spin coating form first photoresist layer, and be patterned, form the first photoresist figure 106.The described first photoresist figure 106 has defined the shape in source region and drain region, and covers the surface of described gate electrode 102.
Be mask with the described first photoresist figure 106 afterwards, carry out first ion and inject that the ionic type that described first ion injects is the N type, as P ion or As ion, its implantation dosage is 1E15/cm
2To 10E15/cm
2, energy is 50KeV to 70KeV, preferred dosage is 5E15/cm in the present embodiment
2, preferred energy is 60KeV.After described first ion injection, source electrode 103a and drain electrode 104a have been formed respectively.Because the mask effect of the described first photoresist figure 106, the scope that makes described first ion inject does not comprise described gate electrode 102, so does not comprise the ion that first ion injects in the gate electrode 102.In addition, because the barrier effect of side wall 105, the scope that makes described first ion inject does not comprise the semiconductor substrate region of described side wall 105 belows, and this zone has constituted lightly doped LDD (lightly doped drain) structure 103b and 104b.After described first ion injection, in described Semiconductor substrate 100, directly formed source electrode 103a and drain electrode 104a, its doping content is 1E19/cm
3To 10E19/cm
3After described first ion injects, remove the described first photoresist figure 106 by ashing (ashing), expose the surface of described gate electrode 102.
Need to prove, described source electrode 103a and drain electrode 104a directly are formed in the Semiconductor substrate 100, the raceway groove that refers to the source electrode 103a of intrinsic MOS transistor and drain between 104a, the source/drain all is formed directly in the Semiconductor substrate, do not form dopant well in the Semiconductor substrate, the source electrode that is formed at the MOS transistor in the well region of doping with routine is different with drain electrode.
What particularly point out is, though part technical scheme of the prior art is as in the relevant patent application and the not mentioned well region that forms in Semiconductor substrate, but those skilled in the art can know the well region that contains doping in its substrate by inference according to conventional knowledge, only be because the improvement of its scheme and dopant well or substrate are irrelevant, so do not mention especially, so they are different with the forming process that forms the intrinsic MOS transistor.
In conjunction with Fig. 1 and Fig. 6, execution in step S103 carries out second ion to described gate electrode and injects, and the ionic type that described second ion injects is opposite with the ionic type that described first ion injects.
In the present embodiment at first on the surface of described Semiconductor substrate 100 and gate electrode 102 spin coating form second photoresist layer, and patterned, form the second photoresist figure 107.The described second photoresist figure 107 has defined the zone of gate electrode 102, and covers described source electrode 103a and drain electrode 104a.
Be mask with the described second photoresist figure 107 afterwards, carry out second ion and inject.The ionic type that described second ion injects is the P type, and as boron (B) ion or indium (In) ion, its implantation dosage is 1E15/cm
2To 10E15/cm
2, energy is 30KeV to 50KeV, preferred dosage is 5E15/cm in the present embodiment
2, preferred energy is 40KeV.Because the mask effect of the described second photoresist figure 107, the scope that makes described second ion inject do not comprise described source electrode 103a and drain electrode 104a, so only comprise the ion that second ion injects in the gate electrode 102.After described second ion injection, the doping content of described gate electrode 102 is 1E19/cm
3To 10E19/cm
3
After described second ion injects, remove the described second photoresist figure 107 by ashing (ashing), expose the semiconductor substrate surface in described source electrode 103a and drain electrode 104a zone.
So far, the transistorized structure of intrinsic NMOS that present embodiment forms comprises: Semiconductor substrate 100 as shown in Figure 7; Gate dielectric layer 101 is formed on the described Semiconductor substrate 100; Gate electrode 102 is formed on the described gate dielectric layer 101; Source electrode 103a and drain electrode 104a directly are formed at respectively in the Semiconductor substrate 100 of described gate electrode 102 and gate dielectric layer 101 both sides.The intrinsic NMOS transistor that present embodiment forms also comprises the LDD structure 103b and the 104b of source electrode and drain electrode.Structure shown in Figure 7 is the intrinsic NMOS transistor in the present embodiment, and the doping type of described Semiconductor substrate 100 is the P type, and doping content is 1E16/cm
3To 10E16/cm
3The doping type of described source electrode 103a and drain electrode 104a is the N type, and doping content is 1E19/cm
3To 10E19/cm
3The doping type of described gate electrode 102 is the P type, and doping content is 1E19/cm
3To 10E19/cm
3
Technique scheme is in forming the transistorized process of intrinsic NMOS, by dissimilar ion implantation process, make gate electrode opposite with the doping type of source electrode and drain electrode, being specially source/drain in this embodiment is that the N type mixes, and gate electrode mixes for the P type, therefore, the work function difference between transistorized gate electrode of the intrinsic NMOS of formation and Semiconductor substrate is bigger, thereby has increased the transistorized threshold voltage of intrinsic NMOS that forms.Find that through inventor's measurement Research the transistorized threshold voltage of intrinsic NMOS that the foregoing description forms is approximately 1V, much larger than 0, makes it become enhancement transistor, is normal off (already off) state.
Be to be example to form the intrinsic NMOS transistor in the foregoing description, the technical program can also be used to form intrinsic PMOS transistor.The transistorized structure of intrinsic PMOS of its concrete forming process and formation and intrinsic NMOS transistor basically identical, difference is that the transistorized Semiconductor substrate type of intrinsic PMOS is the N type, and source/drain electrode doping type is the P type, and the gate electrode doping type is the N type.
The above is two specific embodiments of the present invention, forms intrinsic NMOS transistor and intrinsic PMOS transistor respectively.By the ion injection is carried out in source/drain electrode and gate electrode respectively, make that the doping type of gate electrode is opposite, identical with Semiconductor substrate with source/drain electrode, thereby increased the work function difference between gate electrode and the Semiconductor substrate, improved the threshold voltage of intrinsic MOS transistor.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (18)
1. intrinsic MOS transistor comprises:
Semiconductor substrate;
Gate dielectric layer is formed on the described Semiconductor substrate;
Gate electrode is formed on the described gate dielectric layer;
Source electrode and drain electrode directly are formed in the Semiconductor substrate of described gate electrode both sides respectively;
It is characterized in that the doping type of described gate electrode is opposite with the doping type of source electrode and drain electrode.
2. intrinsic MOS transistor according to claim 1 is characterized in that, the doping type of described Semiconductor substrate is a P type ion, and the doping type of described source electrode and drain electrode is a N type ion, and the doping type of described gate electrode is a P type ion.
3. intrinsic MOS transistor according to claim 1 is characterized in that, the doping type of described Semiconductor substrate is a N type ion, and the doping type of described source electrode and drain electrode is a P type ion, and the doping type of described gate electrode is a N type ion.
4. intrinsic MOS transistor according to claim 1 is characterized in that, the doping content scope of described Semiconductor substrate is 1E16/cm
3To 10E16/cm
3
5. intrinsic MOS transistor according to claim 1 is characterized in that, the doping content scope of described source electrode and drain electrode is 1E19/cm
3To 10E19/cm
3
6. intrinsic MOS transistor according to claim 1 is characterized in that, the doping content scope of described gate electrode is 1E19/cm
3To 10E19/cm
3
7. intrinsic MOS transistor according to claim 1 is characterized in that, also comprises side wall, is formed on the Semiconductor substrate of described gate electrode and gate dielectric layer both sides.
8. the formation method of an intrinsic MOS transistor is characterized in that, comprising:
Semiconductor substrate is provided, is formed with gate dielectric layer and gate electrode on the described Semiconductor substrate successively, the Semiconductor substrate of described gate electrode one side is the source region, and the Semiconductor substrate of opposite side is the drain region;
The injection of first ion is carried out in described source region and drain region, in described Semiconductor substrate, directly formed source electrode and drain electrode;
Described gate electrode is carried out second ion inject, the ionic type that described second ion injects is opposite with the ionic type that described first ion injects.
9. the formation method of intrinsic MOS transistor according to claim 8 is characterized in that, the doping type of described Semiconductor substrate is a P type ion, and the ionic type that described first ion injects is the N type, and the ionic type that described second ion injects is the P type.
10. the formation method of intrinsic MOS transistor according to claim 9 is characterized in that, the ion that described first ion injects is P ion or As ion, and the ion that described second ion injects is B ion or In ion.
11. the formation method of intrinsic MOS transistor according to claim 8 is characterized in that, the doping type of described Semiconductor substrate is a N type ion, and the ionic type that described first ion injects is the P type, and the ionic type that described second ion injects is the N type.
12. the formation method of intrinsic MOS transistor according to claim 11 is characterized in that, the ion that described first ion injects is B ion or In ion, and the ion that described second ion injects is P ion or As ion.
13. the formation method of intrinsic MOS transistor according to claim 8 is characterized in that, the doping content scope of described Semiconductor substrate is 1E16/cm
3To 10E16/cm
3
14. the formation method of intrinsic MOS transistor according to claim 8 is characterized in that, the dosage that described first ion injects is 1E15/cm
2To 10E15/cm
2, energy is 50KeV to 70KeV.
15. the formation method of intrinsic MOS transistor according to claim 8 is characterized in that, the dosage that described second ion injects is 1E15/cm
2To 10E15/cm
2, energy is 30KeV to 50KeV.
16. the formation method of intrinsic MOS transistor according to claim 8, it is characterized in that, described source region and drain region are being carried out also comprising before first ion injects: the injection of light dope ion is carried out in described source region and drain region, formed lightly doped source electrode and drain electrode.
17. the formation method of intrinsic MOS transistor according to claim 16 is characterized in that, the dosage that described light dope ion injects is 1E13/cm
2To 10E13/cm
2, energy is 50KeV to 70KeV.
18. the formation method of intrinsic MOS transistor according to claim 16, it is characterized in that, described source region and drain region are carried out the light dope ion inject after and carry out first ion and also comprise before injecting: at the both sides of described gate electrode and gate dielectric layer formation side wall.
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| CN113783557A (en) * | 2021-09-27 | 2021-12-10 | 普冉半导体(上海)股份有限公司 | Chip power-on reset circuit |
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| CN1146627A (en) * | 1995-05-09 | 1997-04-02 | 现代电子产业株式会社 | Method for making transistor of semiconductor device |
| CN1359156A (en) * | 2000-09-01 | 2002-07-17 | 精工电子有限公司 | CMOS semiconductor device and making method |
| CN1881600A (en) * | 2004-11-25 | 2006-12-20 | 三星电子株式会社 | CMOS image sensor |
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