CN102136462A - General output and input unit as well as related device and method thereof - Google Patents
General output and input unit as well as related device and method thereof Download PDFInfo
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- CN102136462A CN102136462A CN2010101189614A CN201010118961A CN102136462A CN 102136462 A CN102136462 A CN 102136462A CN 2010101189614 A CN2010101189614 A CN 2010101189614A CN 201010118961 A CN201010118961 A CN 201010118961A CN 102136462 A CN102136462 A CN 102136462A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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Abstract
The invention provides a general output and input unit as well as a related device and a method thereof, which can be applied to a crystalline grain/ chip and an integrated circuit. In the embodiment of the invention, each general output and input unit is provided with a power joint pad opening and a plurality of signal joint pad openings so as to realize different functions. According to the function requirement of each general output and input unit, the power joint pad of each general output and input unit is selectively connected with a corresponding electrical conductor and is coupled with a certain voltage by the electrical conductor; and each signal joint pad opening is respectively and selectively connected with a corresponding signal conductor to transfer the signal by the signal conductor.
Description
Technical field
The present invention is about a kind of general output/input unit and relevant apparatus and method, refers to especially a kind ofly have an electric power connection pad opening and at least one signal bonding pad opening and can utilize the selectivity of these connection pad openings to set and be combined into the general output/input unit and the apparatus and method of using this general output/input unit of difference in functionality.
Background technology
Chip (crystal grain) is the most important hardware foundation of advanced information society with integrated circuit.In order to make chip and obtain the required electric power of running with other circuit (similarly being other crystal grain/chip, integrated circuit and/or printed circuit board (PCB)) switching signal, in the chip a plurality of output/input units can be set, form the interface that chip connects outward.
In the prior art, each output/input unit in the chip has single connection pad opening, to be connected to other outer circuit of chip by corresponding signal conductor or electric lead (similarly being routing), and each output/input unit only can be carried out a kind of default function, comes the various functions of executive's interface respectively so chip needs the output/input unit of several different frameworks.For example, the function of some output/input unit just is simple signal driving/output, some output/input unit then can be carried out signal and drive and the signal reception, also has some output/input units then to be used for being coupled predetermined voltage (for example being operating voltage or ground connection) specially so that chip can be obtained the required electric power of running in addition.
Except the various different output/input units that differentiate because of function is different, also Chang Yinwei will reduce the size of chip interface and configuration (staggered IO) is gone in the output that the connection pad opening of adjacent output/input unit is arranged in intermesh in the prior art, and this further makes the diverse location output/input unit also must have different frameworks.In other words, even the function of two output/input units is identical, but for the connection pad opening of these two output/input units is intermeshed, the framework of these two output/input units also can be different.When design one chip, more than all factors all can make the technology of putting automatically and winding the line be difficult to be applied to this output/input unit, can only be difficult to make circuit to arrange optimization manually to carry out putting and winding the line of output/input unit, also increase the time and the cost of chip design.
And, the elasticity on the output/input unit of aforementioned this single connection pad opening/simple function also is short of design and uses; In the time will realizing the chip of distinct interface, all to make customized time and cost be difficult to reduce at the corresponding output/input unit of the demand redesign/arrangement of interface configuration at every turn.In addition, the output/input unit of prior art also can't effectively increase the aggregation degree that the connection pad opening is arranged, and is difficult to be used in the limited application of connection pad.
Summary of the invention
Therefore, purpose of the present invention promptly is will propose a kind ofly can be combined into difference in functionality and effectively increase the general output/input unit of connection pad opening aggregation degree and chip/integrated circuit and the method for using this general output/input unit with the same architecture selectivity.
According to an aspect of the present invention, provide a kind of general output/input unit, this general output/input unit is provided with that an electric power connection pad opening, a plurality of signal bonding pad opening, one are coupled to the electric power block of electric power connection pad opening, block is gone in a plurality of output that is respectively coupled to a respective signal connection pad opening, and a plurality ofly is respectively coupled to the application block that block is gone in a corresponding output; Utilize the setting of these connection pad openings and corresponding circuits block, the present invention is that the general output/input unit of available same architecture is combined into different functions.Wherein, electric power connection pad opening can be complied with the electric lead of functionally selective ground connection one correspondence of being desired to be coupled to a predetermined voltage (for example being operating voltage or ground connection) by this electric lead; The signal conductor that each signal bonding pad opening also can optionally connect a correspondence according to functional requirement with undertaken by this signal conductor the signal transmission (its can comprise signal drive with signal receive among both at least one of them).
In one embodiment of this invention, the electric power block in each general output/input unit is provided with various electric power coilings, similarly is electric power path (power rail) or the like; When each general output/input unit adjoined each other with the realization chip interface, the electric power block of each general output/input unit can couple mutually by the electric power coiling, with transferring electric power between each general output/input unit.In addition, in individual other general output/input unit, its electric power block is coupled to electric power connection pad opening, also electric power transfer can be exported into block and each to each and be used block.Under this kind framework, the electric power connection pad opening of some first general output/input units is coupled to predetermined voltage (operating voltage or ground connection) by corresponding electric lead, this first general output/input unit just can reach the function of transmit outer electric power, its electric power block not only can be with the electric power transfer to the first of operating voltage/ground connection each circuit blocks of general output/input unit itself, can also make each circuit blocks (output is gone into block and used block) in these second general output/input units can obtain electric power with electric power transfer to other second general output/input unit that is not coupled to operating voltage/ground connection by corresponding electric power connection pad opening.
In the general output/input unit of the present invention, a plurality of outputs that are respectively coupled to respective signal connection pad opening are gone into block and can be distinguished independent controlled to determine its function.In one embodiment, each exports into block is independent respectively controlledly whether be enabled with decision, and the output that is enabled go into block can be controlled with optionally carry out signal drive in receiving with signal at least one of them.
For example, the general output/input unit of the present invention can be applicable to the memory interface of a memory control chip; Setting makes an output in the general output/input unit go into the controlled execution signal of block and drives and the signal reception, just can export into signal bonding pad opening transmitting-receiving (receiving/send) data (data) signal or data of block correspondence from this and indicate (data strobe) signal.Setting make same general output/input unit another export that to go into block into block or the output of another general output/input unit controlled and carry out signal and drive, just can export and export a memory clock pulse (clock), an address (address) signal or into the connection pad opening of block correspondence and instruct (command) signal from this.Thus, the general output/input unit of the present invention just can realize out that different output goes into function with the same circuits framework.Because it is independent separately controlled that a plurality of signal bonding pad openings in each general output/input unit are gone into block with corresponding output, as long as can be, even also can realize out that with a general output/input unit multiple signal exports into function simultaneously by appropriate signals lead connection; For example, same general output/input unit both can be by a certain signal bonding pad opening receiving and transmitting data signals, again can be from another signal bonding pad opening OPADD signal.In other words, the general output/input unit of the present invention has high design and uses elasticity.
Provide the chip of the above-mentioned general output/input unit of a kind of the present invention of application according to a further aspect of the invention.Except a plurality of general output/input units, this chip also is provided with a Control Engine, make in each general output/input unit each signal bonding pad opening can according to the setting of this Control Engine carry out the signal transmission (similarly be signal drive with signal receive among both at least one of them).More particularly, whether can be respectively independent each output of setting each general output/input unit of this Control Engine is gone into block and is enabled to set it, and the output that is enabled go into control that block (and use block) also can accept Control Engine with optionally carry out signal drive in receiving with signal at least one of them, and can optionally set each output and go into running of block (and even using block) and be configured in response to different environment of operation and functional requirement, for example be different speed/frequency, different signal driving forces and different operating voltages.
For example, chip of the present invention can be a memory control chip, each general output/input unit is to be applied to a memory interface, and Control Engine just can make at least one general output/input unit at least one export to drive with signal into the controlled execution signal of block and receives, and receives and dispatches data (data) signal or data indication (data strobe) signal to export by this into the connection pad opening of block correspondence.And that this Control Engine also can make at least one general output/input unit at least one export into block is controlled and carry out signal and drive, and exports a memory clock pulse (clock), an address (address) signal or instruction (command) signal with the connection pad opening of going into the block correspondence from output.
In an embodiment of chip of the present invention, Control Engine is to carry out a program code when chip enable, and sets each signal bonding pad opening in each general output/input unit respectively according to execution result.
Provide integrated circuit after a kind of encapsulation according to another aspect of the invention.This integrated circuit includes an aforementioned chip of the present invention and a substrate.In embodiments of the present invention, this substrate can be a soldered ball trellis array (BallGrid Array, substrate BGA) or one or four side pin flat packaging (Quad Flat Package, substrates QFP).In addition, this integrated circuit also can be with substrate system in package (SiP in package shape by a plurality of chips, Silicon in Package) integrated circuit also can promote the use between chip and chip so the present invention is connected framework at chip and lead between substrate.
Just as discussed earlier, the present invention can make the general output/input unit of same architecture/identical type be applied to different functional requirements by the setting control of Control Engine.The most basic application is to select one to be coupled to substrate with lead (electric lead/signal conductor) in the electric power connection pad opening of each general output/input unit and signal bonding pad opening.For example, a certain general output/input unit only is coupled to substrate by its electric power connection pad opening and introduces operating voltage/ground connection, and each signal bonding pad opening of this general output/input unit just is not attached to substrate, and the also controlled anergy of block/application block is gone in the output of each signal bonding pad opening correspondence.In like manner, another general output/input unit then can be coupled to substrate to carry out the signal transmission in a signal bonding pad opening, and electric power connection pad opening and other signal bonding pad opening then are coupled to substrate no longer separately.
In further Application Example, as long as the arrangement of signal conductor is suitable, two signal bonding pad openings of same general output/input unit can be respectively signal conductor by mutually insulated be connected on two independent signal pin positions of substrate, make same general output/input unit can realize simultaneously two kinds different and independently signal export into function.The electric power connection pad opening of this general output/input unit then can be coupled to substrate.
In the another embodiment of integrated circuit of the present invention, this substrate includes an electric power ring (ring) and a signal pin (pin), and being electric lead by correspondence, the electric power connection pad opening that has a general output/input unit in the chip of the present invention at least is connected to aforementioned electric power ring, and a signal bonding pad opening of same general output/input unit also is connected to aforementioned signal pin by the signal conductor of correspondence, make this general output/input unit can not only realize that signal exports into function, also external power can be transferred to chip.
Provide a kind of method of design one chip according to a further aspect of the present invention, its key step includes:
Purchase the identical general output/input unit of same kind of a plurality of circuit structures, each general output/input unit can be controlled respectively to realize different functions, general output/input unit of the present invention as described above just;
Carry out one with a computer and put automatically and wind the line (automatic placing and routing), to determine this position and the coiling of a plurality of general output/input units in chip;
In the chip internal circuit, arrange built-in (numeral) Control Engine to set the function of each general output/input unit; For example be that the block that respectively reads in that makes Control Engine be able to according to the function of each general output/input unit each general output/input unit of activation optionally receives to carry out signal; And make Control Engine can be according to the function of each general output/input unit optionally the block that respectively writes out of each general output/input unit of activation drive to carry out signal; And
Arrange one to read in application circuit in the chip internal circuit, what be coupled to each general output/input unit respectively reads in block to handle the signal that respectively reads in the block transmission; Also can arrange other auxiliary circuit in the chip internal circuit, similarly be phase-locked loop or the like.
As discussed earlier, because the present invention can export into function with identical different electric power function and the signals of general output/input unit realization of circuit framework, so design of the present invention is high with application elasticity, also can significantly simplify the design cycle of chip, make general output/input unit put with coiling be able to computer and Software tool automation finish.
In order to enable further to understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing, yet accompanying drawing only provide with reference to and explanation, be not to be used for the present invention is limited.
Description of drawings
Can obtain more deep understanding by following to the present application in conjunction with the accompanying drawings to the detailed description of preferred embodiment of the present invention, wherein:
Fig. 1 applies to the schematic diagram of chip for the general output/input unit of the present invention.
The different embodiment of the general output/input unit of the present invention in Fig. 2 and Fig. 3 difference schematic diagram 1.
What Fig. 4 to Fig. 6 illustrated is the various Application Examples of Fig. 1 chips.
That Fig. 7 and Fig. 8 illustrate is the various embodiment that Fig. 1 chips is set.
What Fig. 9 illustrated is to use the flow implementation example that the general output/input unit of the present invention carries out chip design.
Embodiment
Please refer to Fig. 1; That Fig. 1 illustrates is the embodiment that the general output/input unit of the present invention is applied to the present invention's one chip 10.In this schematic embodiment, general output/input unit IO of the present invention (0), IO (1) ..., IO (n) is to IO (N-1), and general output/input unit IO (N) promptly is used to realize the outer connector MI (0) and MI (1) of chip 10 respectively to IO (M); The internal circuit 12 of chip 10 is exactly the circuit-switched signals of and chip exterior next by these interfaces MI (0), MI (1) or the like and obtains electric power.With general output/input unit IO (n) is that representative illustrates, is provided with an electric power connection pad opening PG (n) and two signal bonding pad opening Fa (n) and Fb (n) among each general output/input unit IO (n) of the present invention.Wherein, the alternative electric lead of a correspondence that connects of electric power connection pad opening PG (n) is to be coupled to a predetermined voltage (i.e. a working voltage source or ground connection) by electric lead; Each signal bonding pad opening Fa (n) also can distinguish with Fb (n) and optionally connects a corresponding signal conductor.
Except a plurality of general output/input units, also be provided with a Control Engine CE and in the chip 10 and read in application circuit MISC.Control Engine CE can utilize setting signal group CS (n) to set the function of corresponding general output/input unit IO (n), each signal bonding pad opening Fa (n) that makes each general output/input unit IO (n) and Fb (n) can be individually independently according to setting carry out signal drive (signal output) and signal reception at least one of them.For further specifying framework and the operation situation of the general output/input unit IO of the present invention (n), please refer to Fig. 2 and Fig. 3; That Fig. 2 and Fig. 3 illustrate is the embodiment of the general output/input unit IO of the present invention (n).
Just as shown in Figure 1, in the embodiment of Fig. 2, be provided with an electric power connection pad opening PG (n) and a plurality of signal bonding pad opening Fa (n) and Fb (n) among the general output/input unit IO of the present invention (n).Electric power connection pad opening PG (n) can comply with the functionally selective ground of being desired and connect the electric lead of a correspondence to be coupled to operating voltage or ground connection by this electric lead; The signal conductor that each signal bonding pad opening Fa (n)/Fb (n) also can optionally connect a correspondence according to functional requirement with carry out signal by signal conductor and drive or signal receives at least one of them.
Can be for the function that makes each connection pad opening by independent setting respectively, each connection pad opening PG (n) has corresponding output/input circuit separately with Fa (n), Fb (n).Concerning electric power connection pad opening PG (n), promptly be provided with an electric power block pb who is coupled to electric power connection pad opening among the general output/input unit IO (n).At signal bonding pad opening Fa (n) and Fb (n), general output/input unit IO (n) then is respectively equipped with output and goes into block ioa and iob, and uses block ma and mb.Each output is gone into block ioa/iob and is respectively coupled to corresponding signal bonding pad opening Fa (n)/Fb (n), and each is used block ma/mb and then is respectively coupled to corresponding output and goes into block ioa/iob.Carry out different settings at these connection pad openings with the corresponding circuits block, the present invention is that the general output/input unit of available same architecture is combined into different functions.
In one embodiment of this invention, can be provided with various electric power coilings corresponding to the electric power block pb of electric power connection pad opening PG (n), similarly be electric power path (power rail) or the like; When each general output/input unit adjoins each other with the realization chip interface (the general output/input unit IO (0), the IO (1) that similarly are adjacency among Fig. 1 interface MI (0) are to IO (N-1)), the electric power block pb of each general output/input unit can couple mutually by the electric power coiling, with transferring electric power between each general output/input unit; Perhaps, the general output/input unit of the present invention also can with the circuit unit of other kind (similarly being the fixing circuit unit of function) together in abutting connection with arranging; And the coiling of the electric power of the general output/input unit of the present invention also can couple with transferring electric power mutually with the electric power coiling of these circuit units.In addition, in individual other general output/input unit IO (n), its electric power block pb not only is coupled to electric power connection pad opening PG (n), also electric power transfer can be exported into block ioa/iob and each to each and be used block ma/mb.Under this kind framework, the electric power connection pad opening PG (n) of some general output/input unit IO (n) is coupled to operating voltage or ground connection by corresponding electric lead, this general output/input unit IO (n) just can bring into play the function of transmit outer electric power, its electric power block pb not only can be with electric power transfer each circuit blocks to general output/input unit IO (n) itself, can also for example be the general output/input unit IO (n-1) of an adjacency with electric power transfer to other general output/input unit that is not coupled to operating voltage/ground connection by electric power connection pad opening.So, even the electric power connection pad opening PG (n-1) of general output/input unit IO (n-1) does not connect any electric lead, each circuit blocks among the general output/input unit IO (n-1) (output is gone into block and used block) still can obtain electric power.Except electric power coiling, also can be provided with among the electric power block pb of the present invention ESD protection circuit and electric power adjuster (power regulator) or other power conversion circuit at least one of them.In setting signal group CS (n), setting signal CSp (n) promptly is used for setting the function of electric power block pb.
On the other hand, in the general output/input unit IO of the present invention (n), the output that is coupled to respective signal connection pad opening Fa (n)/Fb (n) is gone into block ioa/iob and then can be distinguished independent controlled to determine its function; Use block ma/mb and then be intended for the corresponding interface of exporting between block ioa/iob and chip internal circuit 12 (Fig. 1).In one embodiment, each is exported into block ioa/iob is independent respectively controlled to determine whether be enabled, and the output that is enabled go into block can be controlled with optionally carry out signal drive in receiving with signal at least one of them, and can optionally set each output and go into running of block (and even using block) and be configured in response to different environment of operation and functional requirement, for example be different speed/frequency, different signal driving forces and different operating voltages.In setting signal group CS (n), setting signal CSa (n) promptly is used for setting/control output and goes into the function of block ioa (and using block ma); Setting signal CSb (n) then is used for setting/controlling output and goes into the function that block iob/ uses block mb.Setting signal CSa (n)/CSb (n) can be respectively a digital signal that list is one or more.
In general output/input unit IO (n), output is gone into to include respectively among the block ioa/iob output and is gone into to read in sub-block iora/iorb and and export and go into to write out sub-block iowa/iowb; Sub-block iora and iowa are controlled by setting signal CSa (n) respectively and can be by optionally activation or anergies.Concerning signal bonding pad opening Fa (n), go into to read in sub-block iora when being set signal CSa (n) and setting activation when output, block ioa is gone in output just can carry out the signal reception; And when output was gone into to write out sub-block iowa and is enabled, corresponding output was gone into block ioa and then can be carried out signal and drive (output).In like manner, whether signal bonding pad opening Fb (n) can carry out the function that signal driving/signal receives with sub-block iowb/iorb, is then set by setting signal CSb (n).
Each sub-block of block ioa/iob is gone in collocation output, and each is used and also is respectively arranged with one among the block ma/mb and uses and read in sub-block mra/mrb and write out sub-block mwa/mwb with an application.Application is read in sub-block mra/mrb and is respectively coupled to corresponding output and goes into to read in sub-block iora/iorb, to go into to read in the interface of sub-block as output; Use and to write out sub-block mwa/mwb and then be respectively coupled to corresponding output and go into to write out sub-block iowa/iowb, to go into to write out the interface of sub-block as output.Output is gone into to read in sub-block iora/iorb, output and is gone into to write out sub-block iowa/iowb, uses and to read in sub-block mra/mrb and application and write out sub-block mwa/mwb and all can be controlled by Control Engine CE (Fig. 1) and set its function mode and function.
With signal bonding pad opening Fa (n) is example, uses to write out to be provided with level shifter circuit such as (levelshifter) among the sub-block mwa, exports to go into to write out among the sub-block iowa then can be provided with the drive circuit that operates on high working voltage.When the signal driving function of signal bonding pad opening Fa (n) is set activation, the signal (just writing out signal Swa (n)) that is sent by chip internal circuit 12 (operating on low-work voltage) can transfer to output by the conversion (as level deviation) that sub-block mwa is write out in application and go into to write out sub-block iowa, and output goes into to write out sub-block iowa just can write out application the signal bonding pad opening Fa (n) that signal that sub-block mwa transmits is driven into correspondence.
In like manner, output is gone into to read in sub-block iora and can be provided with the circuit that buffer circuit and/or Schmidt trigger (Schmitttrigger) etc. operate on high working voltage.When the signal receiving function of signal bonding pad opening Fa (n) is enabled, the signal that is transmitted outward by chip can be gone into to read in sub-block iora by output by the transmission of signal bonding pad opening Fa (n) and be received, and converts 12 signals that can receive of chip internal circuit (just reading in signal Sra (n)) to read in the level adjustment of sub-block mra by application after.That is to say that the output of signal bonding pad opening Fa (n) is gone into to read in sub-block iora and read in sub-block mra one-tenth one capable of being combined with corresponding application and read in block, receives with the signal of realizing signal bonding pad opening Fa (n); And output is gone into to write out sub-block iowa and corresponding application and is write out sub-block mwa and can regard one as and write out block, with the signal driving (output) of realization signal bonding pad opening Fa (n).
According to identical circuit framework and operation principles, when the signal of signal bonding pad opening Fb (n) drives function and is enabled, just can write out sub-block mwb and output and go into to write out the running of sub-block iowb and the signal Swb (n) that writes out of inside chip is sent by application.If the signal receiving function of signal bonding pad opening Fb (n) also is enabled, the signal that signal bonding pad opening Fb (n) is received just can be gone into to read in sub-block iorb by output and be read in the running of sub-block mrb and be back to internal circuit 12 with the form of reading in signal Srb (n) with application.Signal bonding pad opening Fa (n) and Fb's (n) reads in signal Sra (n) and Srb (n) and can form the parallel sets of signals Sr (n) that reads in; Writing out signal Swa (n) and Swb (n) then can comprehensively be considered as one and write out sets of signals Sw (n).
In the embodiment of Fig. 2, the present invention goes into block ioa with the pairing output of signal bonding pad opening Fa (n) to be arranged between signal bonding pad opening Fa (n) and the Fb (n) with using block ma, the output of signal bonding pad opening Fb (n) is gone into block iob with using the opposite side that block mb then is arranged at signal bonding pad opening Fb (n), just away from that side of electric power connection pad opening PG (n).
The embodiment of continuity Fig. 2, in the embodiments of figure 3, the element with same numeral is also followed identical operation principles, repeats no more in this.But, in the embodiments of figure 3, it is to be arranged at together between corresponding the signal bonding pad opening Fa (n) and Fb (n) with iob that block ioa is gone in two outputs, the opposite side that the pairing application block of block ioa/iob ma/mb then is arranged at this two signal bonding pad opening Fa (n)/Fb (n) is together gone in output, just away from that side of electric power connection pad opening PG (n).In general, when layout designs, block is gone in output will follow certain design rule (design rule) usually with the placement position of using block; Under the design rule of some technology, block is gone in output and the application area interblock must have certain spacing distance, so in the embodiments of figure 3, output is gone into block ioa/iob and used block ma/mb group's arrangement respectively, can save the clearance space that block and application area interblock are gone in output.In addition, under some technology, some active element (active area) can directly be arranged under the connection pad opening, and the general output/input unit of the present invention also can be used this technology.
No matter be that embodiment among Fig. 2 or Fig. 3 all can be applicable to the chip 10 among Fig. 1.Please once again with reference to figure 1.Discussed just as the front, in the internal circuit 12 of chip 10 of the present invention, Control Engine CE promptly is a function of setting each general output/input unit IO (n) with setting signal group CS (n); And the signal that internal circuit 12 will send is promptly integrated by Control Engine CE and is assigned as each and writes out sets of signals Sw (n), to drive output by suitable general output/input unit IO (n).On the other hand, receiving the sets of signals Sr (n) that reads in that returns by each general output/input unit IO (n) then can be by reading in application circuit MISC reception.Each of reading in that application circuit MISC is coupled to each general output/input unit IO (n) used and to be read in sub-block mra/mrb (Fig. 2, Fig. 3), is used for handling by what sub-block mra/mrb transmission was read in each application reading in signal Sra (n)/Srb (n).For example, read in to include among the application circuit MISC and fasten lock circuit, read in the signal of sub-block and form corresponding digital signal, the internal circuit 12 of chip can be understood with each application of lock of taking a sample/fasten.In addition, read in and the serial/parallel change-over circuit also can be set among the application circuit MISC (SERDES SErializer/DESerializer), is converted to digital serial signal with the parallel and column signal (reading in signal) with the different connecting pad opening.Also can arrange other auxiliary circuit in the internal circuit 12, similarly be phase-locked loop or the like.
In the embodiment in figure 1, the electric power connection pad opening PG (n) of each general output/input unit IO (n) all is arranged in same hurdle along a direction dir1 with signal bonding pad opening Fa (n) and Fb (n); This direction dir1 is parallel to the side of general output/input unit IO (n), make general output/input unit IO (n) can be along direction dir2 and with other circuit unit (similarly be that general output/input unit IO (0) is to IO (N-1), or the circuit unit of other kind) is arranged as row (row) together, wherein, direction dir1 is vertical mutually with direction dir2.In addition, the electric power connection pad opening of adjacent general output/input unit is also aligned with each other along direction dir2; Jointly, the adjacent signals connection pad opening of adjacent general output/input unit equally also aligns along direction dir2.For example, general output/input unit IO (0) is to the electric power connection pad opening PG (0) of IO (N-1) arrangement of aliging to PG (N-1) along direction dir2, and each signal bonding pad opening Fa (0) also aligns along direction dir2 to Fa (N-1).Because the general output/input unit IO of the present invention (n) has gathered the connection pad opening that a plurality of (3) have standalone feature in same hurdle,, save required layout area and the size of chip so can promote the aggregation degree of connection pad opening effectively.
On the other hand, between each connection pad opening PG (n), the Fa (n) and Fb (n) that become the hurdle to arrange, each signal bonding pad opening Fa (n) and Fb (n) all are arranged at the same side of this electric power connection pad opening PG (n), the opposite opposite side that makes electric power connection pad opening PG (n) is signalization connection pad opening not, just electric power connection pad opening PG (n) is arranged in the outermost of general output/input unit IO (n), becomes in each connection pad opening connection pad opening near chip edge S.
Generally, in chip 10 of the present invention, because can distinguishing each output of independently setting each general output/input unit IO (n), Control Engine CE goes into block ioa/iob to determine respectively whether the function that its signal drives and signal receives is enabled, so application elasticity of the present invention is very big.For example, chip 10 can be a memory control chip, be used for controlling, the access one outer memory that connects, and each the general output/input unit IO (n) in the chip 10 can realize the memory interface of this memory control chip.
In order to control/access memory, the memory control chip should be wanted and can send memory clock pulse (clock), address (address) signal and instruction (command) signal to memory, want to cooperate the transmission of data indication (datastrobe) signal and to memory dateout (data) signal, and data index signal that can reception memorizer receives data-signal to cooperate to memory.When realizing the memory control chip with the technology of the present invention, the present invention just can set an output that makes among the general output/input unit IO (n) and go into controlled execution signal driving of block ioa and signal reception, so that receive and dispatch (receiving/send) data-signal or data index signal from the signal bonding pad opening Fa (n) of correspondence.Setting make general output/input unit IO (n) another export that to go into block ioa/iob into block iob or the output of another general output/input unit IO (i) controlled and carry out signal and drive, just can export signal bonding pad opening output storage clock pulse, address signal or command signal from each into the block correspondence.
In other words, the present invention can realize out that different output goes into function with each identical general output/input unit of circuit framework.Because it is independent separately controlled that a plurality of signal bonding pad openings in each general output/input unit are gone into block with corresponding output, as long as can connect by the appropriate signals lead, even also can realize out that with a general output/input unit multiple signal exports into function simultaneously, for example same general output/input unit both can be by a signal bonding pad opening receiving and transmitting data signals, again can be from another signal bonding pad opening OPADD signal.Hence one can see that, and the general output/input unit of the present invention has high design and uses elasticity.
Please refer to Fig. 4 and Fig. 5; This two figure signal be chip 10 collocation one substrates 20 of the present invention and realize the Application Example of encapsulation back integrated circuit.Substrate 20 can be soldered ball trellis array (Ball Grid Array, substrate BGA) or one or four side pin flat packaging (Quad Flat Package, substrates QFP).In addition, this integrated circuit also can be by the system in package (SiP of a plurality of chips with the substrate encapsulated moulding, Silicon inPackage) so integrated circuit is following about respectively being connected framework embodiment and all can promoting the framework that is connected that is in use between chip and the chip between chip of the present invention and substrate.
Just as discussed earlier, the present invention can make the general output/input unit of same architecture be satisfied different functional requirements by the setting control of Control Engine CE (Fig. 1).The most basic application is to select one to be coupled to substrate 20 with electric lead or signal conductor (similarly being routing) in the electric power connection pad opening PG (n) of each general output/input unit IO (n) and signal bonding pad opening Fa (n)/Fb (n).That Fig. 4 illustrates promptly is this kind embodiment; As shown in the figure, general output/input unit IO (k) only is coupled to the electric power pin position PP (k) of substrate 20 to introduce operating voltage by its electric power connection pad opening PG (k); And other each signal bonding pad opening of this general output/input unit IO (k) all is not coupled to substrate 20 separately, and the also controlled anergy of block/application block is gone in the output of each signal bonding pad opening correspondence.The signal pin SP (i) that another general output/input unit IO (i) then is coupled to substrate 20 in single signal bonding pad opening Fa (i) is carrying out handshaking, and this electric power connection pad opening and other signal bonding pad opening once general output/input unit IO (i) is coupled to substrate 20 no longer separately.Similarly, general output/input unit IO (j) also only is coupled to the signal pin SP (j) of substrate 20 by single signal bonding pad opening Fb (j).
With respect to the embodiment of Fig. 4, Fig. 5 then shows further application of the invention embodiment.As long as the arrangement of signal conductor is (for example routing can meet the standard of encapsulation) suitably, two signal bonding pad opening Fa (i) of same general output/input unit IO (i) and Fb (i) can be respectively on signal conductor by mutually insulated two independent signal pin position SP (ia) of being connected to substrate and the SP (ib), make same general output/input unit can realize simultaneously two kinds different and independently signal export into function.The electric power connection pad opening PG (i) of general output/input unit IO (i) then can be coupled to substrate 20.
Please refer to Fig. 6, what it was illustrated is that chip 10 collocation one substrate 22 of the present invention is to be applied to the another embodiment of integrated circuit of the present invention.In this embodiment, substrate 22 is provided with electric power ring (ring) PR working voltage source is provided.In chip 10, the electric power connection pad opening PG (i) of general output/input unit IO (i) promptly is that the electric lead by correspondence is connected to electric power ring PR, and the signal bonding pad opening Fa (i) of same general output/input unit IO (i) the also signal conductor by correspondence is connected to signal pin SP (i) on the substrate 22, make general output/input unit IO (i) can not only realize that signal exports into function, also can be between electric power ring PR and chip 10 transferring electric power.
In an embodiment of chip 10 of the present invention, Control Engine CE loads and carries out a program code when chip enable, and sets function in each general output/input unit respectively according to execution result.So, as long as the substrate of suitably collocation correspondence just can utilize the chip of same architecture to form different types of integrated circuit.Please refer to Fig. 7 and Fig. 8; That this two figure illustrates is exactly the present invention realizes different integrated circuits respectively with identical chips embodiment.
In Fig. 7, chip 10 of the present invention is to wait the function of setting general-purpose output/input unit IO (i-1), IO (i), IO (i+1) respectively with setting signal group CS (i-1), CS (i), CS (i+1).After chip 10 is assembled in substrate 20, suppose that general output/input unit IO (i-N) is defined as the 0th to N the position (being denoted as Addr (0:N) among Fig. 7) in the address signal respectively to the signal bonding pad opening Fa (i-N) of IO (i) to Fa (i), and general output/input unit IO (i+1) is defined as data-signal DQ (0:M-1) to the signal bonding pad opening Fa (i+1) of IO (i+M) to Fa (i+M).Jointly, will write down the functional definition of each signal bonding pad opening Fa (i-N) among the program code cdA accordingly to Fa (i), Fa (i+1) to Fa (i+M), and write down corresponding setting signal group CS (i-N) to CS (i) and CS (i+1) to CS (i+M).
Behind chip 10 executive program code cdA, Control Engine CE just can utilize setting signal group CS (i-N) to CS (i) and CS (i+1) to (CS (i+M) comes the function of setting general-purpose output/input unit IO (i-N) to IO (i), IO (i+1) to IO (i+M); For example, Control Engine CE can with signal bonding pad opening Fa (i-N) to the function setting of Fa (i) be that signal driving/output is to write out address signal Addr (0:N), signal bonding pad opening Fa (i+1) to the signal of Fa (i+M) drive with signal receiving function then by activation in the lump, to cooperate reading in and writing out of data-signal DQ (0:M-1).
On the other hand, in Fig. 8, same chip 10 be cooperate another substrate 20 ' with customized be different types of integrated circuit.In this integrated circuit, signal bonding pad opening Fa (i-K) is defined by data-signal DQ (0:K-1) to Fa (i-1), electric power connection pad opening PG (i) is defined by electric power pin position (being denoted as power among Fig. 8), and general output/input unit IO (i+1) then is defined by command signal CMD (0:L-1) to IO (i+L) pairing signal bonding pad opening Fb (i+1) to Fb (i+L).For cooperating above-mentioned definition, also write down among the program code cdB each general output/input unit IO (i-K) to IO (i+L) the function that should possess and corresponding setting signal group CS (i-K) to CS (i+L).Behind Control Engine CE executive program code cdB, but just enable signal connection pad opening Fa (i-K) drives function to the signal of Fa (i-1) and makes its energy receiving and transmitting data signals DQ (0:K-1) with signal receiving function; General output/input unit IO (i) then is set to the function of electric power transfer.To the Fb (i+L), its signal drives function and then is enabled, so that send (writing out) command signal CMD (0:L-1) concerning signal bonding pad opening Fb (i+1).
When reality was implemented, Control Engine CE can set the relevant deposit unit (register) among the Control Engine CE behind the executive program code, and Control Engine CE promptly is a function of setting each general output/input unit according to the mode bit in these deposit units respectively.
The said procedure code can be stored in the outer external memory storage (for example being nonvolatile memory) of chip of the present invention, so that program code is loaded on chip 10 of the present invention and Control Engine CE when chip/integrated circuit of the present invention comes into operation.In another kind of embodiment, itself, built-in nonvolatile memory stores aforementioned program code in the chip 10 with regard to being arranged.Because the application elasticity of the general output/input unit of the present invention is very high, so when being applied to the memory control chip, can go out the memory interface (DDR is double data frequency, Double Data Rate) of different sizes such as DDR1, DDR2 and DDR3 with identical general output/input unit framework.
Because the present invention can export into function with identical different electric power function and the signals of general output/input unit realization of circuit framework, so design of the present invention is high with application elasticity, also can significantly simplify the design cycle of chip, make general output/input unit put with coiling be able to computer and Software tool automation finish.Please refer to Fig. 9; What Fig. 9 illustrated is the flow process 900 of using the general output/input unit design chips of the present invention (especially its output/input interface), and its key step includes:
Step 902: purchase the identical general output/input unit of same kind of a plurality of circuit structures, each general output/input unit can be realized different functions respectively, just general output/input unit IO of the present invention (n) as described above.In this step, can need with several general output/input units according to the required general output/input unit of the functional requirement of integrated circuit, chip and interface decision, and each general output/input unit function that should possess.
Step 904:, carry out one with a computer and put automatically and the tool software of wind the line (automatic placing and routing), to determine the position and the coiling of these general output/input units in chip at the general output/input unit of previous step.
Step 906: in the chip internal circuit, arrange built-in (numeral) Control Engine to set the function of each general output/input unit.For example, suitable digital control logic and register are set in Control Engine, make Control Engine can be according to the function of each general output/input unit optionally the block that respectively reads in of each general output/input unit of activation receive to carry out signal, and the block that respectively writes out of each general output/input unit of activation drives to carry out signal to make Control Engine be able to according to the function of each general output/input unit optionally.
Step 908: in the chip internal circuit, arrange other circuit.The application circuit that reads in that the front discussed for example being set in chip, also can arranging other auxiliary circuit in the chip internal circuit, similarly is phase-locked loop or the like.
The sequencing of above-mentioned steps can change arbitrarily on demand.For example, also can carry out step 906 and 908 earlier, carry out step 904 again, unify to determine the position and the coiling of Control Engine, various auxiliary circuit and each general output/input unit with the technology of putting automatically and wind the line.
Before the step 902 of carrying out flow process 900 of the present invention, can pre-designed general output/input unit of the present invention, and its design (with the mode of setting) is recorded in the circuit unit database (cell library), as the resource of circuit design.Deng to design/during customized chip, just directly adopt the general output/input unit that has before designed in the circuit unit database thus.
In summary, compared to prior art, in general output/input unit of the present invention and correlation technique, be the multiple different function that realizes out capable of being combined with a kind of general output/input unit, have preferable application elasticity, also can promote the aggregation degree of interface.Extend the extensive use of each general output/input unit, use that the chip of the general output/input unit of the present invention is also related to have preferable function elasticity, can be in response to various integrated circuit demand.
In sum; though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; anyly be familiar with this operator; without departing from the spirit and scope of the present invention; when can doing various changes that are equal to or replacement, so protection scope of the present invention is when looking accompanying being as the criterion that the application's claim scope defined.
Claims (20)
1. a general output/input unit is characterized in that, includes:
One electric power connection pad opening, it optionally connects an electric lead to be coupled to a predetermined voltage by this electric lead; And
At least one signal bonding pad opening, each signal bonding pad opening optionally connect a signal conductor to carry out the signal transmission by this signal conductor.
2. general output/input unit according to claim 1 is characterized in that, this electric power connection pad opening is to be arranged in same hurdle with each signal bonding pad opening.
3. general output/input unit according to claim 2 is characterized in that,, each signal bonding pad opening all is arranged at a side of this electric power connection pad opening, and the opposite opposite side that makes this electric power connection pad opening is signalization connection pad opening not.
4. general output/input unit according to claim 1 is characterized in that, also includes:
At least one is exported into block, and the signal bonding pad opening that block is coupled to a correspondence is gone in each output, and each is exported into block is independent respectively controlled to set its function.
5. general output/input unit according to claim 4, it is characterized in that, be to be applied to a memory interface, wherein, it is controlled and carry out signal and drive with signal and receive to have at least an output to go into block, receives and dispatches a data-signal or a data index signal to export from this into the signal bonding pad opening of block correspondence.
6. general output/input unit according to claim 4, it is characterized in that, be to be applied to a memory interface, wherein, it is controlled and carry out signal and drive to have at least an output to go into block, exports a memory clock pulse, an address signal or a command signal to export from this into the signal bonding pad opening of block correspondence.
7. a chip is characterized in that, includes:
One Control Engine, and
A plurality of general output/input units are coupled to this Control Engine, and each general output/input unit includes:
One electric power connection pad opening, its alternative electric lead of a correspondence that connects is to be coupled to a predetermined voltage by this electric lead; And
The signal conductor that at least one signal bonding pad opening, each signal bonding pad opening optionally connect a correspondence carries out the signal transmission with the setting according to this Control Engine.
8. chip according to claim 7, it is characterized in that, each general output/input unit also includes at least one output and goes into block, each exports the signal bonding pad opening that is coupled to a correspondence into block, and this Control Engine be set respectively each output in each general output/input unit go into block with undertaken by each corresponding signal bonding pad opening signal drive with signal receive at least one of them.
9. chip according to claim 8, it is characterized in that, each general output/input unit is to be applied to a memory interface, and this Control Engine is at least one general output/input unit at least one to be exported drive with signal into the controlled execution signal of block to receive, and receives and dispatches a data-signal or a data index signal to export from this into the signal bonding pad opening of block correspondence.
10. chip according to claim 8, it is characterized in that, each general output/input unit is to be applied to a memory interface, and this Control Engine is that at least one general output/input unit at least one exported into block is controlled and carry out signal and drive, and exports a memory clock pulse, an address signal or a command signal to export from this into the signal bonding pad opening of block correspondence.
11. chip according to claim 7 is characterized in that, this Control Engine is to carry out a program code when this chip enable, and sets each signal bonding pad opening in each general output/input unit respectively according to execution result.
12. chip according to claim 7, it is characterized in that, in each general output/input unit, this electric power connection pad opening and each signal bonding pad opening are to be arranged in a hurdle along a first direction, and the electric power connection pad opening of adjacent general output/input unit is along second direction alignment, and wherein this second direction is vertical with this first direction.
13. chip according to claim 7, it is characterized in that, in each general output/input unit, this electric power connection pad opening and each signal bonding pad opening are to be arranged in a hurdle along a first direction, and the signal bonding pad opening of adjacent general output/input unit is along second direction alignment, and wherein this second direction is vertical with this first direction.
14. an integrated circuit is characterized in that, includes:
One substrate;
One chip, it includes:
One Control Engine, and
A plurality of general output/input units, each general output/input unit includes:
One electric power connection pad opening, its alternative is connected to this substrate by the electric lead of a correspondence, to be coupled to a predetermined voltage by this electric lead; And
At least one signal bonding pad opening, each signal bonding pad opening optionally signal conductor by a correspondence are connected to this substrate and carry out the signal transmission with the setting according to this Control Engine.
15. integrated circuit according to claim 14, it is characterized in that, this substrate includes an electric power ring and a signal pin, be connected to this electric power ring and the electric power connection pad opening that has a general output/input unit in this chip at least is a electric lead by correspondence, and at least one signal bonding pad opening of this general output/input unit is that signal conductor by correspondence is connected to this signal pin.
16. integrated circuit according to claim 14, it is characterized in that, this substrate includes an electric power pin position, be connected to this electric power pin position and the electric power connection pad opening that a general output/input unit is arranged in this chip is a electric lead by correspondence, and each signal bonding pad opening of this general output/input unit all is not connected to this substrate by the signal conductor of correspondence.
17. integrated circuit according to claim 14, it is characterized in that, this substrate includes two independently signal pins, and each general output/input unit of this chip includes a plurality of signal bonding pad openings respectively, and two signal bonding pad openings that a general output/input unit is wherein arranged are that the signal conductor by correspondence is connected to these two independently signal pins respectively.
18. the method for design one chip is characterized in that, includes:
Purchase the identical general output/input unit of a plurality of kinds, each general output/input unit includes:
One electric power connection pad opening, it can selectivity connect the electric lead of a correspondence to be coupled to a predetermined voltage by this electric lead according to the function of this general output/input unit; And
At least one signal bonding pad opening, each signal bonding pad opening are optionally to connect the signal conductor of a correspondence according to the function of this general output/input unit to carry out the signal transmission; And
Carry out one with a computer and put automatically and wind the line, to determine this position and the coiling of a plurality of general output/input units in this chip.
19. method according to claim 18 is characterized in that, other includes:
In this chip, arrange a built-in Control Engine to set the function of each general output/input unit.
20. method according to claim 18 is characterized in that, when respectively this signal bonding pad opening in each general output/input unit carries out signal when transmitting by this signal conductor, be optionally carry out signal drive in receiving with signal at least one of them.
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| CN2010101189614A CN102136462B (en) | 2010-01-27 | 2010-01-27 | General output and input unit as well as related device and method thereof |
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| CN2010101189614A CN102136462B (en) | 2010-01-27 | 2010-01-27 | General output and input unit as well as related device and method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102938831A (en) * | 2011-08-16 | 2013-02-20 | 宏达国际电子股份有限公司 | Control circuit of electronic device and display device |
| CN104183592A (en) * | 2013-05-22 | 2014-12-03 | 晨星半导体股份有限公司 | Chip allowing flexible modification of gasket sequence and related method |
| CN102938831B (en) * | 2011-08-16 | 2016-12-14 | 宏达国际电子股份有限公司 | The control circuit of electronic installation and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6798069B1 (en) * | 2003-03-28 | 2004-09-28 | Lsi Logic Corporation | Integrated circuit having adaptable core and input/output regions with multi-layer pad trace conductors |
| US6717270B1 (en) * | 2003-04-09 | 2004-04-06 | Motorola, Inc. | Integrated circuit die I/O cells |
| JP2005217321A (en) * | 2004-01-30 | 2005-08-11 | Nec Electronics Corp | Automatic arrangement wiring device, method for arrangement wiring semiconductor device, semiconductor device and its manufacturing method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102938831A (en) * | 2011-08-16 | 2013-02-20 | 宏达国际电子股份有限公司 | Control circuit of electronic device and display device |
| CN102938831B (en) * | 2011-08-16 | 2016-12-14 | 宏达国际电子股份有限公司 | The control circuit of electronic installation and display device |
| CN104183592A (en) * | 2013-05-22 | 2014-12-03 | 晨星半导体股份有限公司 | Chip allowing flexible modification of gasket sequence and related method |
| CN104183592B (en) * | 2013-05-22 | 2017-03-01 | 晨星半导体股份有限公司 | Can the elastic chip changing jointing pad sequence and correlation technique |
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Effective date of registration: 20201027 Address after: No. 1, Xingzhu Road, Hsinchu Science Park, Taiwan, China Patentee after: MEDIATEK Inc. Address before: 518057, Guangdong, Shenzhen hi tech Zone, South District, science and technology, South ten road, Shenzhen Institute of Aerospace Science and technology innovation, C block, building 4 Patentee before: Mstar Semiconductor,Inc. Patentee before: MEDIATEK Inc. Effective date of registration: 20201027 Address after: 4 / F, block C, Shenzhen Aerospace Science and Technology Innovation Research Institute, science and technology south 10th Road, South District, Shenzhen high tech Zone, Guangdong Province Patentee after: Mstar Semiconductor,Inc. Patentee after: MEDIATEK Inc. Address before: 518057, Guangdong, Shenzhen hi tech Zone, South District, science and technology, South ten road, Shenzhen Institute of Aerospace Science and technology innovation, C block, building 4 Patentee before: Mstar Semiconductor,Inc. Patentee before: MSTAR SEMICONDUCTOR Inc. |
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