JP2003271548A - Data transfer method and data transfer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve transfer efficiency by reducing the number of signal lines used, and enabling addressed read operation and write operation so as to reduce the number of steps of data transfer procedure. <P>SOLUTION: The procedure for operating an I/O port by software of a circuit test device to perform read operation for data transfer is as follows. An address and write/read select data are read and set in a bus (step S101), a control signal (ALOE signal) is validated (step S102), the drive of the bus is stopped (step S103), data is read from the bus, and stored as read data (step S104), and then the control signal (ALOE signal) is made invalid (step S105). Thus, data transfer can be performed efficiently with a small number of steps. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system applied to data transfer between a circuit inspection device, a circuit board to be inspected, and an IC chip, and particularly, an address and data are shared by a small number of control signal lines. The present invention relates to a data transfer method and a data transfer device of a circuit inspection device using a bus signal (two-way transmission signal line) that operates.

[0002]

2. Description of the Related Art As a data transfer method between a circuit inspection device, a circuit board to be inspected, and an IC chip, there is a memory structure disclosed in Japanese Patent Application Laid-Open No. 7-186783. This data transfer method reduces the number of necessary input / output terminals to reduce the size of the IC package used for the bus, and reduces the wiring amount of the circuit board for wiring the bus signals. Data is shared on a common bus.

The parallel-to-serial conversion device and parallel-to-serial conversion system disclosed in Japanese Patent Laid-Open No. 2000-151423 describe serial transfer systems and configurations, which are used to transfer data bit by bit. This is a method of reducing the circuit scale of the serial-parallel conversion circuit.

Further, the inter-package connection bus multiplexing method disclosed in Japanese Patent Laid-Open No. 5-342147 is intended to reduce the number of pins of the IC package by multiplexing the bus signals, thereby achieving miniaturization of the package. is there. Although this technique is between IC chips, it will be mentioned as a data transfer method using a bus. A configuration is described in which a bus is multiplexed with an address and data, an address is latched by an address latch signal, and a read signal line and a write signal line are used for a read operation and a write operation, respectively.

[0005]

However, with the rapid development of the information industry in recent years, various devices for transferring data are required to handle large-capacity data signals, and circuit boards used in these devices are A large amount of data is being used, and high-speed signals are being handled.

FIG. 4 is a diagram showing a connection structure when the circuit board 400 is inspected by a circuit inspection device. As shown,
When developing / manufacturing the circuit board 400 provided in the device for transferring data, the circuit board 40 to be tested is to be tested.
0 is connected to the circuit inspection device 401 for operation confirmation, and data is transferred between the circuit board 400 and the circuit inspection device 401 to confirm the operation.

The circuit inspection device 401 has hardware (computer) 403 and inspection program (software) 402, and is connected to the circuit board 400 via an I / O port 404. However, the conventional I / O port 404 may not be able to perform all necessary processing due to restrictions on data transfer. Therefore, conventionally, a jig circuit device 405 is arranged between the circuit board 400 and the circuit inspection device 401 to process a high-speed signal that cannot be processed.

The configuration of the circuit inspection device 401 will be described in detail. The computer 403 operates the I / O port 404 to set the voltage of the signal line and input / output a logical value “1” or “0”. For example, the widely known T
The logical value is indicated by the signal voltage of the IC chip of the TL and CMOS standards. The signal output from the I / O port 404 is given to the circuit board 400 by the signal line 406, and at the same time, the signal generated by the circuit board 400 is input / output by the signal line 406.
This signal is input to the port and this signal is input to the computer 403.

For a high-speed, large-capacity data signal that cannot be directly processed by the I / O port 404, the jig circuit device 40 is connected from the I / O port 404 using the signal line 407.
5 are connected to the circuit board 400 via the signal line 408. The jig circuit device 405 controls operations for inspecting the circuit board 400, such as speed conversion from high speed to low speed, accumulation of a large amount of data signal, and the like. Signal line 40
6, 407 and 408 are composed of a plurality of signal lines.
The software 402 is a control program for inspection processing by the circuit inspection device 401.

The jig circuit device 405 is a computer 40.
3 does not directly operate, but operates via the I / O port 404. This is because the software 402 called an I / O port operation driver can operate only the I / O port 404. In order to allow the computer 403 to directly operate the jig circuit device 405, it is necessary to newly develop and prepare software called a jig circuit device operation driver for each jig circuit device 405. . In order to avoid this, the configuration is such that the I / O port 404 is used as described above.

The problem here is the circuit inspection device 401.
How to perform the data transfer method between the I / O port 404 and the jig circuit device 405. According to a general data transfer method, a register for operating the jig circuit device 405 is designated by an address and data is transferred to the computer 40.
It is possible to perform the write operation of transferring the data from No. 3 to the jig circuit device 405 and the read operation of transferring the data from the jig circuit device 405 to the computer 403. Two methods are conventionally known to realize this means.

The first conventional data transfer method is I / O
The O port 404 is a data transfer using a bus signal indicating an address, a bus signal indicating data, a read as a control bus signal, and a bus signal as a write. In this case, since the number of signal lines is large, the number of signal lines of the connection cable 407 is large, an expensive connector with a large number of poles is required for connection, and the cable is also large and difficult to handle. In addition, there are many wirings inside the jig circuit device 405, the area is large, the number of terminals of the IC used in the circuit is increased, and an expensive large package IC is required.

Since many I / O ports are used,
The number of I / O ports available on the circuit board 400 is reduced, and in some cases, it may be impossible to inspect all the signals on the circuit board 400. Thus, it is desirable that the number of signals used for data transfer be as small as possible.

In this regard, the above-mentioned conventional Japanese Patent Laid-Open No. 7-1
According to the data transfer system disclosed in Japanese Patent No. 687883, it is possible to reduce the number of signal lines by sharing the address / data bus with a common bus. However, there are still three control buses (address strobe signal,
The problem remains to use write signals and read signals).

As a method of further reducing the number of signal lines from the above method, a method of realizing only one of the read operation and the write operation can be considered. For example, if the read operation is not required to be realized, the number of control bus signal lines can be reduced to two control buses (address strobe signal, write signal), but this significantly impairs the function of controlling the jig circuit device 405. It is assumed that the circuit board 400 cannot be sufficiently inspected due to a lack of functions. Further, if the read operation cannot be performed, it becomes difficult to manufacture the software 402, which causes a problem that the software manufacturing time increases.

Further, in the data transfer, it is necessary to specify an address to the register so that both the read operation and the write operation can be performed. Therefore, in the conventional method, at least three control buses are required. It was necessary to use a book (address / strobe signal, write signal, read signal).

The second conventional data transfer method is a serial transfer method, which is disclosed in Japanese Patent Laid-Open No. 2000-151423.
It is disclosed in the publication. According to this technique, the bus signal and the control signal line can be only the clock signal and the data signal, so that the number of signal lines used for data transfer can be reduced.
However, it has the following problems.

One is that it is necessary to add a serial / parallel conversion circuit to the jig circuit device 405. JP 2
As disclosed in Japanese Patent Application Laid-Open No. 000-151423, the point that the circuit amount of the serial-parallel conversion circuit is reduced is the object of improvement, and this point is a problem that must be solved conventionally.

Another problem is that the number of software steps increases because the data transfer uses a clock of a plurality of cycles to transfer a data bit a plurality of times. As a result, there is a drawback that the inspection time in the circuit inspection device 401 becomes long and the inspection cost increases. Also,
Since the time required for the data transfer increases, it takes a long time to transfer the data of the large-capacity data signal.
However, the inspection time becomes longer and the inspection cost increases.

For example, in contrast to the conventional "data transfer using a bus signal", the number of write operation steps is 6, while the software of "I / O port operation procedure of software for data transfer by conventional serial communication" The number of steps of wear is 24, which means that the time required is four times as much. As described above, it is not desirable to use serial transfer as the data transfer method for the circuit inspection device 401.

For reference, a software I / O port operation procedure (when 8-bit data is transferred by a data signal line and a clock signal line) in the case of data transfer by conventional serial communication will be described. FIG. 5 shows a timing chart up to step 12 (S512) below.

Step 1. Data bit 1 is set to data signal line (S501) Step 2. 2. Set clock signal line to 0 (S502) Step 3. 3. Set clock signal line to 1 (S503) Step 4. 4. Set data bit 2 to data signal line (S504) Step 5. Set clock signal line to 0 (S505) Step 6. Set clock signal line to 1 (S506) Step 7. Set data bit 3 to data signal line (S507) Step 8. Set clock signal line to 0 (S508) Step 9. Set clock signal line to 1 (S509) Step 10. Set data bit 4 to data signal line (S510) Step 11. Set the clock signal line to 0 (S51
1) Step 12. Set the clock signal line to 1 (S51
2) Step 13. Set data bit 5 to data signal line Step 14. Set clock signal line to 0 Step 15. Set clock signal line to 1 Step 16. Set data bit 6 to data signal line Step 17. Set clock signal line to 0 Step 18. Set clock signal line to 1 Step 19. Set data bit 7 to data signal line Step 20. Set clock signal line to 0 Step 21. Set clock signal line to 1 Step 22. Set data bit 8 to data signal line Step 23. Set clock signal line to 0 Step 24. Set clock signal line to 1

Conventional "Data Transfer Using Bus Signal"
The I / O port operation procedure of the read operation software is as follows. FIG. 6 shows a timing chart of this read operation. Step 1. Output address to bidirectional bus signal (S6
01) Step 2. Enable the address selection signal (S60
2) Step 3. Disable the address selection signal (S60
3) Step 4. Stop output of bidirectional bus signal (S60
4) Step 5. Validate read signal (S605) Step 6. Read data from bidirectional bus signals,
Save as read data (S606) Step 7. Invalidate the read signal (S607)

Conventional “Data Transfer Using Bus Signal”
The I / O port operation procedure of the write operation software is as follows. FIG. 7 is a timing chart of the write operation. Step 1. Set address on bus (S701) Step 2. An address is selected by an address / data selection signal (S702) Step 3. 3. Select data with address / data selection signal (S703) Step 4. Data is set in the bus (S704) Step 5. Validate write signal (S705) Step 6. Disable the write signal (S706)

As described above, in the conventional data transfer using the bus signal, the number of steps of software is 7 in the read operation and 6 in the write operation, and the number of steps in the data transfer procedure is large. The transfer efficiency is poor.

According to the present invention, in order to solve the above-mentioned problems of the prior art, the number of signal lines to be used can be reduced, the read operation and the write operation by designating an address can be performed, and the number of steps of the data transfer procedure can be reduced. Therefore, it is an object of the present invention to provide a data transfer method and a data transfer device capable of improving transfer efficiency.

[0027]

[Means for Solving the Problems]
In order to achieve the object, a data transfer method according to the invention of claim 1 is a data transfer in which data is transferred using one control signal and a bus signal which commonly uses an address, write / read selection data and data. In the method, at least one bit of the bus signal is write / read selection data, at least one bit of the bus signal is an address, and the logical value of the control signal is "1" to "0" (or "0" to " 1)), the address of the bus signal and the write / read selection data are held respectively.

According to the first aspect of the present invention, it is possible to designate a register which holds an address and which transfers data by the address by setting a logical value of the control signal. Therefore, the number of signal lines can be reduced and the address can be designated. Since the read operation and the write operation can be selected, the number of steps in the data transfer procedure can be reduced.

The data transfer method according to a second aspect of the present invention is the data transfer method according to the first aspect, wherein the bus signal is a bidirectional bus signal, and the write / read selection data is a logical value indicating a read operation. Holds, the logical value of the control signal is "1" (or "0").
When the logical value of the control signal is "0" (or "1"), the bus signal is not driven, and the bus signal is driven.

According to the invention of claim 2, the bidirectional bus signal is driven based on the stored write / read selection data and the setting of the control signal, and the number of steps of the data transfer procedure of the read operation can be reduced. .

The data transfer method according to a third aspect of the present invention is the data transfer method according to the first aspect, wherein the bus signal is a bidirectional bus signal, and a logical value indicating a write operation for the write / read selection data. Is held, the data of the bus signal is held when the logical value of the control signal changes from “0” to 1 (or “1” to “0”).

According to the invention of claim 3, since the data of the bus signal can be held in the register, the number of steps in the transfer procedure of the write operation can be reduced.

According to a fourth aspect of the present invention, there is provided a data transfer device, which includes one control signal, a bus signal for commonly using address, write / read selection data and data, and an address holding means for holding address data. And a storage unit for storing a read or write operation, using at least 1 bit of the bus signal as write / read selection data and at least 1 bit of the bus signal as an address, and regarding a logical value of the control signal. By setting from "1" to "0" (or "0" to "1"),
The address of the bus signal is held by the address holding means, and the write / read selection data is held by the operation saving means.

According to the invention of claim 4, the register for holding the address and transferring the data by the address can be designated by setting the logical value of the control signal, so that the number of signal lines can be reduced and the read by designating the address can be performed. Since the operation and the write operation can be selected, the number of steps in the data transfer procedure can be reduced. In addition, high-speed and efficient data transfer can be achieved while simplifying the configuration related to data transfer.

According to a fifth aspect of the present invention, in the data transfer apparatus according to the fourth aspect, the bus signal is a bidirectional bus signal, and the device including the operation storage means is a bidirectional bus signal. When the control signal has a logic value of "1" (or "0") in a state in which the operation storage means holds a logic value indicating a read operation,
The bus signal is not driven, and the bus signal is driven when the logical value of the control signal is "0" (or "1").

According to the invention of claim 5, the bidirectional bus signal is driven based on the stored write / read selection data and the setting of the control signal, and the number of steps of the data transfer procedure of the read operation can be reduced. .

According to a sixth aspect of the present invention, in the data transfer apparatus according to the fourth aspect, the device including the operation storage means has a register for holding the data of the bus signal, and the operation storage is performed. The logic value of the control signal is "0" while the means holds the logic value indicating the write operation.
When (or "1") changes to "1" (or "0"), the data of the bus signal is held in the register.

According to the sixth aspect of the invention, since the data of the bus signal can be held in the register, the number of steps in the transfer procedure of the write operation can be reduced.

A data transfer apparatus according to a seventh aspect of the present invention is the data transfer apparatus according to any one of the fourth to sixth aspects, wherein the circuit board to be tested and a circuit for inspecting the circuit board are provided. I / O that transfers data to and from the board
A circuit inspection device having a port, and the circuit inspection device,
A jig circuit device for performing large-capacity and high-speed data transfer provided between the jig and the circuit board, and the jig circuit device between the I / O port of the circuit inspection device and the jig circuit device. Characterized by performing data transfer.

According to the seventh aspect of the invention, when the circuit board to be tested is tested, the data transfer between the circuit inspection device and the jig circuit device can be performed with a small number of signal lines. Since the number of steps can be reduced, it is possible to achieve high-speed and efficient data transfer while simplifying the configuration related to data transfer.

According to an eighth aspect of the present invention, in the data transfer apparatus according to the seventh aspect, the jig circuit device has the functions of the address holding means and the operation storage means, and PLD ( Programmable logic device).

According to the eighth aspect of the present invention, the data transfer structure in the jig circuit device can be simply and efficiently performed.

[0043]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of a data transfer method and a data transfer apparatus according to the present invention will be described in detail below with reference to the accompanying drawings. The data transfer device of the present invention can be applied to the circuit inspection device 401 and the jig circuit device 405 described above, and in this case, the connection configuration shown in FIG. 4 is adopted. In the following description, the same components as those described in the related art will be designated by the same reference numerals and the description thereof will be omitted.

In the present invention, the control signal (ALO
The number of buses used in E) is reduced from the conventional three to one, and the number of required signal lines is reduced. By using this, the read operation and the write operation by designating the address are performed. Further, as will be described below, the number of data transfer steps is reduced.

First, the circuit inspection device 401 will be described based on the configuration. That is, a write operation of designating a register for operating the jig circuit device 405 by an address and transferring data from the circuit inspection device 401 to the jig circuit device 405, and a read operation of transferring data from the jig circuit device 405 to the circuit inspection device 401. The main configuration regarding the operation will be described.

The data transfer method in the circuit inspection device 401 is realized by the computer 403 and software 402 as described above. In addition, the circuit inspection device 401
The upper I / O port 404 can be realized by mounting a general-purpose expansion I / O board on the computer expansion bus.

(Embodiment 1) First, the data transfer method according to the present invention will be described with reference to the computer 40 of the circuit inspection device 401.
An embodiment of the software 402 realized in 3 will be described. FIG. 1 is a timing chart showing the I / O port operation procedure of the software 402 of the read operation of the data transfer of the present invention.

Step 1. The address and write / read selection data are read and set on the bus (S101) Step 2. 2. Enable the ALOE signal (S102) Step 3. Stop driving the bus (S103) Step 4. 4. Read data from the bus and save as read data (S104) Step 5. Disable the ALOE signal (S105)

At least one bit of the bus in the procedure 1 is write / read selection data, and the other bits are address data. For example, if the bus is BUS [7. ． 0] of 8
For bits, BUS [6. ． Address data is indicated by 7 bits of the [0] signal. If 1 bit of the BUS [7] signal is "1", read designation is given, and if it is "0", write designation is given. As a result, 128 addresses can be designated, and a sufficient number can be secured for use in the circuit inspection device 401. The bus in step 4 (S104) is data in which all bits are read. For example, if the bus is BUS [7. ． 0]
8 bits of BUS [7. ． 0] lead 8
It is bit-width data. In the description, [7. ． 0]
The following description is a description for collectively explaining the eight signal lines.

FIG. 2 is a timing chart showing the I / O port operation procedure of the software of the write operation of the data transfer of the present invention. Step 1. Write the address and write / read selection data to the bus (S201) Step 2. 2. Enable the ALOE signal (S202) Step 3. Output the data to write to the bus (S
203) Step 4. Disable the ALOE signal (S204)

According to the above procedure, there are a total of 5 steps for the read operation and 4 steps for the write operation, which can be shortened compared to the conventional number of steps. Therefore, the steps of software for realizing the read operation and the write operation can be reduced. Data transfer is 7/5 ≈ 1.4 times for read operation and 6/4 ≈ for write operation
It will be 1.5 times faster. As a result, it is possible to reduce the inspection cost by shortening the inspection time of the circuit board 400, and it is possible to speed up the data transfer of the large-capacity data signal of the circuit board 400 to be tested, which could not be realized in the past.

(Second Embodiment) Next, an embodiment in which the data transfer method of the present invention is applied to the jig circuit device 405 will be described. The jig circuit device 405 is provided with an IC that realizes the above-described data transfer method. A PLD (Programmable Logic Device) is used as the IC circuit. For example, PL made by ALTERA
A D-IC can be used.

FIG. 3 is a circuit block diagram showing a configuration relating to data transfer in the jig circuit device 405. The bus signal is 8 bits, the data can be transferred in 8 bits, of which the address is 7 bits and the signal line BUS
[6. ． 0] and write / read selection data is shown on the signal line BUS [7].

As shown in the figure, the internal structure is roughly I /
F unit 301, address storage unit 302, operation storage unit 30
3, an address decoder unit 304, a read data selection unit 305, and register units 306 to 309.

The I / F unit 301 includes a jig circuit device 405.
The RESET signal 310 connected to the inside of the substrate of or of the connection circuit is supplied. This RESET signal 310 is
It is a reset signal which is initialized with a bit value “0” when the power is turned on and is normally “1”. It is supplied when each part in the IC is reset.

Bus signal 312 (BUS [7..0])
Is connected to the I / O port 404 of the circuit inspection device 401. The control signal 313 (ALOE signal) is one signal line connected to the I / O port 404 of the circuit inspection device 401. The register units 306 to 309 are composed of 8-bit flip-flop circuits. When the enable terminal is “1”, the WRITE_PULSE signal 314
Changes from “0” to “1”, data [7. ．
0] terminal data is held and q [7. ． 0] terminal, and the state of the enable terminal and WRITE_PUL
Even if the SE signal 314 changes to “0”, q [7. ． 0] terminal output is held.

Although not shown, the output q [7. ．
0] is connected to another circuit of the jig circuit device 405 and is used for controlling the jig circuit device 405. Further, it is connected to the circuit board 400 to be inspected through a signal line 315 (REG DATA) and used for circuit inspection.

Next, the data transfer operation according to the above configuration will be described. When the ALOE signal 313 changes from “1” to “0”, the write / read selection data (1 bit of BUS [7] in this example) of the bus signal 312 (BUS [7..0]) is stored in the operation storage unit 303. Stored in the other bit (B
US [6. ． 0] (7 bits) is the address storage unit 302
Stored in.

An address decoder section 304 is connected to the address storage section 302, and register sections 306 to 3 are provided.
Any one of 09 enable is selected. In addition, 1 selected by the read data selection unit 305
One register unit 306 to 309 is connected to the input of the gate unit 316.

When performing a read operation by this method, since "1" is set in BUS [7] of the bus signal 312, "1" is held in the operation storage unit 303. Here, since the ALOE signal 313 is “0”, the gate unit 31
6 output becomes valid, and the selected one register unit 3
The data recorded in 06 to 309 is the bus signal 312.
BUS [7. ． 0]. After that, ALOE
When the signal 313 becomes “1”, the output of the gate unit 316 becomes invalid and the bus signal 312 BUS [7. ． 0] to the I / O port 40 of the circuit inspection device 401 is stopped.
4 to the bus signal 312.

On the other hand, when performing the write operation, since BUS [7] of the bus signal 312 is set to "0",
The operation storage unit 303 holds “0”. Where A
Since the LOE signal 313 is “0”, WRITE_P
The ULSE signal 314 becomes “0”. After that, ALOE
When the signal 313 becomes “1”, WRITE_PULSE
The signal 314 changes from “0” to “1”, and the data of the bus signal 312 is stored in one of the register units 306 to 309 selected by the read data selection unit 315.

The ALOE signal 313 is not limited to the above configuration example.
And the bus width of the bus signal 312 may be different. For example, "1" and "0" of the ALOE signal 313 may be exchanged. Even if the bus signal 312 is a 32-bit bus signal, data can be transferred by using only one ALOE signal 313 as a control signal.

Further, the address storage unit 302 and the operation storage unit 303 can be realized by using a latch element instead of using a flip-flop. In this case, the ALOE signal 3 is used.
When 13 is “0”, the bus signal 312 is the address storage unit 3
02, stored in the operation storage unit 303 and operated.

As described above, the data transfer apparatus according to the present embodiment enables efficient data transfer while using existing wiring without changing the number of bus signal lines. .

The data transfer method described in this embodiment can be realized by programming a program prepared in advance in a computer or a PLDIC. This program itself is a hard disk, floppy (R) disk, CD-RO
It is recorded on a computer-readable recording medium such as M, MO, and DVD, and executed by being read from the recording medium by the computer. Further, this program can be distributed via the recording medium and a network such as the Internet.

[0066]

As described above, according to the invention of claim 1, one control signal, an address and a write / write signal are used.
In a data transfer method for transferring data using a bus signal that commonly uses read selection data and data, at least one bit of the bus signal is write / read selection data, and at least one bit of the bus signal is an address, Since the logical value of the control signal is set from "1" to "0" (or "0" to "1"), the address of the bus signal and the write / read selection data are held respectively. , It is possible to specify the register that holds the address and transfers the data by the address by setting the logical value of the control signal, the number of signal lines can be reduced, and the read operation and the write operation by specifying the address can be selected. It is possible to reduce the number of steps in the data transfer procedure.

According to a second aspect of the invention, in the first aspect of the invention, the bus signal is a bidirectional bus signal, and the write / read selection data has a logical value indicating a read operation. When held, when the logical value of the control signal is "1" (or "0"), the bus signal is not driven and the logical value of the control signal is "0" (or "1"). )), The bus signal is configured to be driven. Therefore, the bidirectional bus signal is driven based on the stored write / read selection data and the setting of the control signal, and the data transfer procedure of the read operation is changed. This has the effect of reducing the number of steps.

According to a third aspect of the invention, in the first aspect of the invention, the bus signal is a bidirectional bus signal, and the write / read selection data has a logical value indicating a write operation. When held, the logical value of the control signal is "0" to "1" (or "1").
Since the data of the bus signal is held when it changes from "0" to "0"), the data of the bus signal can be held in the register. Therefore, the number of steps of the transfer procedure of the write operation can be reduced. Play.

According to the invention described in claim 4, 1
A control signal for a book, a bus signal for commonly using address and write / read selection data and data, an address holding means for holding address data, and an operation saving means for saving a read or write operation, At least 1 bit of the bus signal is used as write / read selection data, and at least 1 bit of the bus signal is used as an address,
By setting the logical value of the control signal from "1" to "0" (or "0" to "1"), the address of the bus signal is held by the address holding means, and the write / read selection data is stored. Since it is configured to be held by the operation storing means, since it is possible to specify the register that holds the address and transfers the data by the address by setting the logical value of the control signal, the number of signal lines can be reduced and the read operation by specifying the address Since the write operation can be selected, the number of steps in the data transfer procedure can be reduced. Further, there is an effect that a high-speed and efficient data transfer can be achieved while simplifying the configuration related to the data transfer.

According to the invention of claim 5, in the invention of claim 4, the bus signal is a bidirectional bus signal, and the device including the operation storing means drives the bidirectional bus signal. The operation storing means holds a logical value indicating a read operation, and drives the bus signal when the logical value of the control signal is "1" (or "0"). If the logical value of the control signal is “0” (or “1”), the bus signal is driven, so that the stored write / read selection data and the control signal are set. Based on this, the bidirectional bus signal can be driven, and the number of steps of the data transfer procedure of the read operation can be reduced.

According to the invention of claim 6, in the invention of claim 4, the device including the operation saving means has a register for holding the data of the bus signal, and the operation saving means Holds a logical value indicating a write operation, and the logical value of the control signal changes from "0" (or "1") to "1" (or "0"), Since the data is held in the register so that the data of the bus signal can be held in the register, the number of steps in the transfer procedure of the write operation can be reduced.

According to a seventh aspect of the present invention, in the invention according to any one of the fourth to sixth aspects, the circuit board to be tested and the circuit board for inspecting the circuit board. A circuit inspection device provided with an I / O port for performing data transfer between the device and a jig circuit provided between the circuit inspection device and the circuit board for performing large-capacity and high-speed data transfer. Since the device is configured to transfer the data between the I / O port of the circuit inspection device and the jig circuit device, the circuit inspection device and the circuit inspection device are used when the circuit board to be tested is tested. Since data transfer with the component circuit device can be performed with a small number of signal lines and a small number of steps in the data transfer procedure, high-speed and efficient data transfer can be achieved while simplifying the configuration related to data transfer. The effect To.

According to the invention described in claim 8, in the invention described in claim 7, the jig circuit device has the functions of the address holding means and the operation storing means, and a PLD (programmable・ Logic device)
Since it is configured as described above, there is an effect that the configuration of data transfer in the jig circuit device can be performed simply and efficiently.

[Brief description of drawings]

FIG. 1 is a timing chart showing a procedure of a read operation of a data transfer method according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the procedure of a write operation of the data transfer method of the present invention.

FIG. 3 is a block diagram showing a configuration of a data transfer device according to the embodiment of the present invention.

FIG. 4 is a block diagram showing a connection configuration with a circuit inspection device when inspecting a circuit board.

FIG. 5 is a timing chart for explaining a conventional data transfer procedure by serial transfer.

FIG. 6 is a timing chart showing a procedure of a read operation according to a conventional technique.

FIG. 7 is a timing chart showing a procedure of a write operation according to a conventional technique.

[Explanation of symbols]

301 I / F section 302 address storage 303 Motion Saver 304 address decoder 305 Read data select section 306, 306, 308, 309 register unit 310 RESET signal 312 bus signal 313 Control signal (ALOE signal) 314 WRITE_PULSE signal 315 signal line (REG DATA) 316 Gate 400 circuit board 401 Circuit inspection device 402 software 403 computer 404 I / O port 405 jig circuit device 406, 407, 408 signal lines

Claims (8)

[Claims] 1. One control signal, address and write / write
In a data transfer method for transferring data using a bus signal that commonly uses read selection data and data, at least one bit of the bus signal is write / read selection data, and at least one bit of the bus signal is an address, An address of the bus signal and the write / read selection data are held in a state where the logical value of the control signal is set from "1" to "0" (or "0" to "1"). Data transfer method. 2. The bus signal is a bidirectional bus signal, and when the write / read selection data holds a logical value indicating a read operation, the logical value of the control signal is “1” (or The bus signal is not driven when it is "0"), and the bus signal is driven when the logical value of the control signal is "0" (or "1"). The data transfer method described in 1. 3. The bus signal is a bidirectional bus signal, and when the write / read selection data holds a logical value indicating a write operation, the logical value of the control signal changes from “0” to “0”. 2. The data transfer method according to claim 1, wherein the data of the bus signal is retained when it changes from "1" (or from "1" to "0"). 4. One control signal, address and write / write
A bus signal that uses read selection data and data in common, an address holding unit that holds address data, and an operation storage unit that stores a read or write operation are provided, and at least one bit of the bus signal is written / read. The selection data and at least one bit of the bus signal are used as an address, and the address of the bus signal is set by setting the logical value of the control signal from “1” to “0” (or “0” to “1”). A data transfer device, wherein the address holding means holds the write / read selection data, and the operation storing means holds the write / read selection data. 5. The bus signal is a bidirectional bus signal, and the device including the operation storage means has a drive part for the bidirectional bus signal, and the operation storage means holds a logical value indicating a read operation. When the logical value of the control signal is "1" (or "0") in the above state, the bus signal is not driven and the logical value of the control signal is "0" (or "1").
5. The data transfer device according to claim 4, wherein the bus signal is driven in the case of the above. 6. The logic of the control signal is provided in a state in which a device including the operation saving means has a register for holding data of the bus signal, and the operation saving means holds a logical value indicating a write operation. 5. The data transfer device according to claim 4, wherein when the value changes from "0" (or "1") to "1" (or "0"), the data of the bus signal is held in a register. . 7. A circuit board to be tested, and a circuit tester having an I / O port for transferring data between the circuit board to test the circuit board, the circuit tester, and It is provided between the circuit board and
A jig circuit device for performing large-capacity and high-speed data transfer is provided, and the jig circuit device is arranged between the I / O port of the circuit inspection device and the jig circuit device. A data transfer device, which performs the data transfer described in 1. 8. The data according to claim 7, wherein the jig circuit device has the functions of the address holding unit and the operation storing unit, and is configured by a PLD (Programmable Logic Device). Transfer device.