KR20110078732A - Data output circuit of semiconductor memory device - Google Patents

Data output circuit of semiconductor memory device Download PDF

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Publication number
KR20110078732A
KR20110078732A KR1020090135614A KR20090135614A KR20110078732A KR 20110078732 A KR20110078732 A KR 20110078732A KR 1020090135614 A KR1020090135614 A KR 1020090135614A KR 20090135614 A KR20090135614 A KR 20090135614A KR 20110078732 A KR20110078732 A KR 20110078732A
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KR
South Korea
Prior art keywords
sense amplifier
amplifier circuit
data line
circuit
page
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Application number
KR1020090135614A
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Korean (ko)
Inventor
김보겸
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주식회사 하이닉스반도체
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Priority to KR1020090135614A priority Critical patent/KR20110078732A/en
Publication of KR20110078732A publication Critical patent/KR20110078732A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

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  • Read Only Memory (AREA)

Abstract

PURPOSE: A data output circuit of a semiconductor memory device is provided to shorten the driving time of a sensing amplification circuit, thereby shortening data output time. CONSTITUTION: Sensing amplification circuits(210,220) group a plurality of page buffers corresponding to a bit line of a memory block and connect the page buffers to at least two page buffer groups. A MUX circuit(300) selects one of sensing amplification circuits and connects the one to an external data line. Page buffers of a page buffer group are connected to an internal data line of the sensing amplification circuits. The sensing amplification circuits perform sensing at different time.

Description

Data output circuit of semiconductor memory device

The present invention relates to a data output circuit of a semiconductor memory device.

1 is a configuration diagram illustrating a data output circuit of a semiconductor memory device according to the prior art.

Referring to FIG. 1, a data output circuit of a semiconductor memory device includes a sense amplifier circuit IOSA 20 connected to an output line IO and an inverted output line IOb of the page buffer unit 10. The sensing amplifier circuit 20 is connected to the data line DL to sense and amplify the output data received through the output line IO and the inverted output line IOb and output the data data to the data line DL.

The operating time of the sense amplifier circuit 20 is influenced by the data loading time of the output line IO and the inverted output line IOb. As the memory capacity of the semiconductor memory device increases, the number of page buffers increases, thereby increasing the number of page buffers connected to the output line IO and the inverted output line IOb. As a result, the operating time of the sense amplifier circuit 20 is increased, thereby increasing the data output time.

In order to reduce the data output time, the number of sense amplifier circuits must be increased to reduce the number of page buffers connected to one sense amplifier circuit. As the number of sense amplifier circuits increases, the data line must increase, and a circuit size and a signal for controlling the data line increase, resulting in a problem of increasing chip size.

The present invention provides a data output circuit of a semiconductor memory device capable of reducing the drive time of the sense amplification circuit to reduce the data output time, thereby reducing the number of data lines and thus improving chip integration.

To this end, the present invention provides a first sense amplifying circuit connected to a first page buffer group among a plurality of page buffers corresponding to one page of a memory block, and a first connected to a second page buffer group among the plurality of page buffers. A second sense amplifier circuit, and a mux circuit coupled between the first and second sense amplifier circuits and an external data line.

Page buffers of the first page buffer group are connected to an internal data line of the first sense amplifier circuit, and page buffers of the second page buffer group are connected to an internal data line of the second sense amplifier circuit.

The first sense amplifier circuit and the second sense amplifier circuit perform a sensing operation at different times.

The first sense amplifier circuit and the second sense amplifier circuit output data sensed at different times to the external data line.

The second sense amplifier circuit is connected to the external data line in the sensing operation of the first sense amplifier circuit, and the first sense amplifier circuit is connected to the external data line in the sensing operation of the second sense amplifier circuit.

The MUX circuit connects the second sensing amplifier circuit and the external data line in the sensing operation of the first sensing amplifier circuit, and the first sensing amplifier circuit and the external data in sensing operation of the second sensing amplifier circuit. Connect the line.

In addition, the present invention provides a plurality of output lines respectively connected to a plurality of page buffers, and a plurality of first to nth sense amplifier circuits connected to each of the first to nth output lines by grouping the plurality of output lines into first to nth output lines. And a mux circuit connected between the first to nth sense amplifying circuits and the data line.

The first to nth sense amplifier circuits are connected to the data line at different times.

When any one of the first to nth sense amplifier circuits is connected to the data line, the other sense amplifier circuits perform a sensing operation.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below, but to those skilled in the art It is preferred that the present invention be interpreted as being provided to more fully explain the present invention.

2 is a block diagram illustrating a data output circuit of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 2, a data output circuit of a semiconductor memory device includes a first sense amplifier circuit 210, a second sense amplifier circuit 220, and a mux circuit 300.

The internal data line IO and the inverted internal data line IOb of the first sense amplifier circuit 210 may include a first page buffer group among a plurality of page buffers corresponding to one page of a memory block of the semiconductor memory device. Connected with 110. That is, the first page buffer group 110 among the plurality of page buffers corresponding to each bit line of the memory block is connected. The internal data line IO and the inverted internal data line IOb of the second sense amplifier circuit 220 may include a second page buffer group among a plurality of page buffers corresponding to one page of a memory block of the semiconductor memory device. Connected with 120. That is, the second page buffer group 120 is connected among the plurality of page buffers corresponding to each bit line of the memory block.

 According to an exemplary embodiment of the present invention, a plurality of page buffers corresponding to one page may be divided into a first page buffer group 110 and a second page buffer group 120, and the first and second sense amplifying circuits corresponding to each group ( Although 210 and 220 are disposed, a plurality of page buffers may be grouped into three or more so that one sense amplifier circuit corresponds to one page buffer group. As a result, the number of page buffers connected to the internal data line IO and the inverted internal data line IOb of one sense amplifier circuit is reduced. For example, when the number of sense amplifier circuits is n (n is a natural number of 1 or more), the number of page buffers connected with one sense amplifier circuit is reduced to the number of total page buffers / n.

Since the internal data line IO and the inverted internal data line IOb of the first sense amplifier circuit 210 are connected to the page buffer of the first page buffer group 110 of the plurality of page buffers, the first sense amplifier circuit ( The operation time of 210 is reduced compared with the case where a plurality of page buffers corresponding to one page are connected. Also, since the internal data line IO and the inverted internal data line IOb of the second sense amplifier circuit 220 are connected to the page buffer of the second page buffer group 120 of the plurality of page buffers, the second sense amplifier circuit The operation time of 220 is reduced than when connected to a plurality of page buffers corresponding to one page.

The first sense amplifier circuit 210 and the second sense amplifier circuit 220 perform sensing operations at different times and perform data output operations at different times. More specifically, during the sensing operation of the first sense amplifier circuit 210, the second sense amplifier circuit 220 performs a data output operation, and during the sensing operation of the second sense amplifier circuit 220, the first sense amplifier circuit ( 210 proceeds with the data output operation. When the number of sense amplifier circuits is three or more, when one sense amplifier circuit performs a data output operation, it is preferable that the other sense amplifier circuits perform a sensing operation. This is because the mux circuit 300 can connect one sense amplifier circuit to the data line.

The mux circuit 300 is connected between the first and second sense amplifier circuits 210 and 220 and the external data line DL, and the first sense amplifier circuit 210 and the external data line during an output operation of the semiconductor memory device. DL or the second sense amplification circuit 220 and an external data line DL. That is, one sensing amplifier circuit of the plurality of sensing amplifier circuits is selected and connected to the external data line DL.

In the sensing operation of the first sensing amplifier circuit 210, the MUX circuit 300 connects the second sensing amplifier circuit 220 to an external data line DL to output an output sensed by the second sensing amplifier circuit 220. Output data to a data line. In the sensing operation of the second sensing amplifier circuit 220, the first sensing amplifier circuit 210 is connected to the external data line DL to output output data sensed by the first sensing amplifier circuit 210 to the external data line. Output in (DL). As described above, since the first sense amplifying circuit 210 and the second sense amplifying circuit 220 are connected to the external data line DL by using the MUX circuit 300, even if the number of sense amplifying circuits is increased, the data line is increased. The number of DLs does not increase.

Referring to FIG. 2, a method of operating a data output circuit of a semiconductor memory device according to an embodiment of the present invention will be described below.

The first sense amplifying circuit 210 senses read data stored in the page buffer of the first page buffer group 110 through the internal data line IO and the inverted internal data line IOb.

Subsequently, when the sensing operation of the first sense amplifier circuit 210 is completed, the second sense amplifier circuit 220 includes the second page buffer group 120 through the internal data line IO and the inverted internal data line IOb. Sense read data stored in the page buffer.

In this case, the MUX circuit 300 connects the first sense amplifier circuit 210 and the external data line DL to transmit read data sensed by the first sense amplifier circuit 210 to the external data line DL.

When the sensing operation of the second sense amplification circuit 220 is completed, the MUX circuit 300 connects the second sense amplification circuit 220 and the external data line DL to be sensed by the second sense amplification circuit 220. The read data to the external data line DL.

The present invention is not limited to the above-described embodiments, but may be implemented in various forms, and the above embodiments are intended to complete the disclosure of the present invention and to completely convey the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.

1 is a block diagram showing a data output circuit of a semiconductor memory device according to the prior art.

2 is a block diagram illustrating a data output circuit of a semiconductor memory device according to an embodiment of the present invention.

DESCRIPTION OF THE RELATED ART [0002]

110, 120: first and second page buffer groups

IO, IOb: output line and inverted output line

210, 220: first and second sense amplifier circuits

300: mux circuit

DL: data line

Claims (13)

Sense amplifying circuits each connected to at least two or more page buffer groups obtained by grouping a plurality of page buffers corresponding to bit lines of a memory block; And And a mux circuit configured to select one of the sense amplifier circuits and to connect an external data line. The method according to claim 1, And page buffers included in the page buffer group are connected to internal data lines of the sense amplifier circuit. The method according to claim 1, And the sensing amplifier circuits perform sensing operations at different times. The method according to claim 1, And other sense amplifier circuits perform a sensing operation while one of the sense amplifier circuits is connected to the external data line. A first sense amplifier circuit coupled with a first page buffer group of a plurality of page buffers corresponding to one page of a memory block; A second second sense amplifier circuit connected to a second page buffer group of the plurality of page buffers; And And a mux circuit connected between the first and second sense amplifier circuits and an external data line. The method according to claim 5, The page buffers of the first page buffer group are connected to an internal data line of the first sense amplifier circuit, and the page buffers of the second page buffer group are connected to an internal data line of the second sense amplifier circuit. Data output circuit. The method according to claim 5, And the first sense amplifier circuit and the second sense amplifier circuit perform sensing operations at different times. The method according to claim 5, And the first sense amplifier circuit and the second sense amplifier circuit output data sensed at different times to the external data line. The method according to claim 5, The second sense amplifier circuit is connected to the external data line in the sensing operation of the first sense amplifier circuit, and the first sense amplifier circuit is connected to the external data line in the sensing operation of the second sense amplifier circuit. Data output circuit of the memory device. The method according to claim 5, The MUX circuit connects the second sense amplifier circuit and the external data line during a sensing operation of the first sense amplifier circuit. And a data output circuit of the semiconductor memory device connecting the first sense amplifier circuit and the external data line during a sensing operation of the second sense amplifier circuit. A plurality of output lines, each connected with a plurality of page buffers; First to n-th sense amplifier circuits grouping the plurality of output lines into first to n-th output lines and connected to the first to n-th output lines; And And a mux circuit connected between the first to nth sense amplifier circuits and a data line. The method of claim 11, And the first to n-th sense amplifier circuits are connected to the data line at different times. The method of claim 11, And the other sense amplifier circuits perform a sensing operation when any one of the first to nth sense amplifier circuits is connected to the data line.
KR1020090135614A 2009-12-31 2009-12-31 Data output circuit of semiconductor memory device KR20110078732A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9036433B2 (en) 2013-05-31 2015-05-19 SK Hynix Inc. Data transfer circuit and memory including the same
US9147482B2 (en) 2012-12-17 2015-09-29 SK Hynix Inc. Data transmission circuit, memory including the same, and data transmission method
US9190176B2 (en) 2012-05-22 2015-11-17 SK Hynix Inc. Memory device with redundancy page buffer array

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9190176B2 (en) 2012-05-22 2015-11-17 SK Hynix Inc. Memory device with redundancy page buffer array
US9147482B2 (en) 2012-12-17 2015-09-29 SK Hynix Inc. Data transmission circuit, memory including the same, and data transmission method
US9036433B2 (en) 2013-05-31 2015-05-19 SK Hynix Inc. Data transfer circuit and memory including the same

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