KR20070066501A - Data ordering and organization method of memory device - Google Patents

Abstract

A method for ordering and organizing data in a memory device are provided to output data at a high speed by forming data ordering/organization in one control block. A memory cell block arranges a plurality of memory cells. Data line sense amplifiers detect and amplify memory cell data output from the memory cell block. The first control block(320) organizes an output data bit by ordering a sequence of the outputs of the data line sense amplifiers in response to the first ordering/multiplexing signal. The first control block is equipped with a plurality of ordering/multiplexing parts(321-324) receiving a pair of outputs of the data line sense amplifiers and determining whether the output of the received data line sense amplifiers is the first or the fifth output. The second control block(330) organizes the output data bit by ordering the sequence of the outputs of the first control block in the response to the second ordering/multiplexing signal.

Description

Data ordering and organization method of memory device

1 is a block diagram illustrating a conventional memory device.

2A and 2B are diagrams illustrating data alignment by the first to fourth control blocks of FIG. 1.

3 is a block diagram illustrating a memory device according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating data alignment by the first and second control blocks of FIG. 3.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a method of data ordering and configuration of a synchronous memory device.

The synchronous memory device inputs and outputs memory cell data in synchronization with a clock signal. Referring to the read operation of the memory cell data, the memory cell data is sensed and amplified by the bit line sense amplifier and the data line sense amplifier, and then output to the data pad through the data output buffer.

In general, in a synchronous memory device, the number of data bits input and output simultaneously to the pads, that is, the data band whiskey is specified as X4, X8, X16, X32, and the like. To satisfy these various data bands, the number of memory cell data bits output from the data line sense amplifier is larger than the number of data bits simultaneously output to the pad. For example, for the data band X8 operation, the number of data bits output from the data line sense amplifier may be set to X16.

In order to output the number of data bits corresponding to X16 inside the memory device to the number of X8 data bits outside the memory device, a data ordering method for ordering data is required. In addition, a data organization method is required to output the ordered data to the pad.

1 is a block diagram illustrating a conventional memory device. Referring to this, the memory cell data DATA of the memory device 100 is controlled by the first control block 120, the second control block 130, the third control block 140 through the data line sense amplifier 110. The pad pin 160 is output to the pad pin 160 through the fourth control block 150. Alignment of the memory cell data DATA by the first to fourth control blocks 120 to 150 is described with reference to FIG. 2.

2A and 2B, the first control block 120 outputs the outputs D0-D3 of the group of data line sense amplifiers 110 (FIG. 1) in response to the first ordering signal to the first to fourth data. And outputs D4-D7 of the two groups of data line sense amplifiers 110 (FIG. 1) to the first to fourth data.

The second control block 130 orders the outputs of the first control block 120 as first to eighth data in response to the secondary ordering signal. The second control block 130 transmits two groups of first to eighth data 1st-8th Data_U and 1st-8th Data_L to the third control block 140.

The third control block 140 reconfigures the outputs of the second control block 130 in response to the first multiplexing signal and determines whether to output the result to X8. The fourth control block 150 reconfigures the outputs of the third control block 150 in response to the second multiplexing signal and determines whether to output the result to X4.

The memory device 100 has a problem in that it takes a long time until the memory cell data is output to the pin due to delays in the respective control blocks 120-150.

It is an object of the present invention to provide a memory device that implements simplified data ordering and data organization.

Another object of the present invention is to provide a data ordering and data configuration method of the memory device.

In order to achieve the above object, a memory device according to an aspect of the present invention includes a memory cell block in which a plurality of memory cells are arranged, data line sense amplifiers for sensing and amplifying memory cell data output from the memory cell block, and 1 And a first control block that orders the outputs of the data line sense amplifiers in response to the order ordering and multiplexing signals to configure the output data bits.

According to embodiments of the present invention, the first control block inputs two outputs of the data line sense amplifier as a pair, and determines a plurality of whether to determine whether the input of the input data line sense amplifier is first or fifth. And ordering and multiplexing units.

According to embodiments of the present invention, the first control block may configure the output data bit configuration of the memory device as X16 or X8.

According to embodiments of the present disclosure, the memory device may further include a second control block configured to output data bits by ordering the outputs of the first control block in response to the secondary ordering and multiplexing signal.

According to embodiments of the present invention, the second control block orders first, second, third, and fourth data output from the first control block in response to the second ordering and multiplexing signal, and the first control. It may include an ordering and multiplexing unit for ordering the fifth data output from the block to the fifth, sixth, seventh, and eighth order.

According to embodiments of the present invention, the second control block may configure the output data bit configuration of the memory device as X4.

In order to achieve the above object, a memory device according to another aspect of the present invention is a memory cell block arranged a plurality of memory cells, data line sense amplifiers for sensing and amplifying the memory cell data output from the memory cell block, 1 A first control block for inputting two outputs of the data line sense amplifier as a pair in response to the difference ordering and multiplexing signal and determining whether the input of the input data line sense amplifier is first or fifth; In response to the second ordering and multiplexing signal, the first, second, third, and fourth data are output from the first control block and the fifth, fifth, and fifth data are output from the first control block. And a second control block that orders eighth.

In order to achieve the above object, a data ordering and configuration method of a memory device according to another aspect of the present invention comprises the steps of (a) sensing and amplifying a plurality of memory cell data, and in response to the first ordering and multiplexing signal (B) inputting two amplified data as a pair and determining whether the order of the sensed amplified data is first or fifth; and firstly outputting data in response to the second ordering and multiplexing signal. (C) ordering the 1,2,3,4th order and the fifth, sixth, seventh, and eighth ordered data output from the first control block in response to the second ordering and multiplexing signal. (d) step.

According to embodiments of the present invention, step (b) may configure the output data bit configuration of the memory device as X16 or X8, and step (c) or (d) may set the output data bit configuration of the memory device as X4. It can be configured as.

Therefore, in the memory device of the present invention, since data ordering and data configuration are performed by one control block, high-speed data output is possible.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings that describe exemplary embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a simplified block diagram of a memory device according to an embodiment of the present invention. Referring to this, the memory device 300 may include a data line sense amplifier 310 for inputting memory cell data DATA, a first control block 320 in response to a first ordering and multiplexing signal, a second ordering and multiplexing signal. And a second control block 330 in response to the pad pin 340.

FIG. 4 is a block diagram illustrating the memory device 300 of FIG. 3 in detail. Referring to this, the first control block 320 determines whether the data order is first or fifth in response to the first ordering and multiplexing signal. The first control block 320 determines which data to output to the pin 340 in the case of X16 or X8.

For example, a case in which eight outputs of the data line sense amplifier 310 are illustrated in FIG. 3 will be described. The unit 321 determines whether the data order is first or fifth. The first and second data line sense amplifiers 310 outputs D2 and D3 are determined by the first ordering and multiplexing unit 322 to determine whether the data order is first or fifth. The first and second data line sense amplifiers 310 outputs D4 and D5 are determined by the first ordering and multiplexing unit 323 to determine whether the data order is first or fifth. The first and second data line sense amplifiers 310 outputs D6 and D7 are determined by the first ordering and multiplexing unit 324 whether the data order is first or fifth.

The second control block 330 is configured to order the output order of the first data output from the first control block 320 in response to the second ordering and multiplexing signal, and is output from the first control block 320. Configure the order of output of the fifth data. The second control block 330 data orders the first data output from the first control block 320 to 1,2,3,4, and the fifth data output from the first control block 320 is 5, Data is ordered at Nos. 6, 7, and 8 to determine which data is to be output to pin 340 in the case of X4.

The memory device 300 performs data ordering and data configuration through the first control block 320 in the case of X8 or X16 and through the first and second control blocks 320 and 330 in the case of X4. Accordingly, the memory device 300 can output high speed data as compared with a memory device having a plurality of control blocks.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

In the memory device of the present invention described above, since data ordering and data configuration are made by one control block, high-speed data output is possible.

Claims (12)

A memory cell block in which a plurality of memory cells are arranged; Data line sense amplifiers for sensing and amplifying memory cell data output from the memory cell block; And And a first control block for ordering outputs of the data line sense amplifiers in response to a first ordering and multiplexing signal to configure output data bits. The method of claim 1, wherein the first control block is And a plurality of ordering and multiplexing units configured to input two outputs of the data line sense amplifier as a pair, and determine whether the input of the input data line sense amplifier is the first or fifth. Memory device. The method of claim 2, wherein the first control block is And configure the output data bit configuration to X16 or X8. The memory device of claim 1, wherein the memory device And a second control block configured to configure the output data bits by ordering the outputs of the first control block in response to a second ordering and multiplexing signal. The method of claim 4, wherein the second control block is In response to the second ordering and multiplexing signal, first, first, second, third, and fourth data output from the first control block are ordered, and fifth, fifth, and fifth data are output from the first control block. And a seventh and eighth ordering and multiplexing unit. The method of claim 5, wherein the second control block is And configure the output data bit configuration to X4. A memory cell block in which a plurality of memory cells are arranged; Data line sense amplifiers for sensing and amplifying memory cell data output from the memory cell block; A first control block for inputting two outputs of the data line sense amplifier as a pair and determining whether the output of the input data line sense amplifier is first or fifth in response to a first ordering and multiplexing signal; And In response to the second ordering and multiplexing signal, first, first, second, third, and fourth data output from the first control block are ordered, and fifth, fifth, and fifth data are output from the first control block. And a second control block which orders seventh and eighth. The method of claim 7, wherein the first control block is And an output data bit configuration of the memory device as X16 or X8. The method of claim 7, wherein the second control block is And an output data bit configuration of the memory device as X4. In the data ordering and configuration method of the memory device, (A) sensing and amplifying a plurality of memory cell data; In response to a first ordering and multiplexing signal, inputting the two sensed amplified data as a pair and determining whether the order of the sensed amplified data is first or fifth; (C) ordering the first output data first, second, third and fourth in response to a second ordering and multiplexing signal; And And (d) ordering the fifth, fifth, sixth, and eighth data output from the first control block in response to the second ordering and multiplexing signal. And configuration method. The method of claim 10, wherein step (b) And an output data bit configuration of the memory device as X16 or X8. The method of claim 10, wherein step (c) or step (d) And configuring the output data bit configuration of the memory device as X4.

Images