TWI493569B - Memory device and method for reading data from memeory device - Google Patents

Description

Memory device and method for reading data from memory device

The present invention relates to a memory device, and more particularly to a memory device having a high speed reading function.

1 is a schematic diagram showing a conventional one memory device 100. The memory device 100 includes a memory cell array 110 and a sense amplifier 160. A plurality of pieces of data, for example, bytes 0-7, are stored in the memory cell array 110. The memory cell array 110 includes a plurality of word lines 111, 112 and a plurality of bit lines to select an address of the data. When an external device wants to read data from the memory cell array 110, only one word line can be selected in one sensing cycle, otherwise an error will occur. For example, if word lines 111, 112 are selected at the same time, sense amplifier 160 will not be able to distinguish that the read data is from byte 0 or byte 4. Therefore, the reading speed of the conventional memory device 100 will be limited.

The present invention provides a memory device, comprising: a first memory cell array comprising a plurality of first word lines and a plurality of first bit lines, wherein the plurality of first data are stored in the first memory cell array; The second memory cell array is separated from the first memory cell array and includes a plurality of second word lines and a plurality of second bit lines, wherein the plurality of second data are stored in the second memory cell array; a control logic circuit , allowed at the same time or in an overlapping time Selecting one of the first word lines and one of the second word lines, and alternately selecting one of the first address of the first memory cell array and one of the second memory cell array And an address of the first corresponding portion of the first data and a second corresponding portion of the second data are alternately read from the first memory cell array and the second memory cell array; a first sense amplifier coupled to the first memory cell array via the first bit lines and amplifying the first corresponding portion of the first data; and a second sense amplifier via the first sense amplifier The second bit line is coupled to the second memory unit array and amplifies the second corresponding portion of the second data.

In addition, the present invention provides a method of reading data from a memory device, comprising the steps of: providing a first memory cell array, wherein the first memory cell array comprises a plurality of first word lines and a plurality of first bits a plurality of first data is stored in the first memory cell array; a second memory cell array is provided, wherein the second memory cell array includes a plurality of second word lines and a plurality of second bit lines, the The second memory cell array is separated from the first memory cell array, and the plurality of second data is stored in the second memory cell array; and one of the first word lines is selected at the same time or in an overlapping time And one of the second word lines; alternately selecting one of the first address of the first memory cell array and the second address of the second memory cell array from the first memory cell array and Interleaving a first corresponding portion of the first data and a second corresponding portion of the second data in the second memory cell array; and amplifying the first corresponding portion of the first data Share And the second part corresponding to those of the second data.

100, 200‧‧‧ memory devices

110, 210, 220‧‧‧ memory cell array

111, 112, 211, 212, 221, 222‧‧ ‧ character lines

160, 260, 270‧‧ ‧ sense amplifier

215, 216, 225, 226‧ ‧ bit lines

250‧‧‧Control logic

280‧‧‧Data multiplexer

290‧‧‧Displacement register

CLK‧‧‧ clock signal

Corresponding parts of S1, S2‧‧‧ data

SA1, SA2, 410-1, 410-2, ..., 410-7‧‧‧ addresses

SE1, SE2‧‧‧ sensing enable signal

SIN‧‧‧ input signal

SOUT‧‧‧Output data

T1, T2‧‧‧ sensing time

1 is a schematic view showing a conventional memory device; FIG. 2 is a schematic view showing a memory device according to an embodiment of the present invention; and FIG. 3A is a view showing a first memory according to an embodiment of the present invention; Schematic diagram of a cell array and a second memory cell array; FIG. 3B is a schematic diagram showing a first memory cell array and a second memory cell array according to another embodiment of the present invention; FIG. 4A is a view showing an implementation according to the present invention; FIG. 4B is a signal waveform diagram of a memory device according to another embodiment of the present invention; and FIG. 5 is a diagram showing a signal waveform of a memory device according to another embodiment of the present invention; A flowchart of a method of reading data in a memory device; FIG. 6A is a schematic diagram showing a first memory cell array and a second memory cell array according to an embodiment of the invention; and FIG. 6B is a diagram showing A schematic diagram of a first memory cell array and a second memory cell array according to another embodiment.

2 is a schematic diagram showing a memory device 200 according to an embodiment of the invention. The memory device 200 can be a NOR flash memory, but is not limited thereto. As shown in FIG. 2, the memory device 200 includes a first memory cell array 210, a second memory cell array 220, a control logic circuit 250, a first sense amplifier 260, and a second sense amplifier 270. Data multiplexer 280, and a shift register 290.

The first memory cell array 210 is separated from the second memory cell array 220. The plurality of first data (eg, a byte) is stored in the first memory cell array 210, and the second data (eg, a byte) is stored in the second memory cell array 220. The combination of these first materials and the second materials is complete and continuous. However, in some embodiments, the first data stored in the first memory cell array 210 and the second data stored in the second memory cell array 220 are discontinuous data. The first memory cell array 210 includes a plurality of first word lines 211, 212 and a plurality of first bit lines 215, 216. The first sense amplifier 260 is coupled to the first memory cell array 210 via the first bit lines. The second memory cell array 220 also includes a plurality of second word lines 221, 222 and a plurality of second bit lines 225, 226. The second sense amplifier 270 is coupled to the second memory cell array 220 via the second bit lines. In a read process, the aforementioned word line and bit line are used to select the address of any memory cell array. To simplify the drawing, not all of the word lines and bit lines are shown in Figure 2. It should be understood that each memory cell array in this embodiment may include more word lines and bit lines.

Control logic circuit 250 is for reading the first data from first memory cell array 210 and reading the second data from second memory cell array 220. In some embodiments, control logic circuit 250 receives an input signal SIN indicating one of the start addresses of any of the memory cell arrays, and control logic circuit 250 then performs a read procedure from the start address. During the read process, control logic circuit 250 may allow one of the first word lines and one of the second word lines to be selected at an identical time or in an overlap time By. For example, the first word line 211 of the first memory cell array 210 and the second word line 221 of the second memory cell array 220 can be selected at the same time. Since the first memory cell array 210 is separated from the second memory cell array 220, the selection of one first word line is independent of the selection of the other second word line, and the sense amplifiers 260, 270 can be confusingly Distinguish the data read. In a preferred embodiment, the control logic circuit 250 alternately selects one of the first address unit SA1 of the first memory cell array 210 and the second address address SA2 of the second memory cell array 220 to be from the first memory cell array. The first corresponding portion S1 of the first data and the second corresponding portion S2 of the second data are alternately read by the 210 and the second memory cell array 220. It must be noted that each corresponding part may include one or more pieces of data. Next, the first sense amplifier 260 amplifies the read first corresponding portion S1, and the second sense amplifier 270 amplifies the read second corresponding portion S2. The data multiplexer 280 is coupled to the first sense amplifier 260 and the second sense amplifier 270. The data multiplexer 280 selectively transmits the amplified first corresponding portion S1 and the amplified second corresponding portion S2 to the shift register 290. The shift register 290 sequentially generates the plurality of output data SOUT according to the first corresponding portion S1 and the second corresponding portion S2.

In more detail, the control logic circuit 250 further receives a clock signal CLK. After the control logic circuit 250 receives the input signal SIN indicating the start address, the control logic circuit 250 transmits the sense enable signals SE1, SE2 to initiate the read process. The detailed operational flow of the memory device 200 will be described in the following embodiments.

FIG. 3A is a schematic diagram showing a first memory cell array 210 and a second memory cell array 220 according to an embodiment of the invention. As shown in Figure 3A The first data stored in the first memory cell array 210 includes discontinuous bits 0, 2, 4, and 6, and the second data stored in the second memory cell array 220 includes Successive bytes 1, 3, 5, 7. Each tuple can be viewed as a piece of information. The combination of the first data and the second data may form complete information including consecutive bytes 0 through 7. To simplify the drawing, Figure 3A does not show all the bytes, but it must be understood that each memory cell array can store more bytes.

FIG. 4A is a diagram showing signal waveforms of the memory device 200 according to an embodiment of the invention. Please refer to Figure 2, Figure 3A, and Figure 4A together. If the input signal SIN has been received, it is necessary to spend several dummy cycles (Dummy Cycles) to initialize a read program before generating the output data SOUT. The addresses 410-0 to 410-7 in Figure 4A (all addresses are not shown) correspond to the bytes 0 to 7 in Figure 3A, respectively. As shown in FIG. 4A, during the read process, the control logic circuit 250 alternately selects the first address SA1 of the first memory cell array 210 (eg, addresses 410-0, 410-2, 410-4). a second address SA2 of the second memory cell array 220 (eg, one of the addresses 410-1, 410-3, 410-5, 410-7) to The memory cell array 210 and the second memory cell array 220 alternately read the first corresponding portion S1 of the first data (eg, one of the bytes 0, 2, 4, and 6) and the second The second corresponding portion of the data S2 (for example, one of the bytes 1, 3, 5, 7). Even if the first data stored and the stored second data are discontinuous, the output data SOUT may be complete and continuous data. In this embodiment, each time the first address SA1 (for example, the address 410-2) is selected, the number of data of the first corresponding portion S1 (for example, byte 2) read is 1, and Whenever the second address is SA2 (for example: bit When the address 410-3) is selected, the number of data of the second corresponding portion S2 (for example, byte 3) read is also 1. For example, in FIG. 3A, if the first word line 211 is selected, one of the first data (eg, byte 2) will be read; and if the second word line 221 is selected. Then, one of the second materials (eg, byte 3) will be read, wherein the first word line 211 and the second word line 221 can be selected at the same time or an overlapping time. In this embodiment, the first address SA1 and the second address SA2 are both increased by 2 every two clock cycles. A sensing time T1 is used to read the first corresponding portion S1 (for example: byte 2) or to read the second corresponding portion S2 (for example: byte 3), except during the initialization process, The maximum value of the sensing time T1 is two clock cycles. In contrast, the maximum value of one of the sensing times of the conventional memory device 100 shown in FIG. 1 is one clock period. Thus, the embodiment shown in Figures 2, 3A, and 4A will provide a faster read speed that is about twice the conventional read speed.

FIG. 3B is a schematic diagram showing the first memory cell array 210 and the second memory cell array 220 according to another embodiment of the present invention. As shown in FIG. 3B, the first data stored in the first memory cell array 210 includes discontinuous bits 0, 1, 4, and 5, and are stored in the second memory cell array 220. The second data includes discontinuous bits 2, 3, 6, and 7. Each tuple can be viewed as a piece of information. The combination of the first data and the second data may form complete information including consecutive bytes 0 through 7. In order to simplify the drawing, Figure 3B does not show all the bytes, but it must be understood that each memory cell array can store more bytes. Figure 3B is similar to Figure 3A in that the difference between the two is that, in Figure 3B, any two adjacent bytes stored in each memory cell array (e.g., byte 0, 1) may be continuous data. This design method will be able to enter one The reading speed of the memory device 200 is accelerated step by step.

Fig. 4B is a diagram showing signal waveforms of the memory device 200 according to another embodiment of the present invention. Please refer to Figure 2, Figure 3B, and Figure 4B together. If the input signal SIN has been received, it is necessary to spend several virtual cycles to initialize a read program before generating the output data SOUT. The addresses 410-0 to 410-7 (not all addresses are shown) in Fig. 4B correspond to the bytes 0 to 7 in Fig. 3B, respectively. As shown in FIG. 4B, during the read process, the control logic circuit 250 alternately selects the first address SA1 of the first memory cell array 210 (eg, one of the addresses 410-0, 410-4). And a second address SA2 of the second memory cell array 220 (eg, one of the addresses 410-2, 410-6) to be interleaved from the first memory cell array 210 and the second memory cell array 220 a first corresponding portion S1 of the first data (eg, byte 0, 1, or a byte 4, 5) and a second corresponding portion S2 of the second data (eg, a byte) 2, 3, or byte 6, 7). Even if the first data stored and the stored second data are discontinuous, the output data SOUT may be complete and continuous data. In this embodiment, each time the first address SA1 (for example, the address 410-4) is selected, the number of data of the first corresponding portion S1 (for example, the bytes 4, 5) read is 2 And each time the second address SA2 (for example, the address 410-6) is selected, the number of data of the second corresponding portion S2 (for example, the bytes 6, 7) read is also 2. For example, in FIG. 3B, if the first word line 212 is selected, then consecutive two of the first data (eg, bytes 4, 5) will be read together; and if the second is selected Word line 222, then consecutive two of the second data (eg, bytes 6, 7) will be read together, wherein the first word line 212 and the second word line 222 can be at the same time Or selected during an overlapping time. In this embodiment, the first address SA1 and the second address SA2 are both It increases by 4 every four clock cycles. A sensing time T2 is used to read the first corresponding portion S1 (eg, byte 4, 5) or to read the second corresponding portion S2 (eg, byte 6, 7), except for initialization Outside of the process, the maximum value of the sensing time T2 is four clock cycles. In contrast, the maximum value of one of the sensing times of the conventional memory device 100 shown in FIG. 1 is one clock period. Thus, the embodiment shown in Figures 2, 3B, and 4B will provide a faster read speed that is approximately four times the conventional read speed.

Figure 5 is a flow chart showing a method of reading data from a memory device in accordance with an embodiment of the present invention. First, in step S510, a first memory cell array is provided, wherein the first memory cell array includes a plurality of first word lines and a plurality of first bit lines, and the plurality of first data is stored in the first memory cell array in. In step S520, a second memory cell array is provided, wherein the second memory cell array includes a plurality of second word lines and a plurality of second bit lines, and the second memory cell array is separated from the first memory cell array, and The plurality of second data are stored in the second memory cell array. In step S530, one of the first word lines and one of the second word lines are selected at the same time or in an overlap time. In step S540, one of the first address of the first memory cell array and one of the second address of the second memory cell array are alternately selected to be interleaved from the first memory cell array and the second memory cell array. And reading a first corresponding portion of the first data and a second corresponding portion of the second data. Finally, in step S550, the first corresponding portion of the first data and the second corresponding portion of the second data are enlarged. It is worth noting that none of the above method steps need to be performed sequentially. For the embodiments related to Figures 2, 3A, 3B, 4A, and 4B, all of the detailed features can be applied to the square shown in Figure 5. In the law.

Although described above, in each memory cell array, each word line corresponds to only two bytes, but the present invention is not limited thereto. FIG. 6A is a schematic diagram showing a first memory cell array 210 and a second memory cell array 220 according to an embodiment of the invention. As shown in Fig. 6A, in each memory cell array, each word line can correspond to four bytes, and the design of Fig. 6A can produce a similar signal waveform as the embodiment of Fig. 4A. FIG. 6B is a schematic diagram showing the first memory cell array 210 and the second memory cell array 220 according to another embodiment of the present invention. As shown in FIG. 6B, in each memory cell array, each word line can correspond to four bytes, and the design of FIG. 6B can produce a similar signal waveform as the embodiment of FIG. 4B. It should be noted that the present invention can be applied to various memory cell arrays, for example, each word line corresponds to 2, 4, 8, 16, 32, 64, 128, 256, or even more bits. A memory cell array of tuples.

The ordinal numbers in this specification and the scope of the patent application, such as "first", "second", "third", etc., have no sequential relationship with each other, and are only used to indicate that two are identical. Different components of the name.

The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

Claims (18)

A memory device includes: a first memory cell array including a plurality of first word lines and a plurality of first bit lines, wherein the plurality of first data are stored in the first memory cell array; and a second memory unit An array, separated from the first memory cell array, and including a plurality of second word lines and a plurality of second bit lines, wherein the plurality of second data are stored in the second memory cell array; a control logic circuit allows Selecting one of the first word lines and one of the second word lines at the same time or in an overlap time, and interlacing one of the first address of the first memory cell array and the a second address of the second memory cell array for interleaving the first corresponding portion of the first data and the second data from the first memory cell array and the second memory cell array a second corresponding portion; a first sense amplifier coupled to the first memory cell array via the first bit lines, and amplifying the first corresponding portion of the first data; Two sense amplifiers And a second bit line coupled to the second memory cell array and amplifying the second corresponding portion of the second data; a data multiplexer; and a shift register, wherein the data multiplexer Is coupled to the first sense amplifier and the second sense amplifier, the data multiplexer selectively transmitting the first corresponding portion and the second corresponding portion to the displacement register, and the displacement The register sequentially generates the complex output data according to the first corresponding portion and the second corresponding portion. The memory device of claim 1, wherein the first address and the second address are increased by 2 every two clock cycles. The memory device of claim 1, wherein a sensing time is used to read the first corresponding portion or to read the second corresponding portion, and the maximum value of the sensing time For two clock cycles. The memory device of claim 1, wherein each time the first address is selected, the number of data of the first corresponding portion read is 1, and each time the second address is When selected, the number of data of the second corresponding portion read is 1. The memory device of claim 1, wherein the first address and the second address are increased by 4 every four clock cycles. The memory device of claim 1, wherein a sensing time is used to read the first corresponding portion or to read the second corresponding portion, and the maximum value of the sensing time For four clock cycles. The memory device of claim 1, wherein each time the first address is selected, the number of data of the first corresponding portion read is 2, and each time the second address is When selected, the number of data of the second corresponding portion read is 2. The memory device of claim 1, wherein the first data stored in the first memory cell array and the second data stored in the second memory cell array are discontinuous data. The memory device of claim 1, wherein the combination of the first data and the second data is complete continuous data. A method of reading data from a memory device, comprising the steps of: Providing a first memory cell array, wherein the first memory cell array includes a plurality of first word lines and a plurality of first bit lines, and the plurality of first data is stored in the first memory cell array; providing a second a memory cell array, wherein the second memory cell array includes a plurality of second word lines and a plurality of second bit lines, the second memory cell array is separated from the first memory cell array, and the plurality of second data systems are stored in the In the second memory cell array, selecting one of the first word lines and one of the second word lines at the same time or in an overlap time; interleaving the first memory cell array a first address and a second address of the second memory cell array to alternately read the first corresponding portion of the first data from the first memory cell array and the second memory cell array And a second corresponding portion of one of the second materials; amplifying the first corresponding portion of the first data and the second corresponding portion of the second data; by means of a data multiplexer, Selectively transfer the ranking The first corresponding portion of the data and the second corresponding portion of the second data to a displacement register; and the displacement register, according to the first corresponding portion and the second corresponding portion The plurality of output data are sequentially generated. A method for reading data from a memory device as described in claim 10, wherein the first address and the second address are both increased by 2 every two clock cycles. Reading data from a memory device as described in claim 10 The method includes a sensing time for reading the first corresponding portion or for reading the second corresponding portion, and the maximum value of the sensing time is two clock cycles. The method for reading data from a memory device as described in claim 10, wherein each time the first address is selected, the number of data of the first corresponding portion read is one, and Whenever the second address is selected, the number of data of the second corresponding portion read is one. The method for reading data from a memory device according to claim 10, wherein the first address and the second address are increased by 4 every four clock cycles. A method for reading data from a memory device as described in claim 10, wherein a sensing time is used to read the first corresponding portion or to read the second corresponding portion, The maximum value of the sensing time is four clock cycles. The method for reading data from a memory device as described in claim 10, wherein each time the first address is selected, the number of data of the first corresponding portion read is 2, and Whenever the second address is selected, the number of data of the second corresponding portion read is 2. The method for reading data from a memory device according to claim 10, wherein the first data stored in the first memory cell array and the first memory cell array are stored in the second memory cell array The second data is a discontinuous data. A method for reading data from a memory device as described in claim 10, wherein the combination of the first data and the second data is complete Continuous data.