KR20110121350A - Semiconductor memory device and operating method thereof - Google Patents

Semiconductor memory device and operating method thereof Download PDF

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Publication number
KR20110121350A
KR20110121350A KR1020100040909A KR20100040909A KR20110121350A KR 20110121350 A KR20110121350 A KR 20110121350A KR 1020100040909 A KR1020100040909 A KR 1020100040909A KR 20100040909 A KR20100040909 A KR 20100040909A KR 20110121350 A KR20110121350 A KR 20110121350A
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KR
South Korea
Prior art keywords
global data
write
read
data lines
memory device
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KR1020100040909A
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Korean (ko)
Inventor
박기천
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020100040909A priority Critical patent/KR20110121350A/en
Publication of KR20110121350A publication Critical patent/KR20110121350A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes

Abstract

A semiconductor memory device having a plurality of global data lines for transferring a plurality of data, the method comprising: a plurality of write global data lines and a plurality of read globals respectively disposed between the plurality of write global data lines A semiconductor memory device comprising a data line and a plurality of read line driving means for driving the plurality of read global data lines to a predetermined voltage level during a write operation.

Description

Semiconductor memory device and its operation method {SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device having a plurality of global data lines for transferring a plurality of data.

In general, a plurality of memory cells are provided in a semiconductor memory device including a double data rate synchronous DRAM (DDR SDRAM), and the number of memory cells also increases rapidly as the degree of integration increases. Thus, a semiconductor memory device having a plurality of memory cells performs a write and read operation under the control of an external chip set, thereby storing data in the corresponding memory cell or outputting data stored in the memory cell. . At this time, the data is transferred through the global data line corresponding to the write and read operations. In other words, data input from an external device during a write operation is stored as a memory cell through a write global data line (WGL), and data stored in the memory cell during a read operation is read global data line (WGL). Is output to the outside through RGL).

As described above, the global data line is divided into a write global data line (WGL) used in a write operation and a read global data line (RGL) used in a read operation. In general, the write global data line (WGL) and the read global data line (RGL) are disposed in the peri region, and the interference between data transmitted through the write global data line (WGL) and the read global data line (RGL) is maintained. In order to minimize, a read global data line RGL is disposed between the plurality of write global data lines WGL.

FIG. 1 is a view for explaining a layout of a general write global data line WGL and a read global data line RGL. For convenience of description, three write global data lines WGL1, WGL2, and WGL3 are shown. The read global data lines RGL1, RGL2, RGL3 will be described as an example.

Referring to FIG. 1, first to third read global data lines RGL1, RGL2, and RGL3 are disposed between the first to third write global data lines WGL1, WGL2, and WGL3. For reference, in the write operation, the first to third read global data lines RGL1, RGL2, and RGL3 are generally driven by previous data by a latch having a very small driving force. The reason why the latch is designed to have a very small driving force is to prevent the driving force of the latch from the data input through the first to third read global data lines RGL1, RGL2, and RGL3 during the read operation. to be.

On the other hand, as the size of the semiconductor memory device becomes smaller these days, the size of the ferry region also decreases. The smaller size of the ferry region means that the interval between the first to third write global data lines WGL1, WGL2, and WGL3 and the first to third read global data lines RGL1, RGL2, and RGL3 become smaller. . This shorter gap between global data lines causes the following problems.

FIG. 2 is a waveform diagram illustrating an operation waveform of the global data line of FIG. 1 during a write operation of the semiconductor memory device. For convenience of description, it is assumed that the first to third write global data lines WGL1, WGL2, and WGL3 are toggled by a write operation.

Referring to FIG. 2, the first read global data line RGL1 is smallly toggled by a coupling phenomenon caused by the first write global data line WGL1, and the second read global data line RGL2 is small. And second read global data lines RGL3 are largely toggled by first and second write global data lines WGL1 and WGL2 and second and third write global data lines WGL2 and WGL3 disposed adjacent to both sides. You can see it ringing. This toggling causes unnecessary operation in other circuits receiving this signal, which means unnecessary power consumption. In other words, it is common to have a repeater in the middle of a global data line having a long loading. Therefore, when the first to third read global data lines RGL1, RGL2, and RGL3 toggle as described above, the repeater performs an unwanted amplification operation, which causes unnecessary power consumption.

In addition, this toggling phenomenon causes cross talk between write global data lines, which makes it difficult to secure circuit stability.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and an object thereof is to provide a semiconductor memory device capable of preventing a toggle of a plurality of read global data lines during a write operation.

Another object of the present invention is to provide a semiconductor memory device in which a read global data line may serve as a shielding function in driving a global data line during a write operation.

In accordance with an aspect of the present invention, a semiconductor memory device includes: a plurality of write global data lines; A plurality of read global data lines respectively disposed between the plurality of write global data lines; And a plurality of read line driving means for driving the plurality of read global data lines to a predetermined voltage level during a write operation.

A method of operating a semiconductor memory device according to another aspect of the present invention for achieving the above object is a method of operating a semiconductor memory device having a plurality of read global data lines respectively disposed between a plurality of write global data lines. Driving the plurality of read global data lines to a predetermined voltage level and driving the plurality of write global data lines in response to input data corresponding to successive write operations; And driving the read global data line in response to output data in a read operation.

In the semiconductor memory device according to the embodiment of the present invention, it is possible to prevent unnecessary toggling by driving a plurality of read global data lines at a predetermined voltage level during a write operation. In addition, in driving a plurality of write global data lines in a write operation, a read global data line driven at a predetermined voltage level may serve as a shielding line corresponding to the plurality of write global data lines.

The present invention prevents unnecessary power consumption by preventing toggling of a plurality of read global data lines during a write operation.

In addition, in the present invention, since a plurality of read global data lines serve as shielding lines in response to a plurality of write global data lines during a write operation, it prevents cross-talk phenomenon of the plurality of write global data lines, thereby ensuring stability of the semiconductor memory device. The effect can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram for explaining the arrangement of a general write global data line WGL and a read global data line RGL.
FIG. 2 is a waveform diagram illustrating an operation waveform of the global data line of FIG. 1 during a write operation of the semiconductor memory device. FIG.
3 is a block diagram illustrating a part of a configuration of a semiconductor memory device according to an embodiment of the present invention.
4 is a circuit diagram for describing the read line driving unit 350 of FIG. 3.
5 is a waveform diagram illustrating a circuit operation of a semiconductor memory device according to an embodiment of the present invention.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3 is a block diagram illustrating a part of a configuration of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 3, the semiconductor memory device may include a pad 310, a write line driving unit 320, a write driving unit 330, a sense amplifier 340, a read line driving unit 350, and A pipe latching portion 360 is provided.

In the write operation of the semiconductor memory device, the write line driving unit 320 drives the write global data line WGL in response to data input through the pad 310, and the write driving unit 330 writes the write global data line ( It receives data transmitted through WGL) and drives positive / negative local I / O lines (LIO, / LIO). For reference, the data transferred to the positive / negative local input / output lines LIO and / LIO are transferred to a memory cell (not shown), and the semiconductor memory device performs a write operation on the memory cell through the operation. . For reference, the sense amplifier 340 is deactivated during the write operation.

During the read operation of the semiconductor memory device, the sense amplifier 340 senses and amplifies data of a memory cell transferred through positive / negative local input / output lines LIO and / LIO, and the read line driving unit 350 detects and amplifies the data. The read global data line RGL is driven in response to the output signal of 340. Subsequently, the pipe latching unit 360 aligns and outputs a plurality of data transferred through the read global data line RGL to the pad 310.

The semiconductor memory device may drive the read global data line RGL at a predetermined voltage level during a write operation. To this end, the read line driving unit 350 receives a write control signal CTR_WT that is activated during a write operation and drives the read global data line RGL to a predetermined voltage level in response to the write control signal CTR_WT. It is possible.

FIG. 4 is a circuit diagram illustrating the read line driving unit 350 of FIG. 3.

3 and 4, the read line driving unit 350 may include an input unit 410 for receiving first and second data DATH and DATL, and a driving unit for driving the read global data line RGL. 420 and a controller 430 for controlling the driver 420 in response to the write control signal CTR_WT. Here, the first and second data DATH and DATL are signals output from the sense amplifier 340, and operation waveforms during the write operation and the read operation will be described again with reference to FIG. 5.

Hereinafter, a brief operation of the read line driving unit 350 will be described.

First, during the read operation, the sense amplifier 340 detects data transmitted through the positive / negative local input / output lines LIO and / LIO to activate the first data DATH or the second data DATL. During the read operation, the write control signal CTR_WT becomes logic 'low', and the second data DATL is transferred to the driver 420 via the controller 340. Therefore, when the first data DATH is activated, the read global data line RGL is driven to logic 'high', and when the second data DATL is activated, the read global data line RGL is logic. It is driven low.

Next, during the write operation, the sense amplifier 340 is deactivated, and the write control signal CTR_WT becomes logic 'high'. Thus, the NMOS transistor of the driver 420 is turned on and the read global data line RGL is driven to logic 'low'.

The semiconductor memory device according to an embodiment of the present invention acts as a shielding line corresponding to a plurality of write global data lines disposed adjacent thereto by driving the read global data line RG to logic 'low' during a write operation. Perform. In the first embodiment, the NMOS transistor of the driver 420 is controlled in response to the write control signal CTR_WT. However, the PMOS transistor of the driver 420 may be controlled according to the design. It is also possible to directly drive the global data line RGL.

5 is a waveform diagram illustrating a circuit operation of a semiconductor memory device according to an embodiment of the present invention.

3 to 5, when a write command WT is continuously input during a write operation, the write line driving unit 320 writes a global data line WGL in response to different data input through the pad 310. ). In this case, the write control signal CTR_WT maintains logic 'high' and the driver 420 of the read line driving unit 350 drives the read global data line RGL to logic 'low'. Therefore, in the embodiment of the present invention, since the coupling phenomenon does not occur in the read global data line RGL during the write operation, it is possible to prevent power consumption caused by the coupling phenomenon. In addition, since the read global data line RGL serves as a shielding line from the standpoint of the write global data lines, the write global data lines do not cause cross talk.

On the other hand, when a read command RD is input during a read operation, the sense amplifier 340 generates the first data DATH and the second data DATL corresponding to the data stored in the memory cell. Thereafter, the read line driving unit 350 drives the read global data line RGL to logic 'high' in response to the first data DATH, and the read global data line RGL latches it. Subsequently, the read line driving unit 350 drives the read global data line RGL to logic 'low' in response to the second data DATL, and the read global data line RGL latches it. In this case, since the write control signal CTR_WT becomes logic 'low', the driving unit 420 of the read line driving unit 350 may be driven according to the first data DATH and the second data DATL.

As described above, the semiconductor memory device according to the embodiment of the present invention drives the read global data line RGL to a predetermined voltage level during a write operation. Therefore, it is possible to prevent toggling of the read global data line RGL during a write operation, which means that unnecessary power consumption can be prevented. In addition, many write global data lines having read global data lines (RGLs) interposed therebetween do not cause crosstalk because the read global data lines (RGLs) serve as shielding lines. It is possible to secure.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

In addition, the position and type of the logic gate and the transistor illustrated in the above-described embodiment should be implemented differently according to the polarity of the input signal.

310: pad 320: writing line driving unit
330: Write driving unit 340: Detection amplifier
350: reading line driving unit 360: pipe latching unit

Claims (7)

Multiple write global data lines;
A plurality of read global data lines respectively disposed between the plurality of write global data lines; And
A plurality of read line driving means for driving the plurality of read global data lines to a predetermined voltage level during a write operation
A semiconductor memory device having a.
The method of claim 1,
The plurality of read line driving means,
A driver for driving the plurality of read global data lines in response to data input during a read operation; And
And a controller for controlling the driver in response to a write control signal activated during the write operation.
The method of claim 2,
The control unit transfers the input data to the drive unit during the read operation.
The method of claim 1,
And a plurality of write line driving means for driving the plurality of write global data lines in response to data input during the write operation.
The method of claim 1,
A plurality of write driving means for driving corresponding local input / output lines among the plurality of local input / output lines in response to data transmitted through the plurality of write global data lines; And
And a plurality of sense amplifying means for sense amplifying data transmitted through the plurality of local input / output lines and outputting the sensed amplification data to the plurality of read line driving units.
A method of operating a semiconductor memory device having a plurality of read global data lines respectively disposed between a plurality of write global data lines,
Driving the plurality of read global data lines to a predetermined voltage level and driving the plurality of write global data lines in response to input data corresponding to successive write operations; And
Driving the read global data line in response to output data in a read operation
Method of operating a semiconductor memory device comprising a.
The method of claim 6,
And latching the plurality of read global data lines during the read operation.
KR1020100040909A 2010-04-30 2010-04-30 Semiconductor memory device and operating method thereof KR20110121350A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10157651B2 (en) 2015-09-04 2018-12-18 SK Hynix Inc. Semiconductor device for driving data line by using different voltages

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10157651B2 (en) 2015-09-04 2018-12-18 SK Hynix Inc. Semiconductor device for driving data line by using different voltages

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