KR100988811B1 - Semiconductor memory device - Google Patents

Abstract

The present invention relates to a semiconductor memory device for controlling data transfer by dividing a global data line into a shared routing area and a separate routing area. The present invention includes a first global line for transmitting data on the same line during read and write operations; A repeater that regulates read data and write data transmission between the first global line and the bank; A second write global line for transmitting the write data transferred from the repeater to a write driver of a bank; And a second lead global line transferring the read data transferred from the bank to the repeater. According to this aspect, the present invention reduces the loading load of the global data line, thereby reducing the amount of current consumed and at the same time increasing the operation speed.

Semiconductors, Memory Devices, Global Data Lines

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to a semiconductor memory device for controlling data transfer by dividing a global data line into a shared routing area and a separate routing area.

The semiconductor memory device includes a global data line (GIO), which is an input / output data line for data transfer between a data input / output pad and a memory cell region, and a local data line that receives an output of a bit line sensing amplifier output in the memory cell region ( LIO) is provided. In general, a semiconductor memory device has a plurality of bank structures. In the semiconductor memory device configured as described above, the read / write operation of data is controlled through the global data line in order to transfer or import data input / output from the input / output pad to a plurality of banks.

1 illustrates a routing structure of a global data line in a general semiconductor memory device.

The illustrated semiconductor memory device is configured to share and use global data lines during write and read operations throughout the entire region. Therefore, all banks have a structure in which one line is partially allocated and used.

According to this structure, the loading capacitance of the global data line is increased, so that a relatively large driver is required to drive the global data line. In addition, a problem arises in that a driving current for driving a global data line also increases.

Although not shown in another embodiment, there is a method of separately using the global data line used in the read operation process and the global data line used in the read operation process. However, this separation method has a problem in that the required global data line becomes complicated and the required space increases.

Accordingly, an object of the present invention is to provide a semiconductor memory device that can be controlled by dividing a global data line used in a semiconductor memory device into a shared routing area and a separate routing area.

According to another aspect of the present invention, there is provided a semiconductor memory device including: a global data line configured to transmit data on the same line during read and write operations; A repeater that regulates read data and write data transfer between the global data line and the bank; A write global data line transferring write data transferred from the repeater to a write driver of a bank; And a read global data line transferring read data transferred from the bank to the repeater.

In addition, the semiconductor memory device according to another embodiment of the present invention, the global data line for transmitting data on the same line during the read and write operations; A plurality of repeaters for controlling read data and write data transmission between the global data lines and the plurality of banks; A write global data line configured to transmit write data transmitted from each repeater to a write driver of a corresponding bank; And a read global data line transferring read data transferred from each bank to a corresponding repeater.

According to the present invention, a first global data line connected to a ferry area is shared and used during read and write (read and write) data transmission, and a second global data line connected between the ferry area and a bank area is read and written. Independently using the data line. According to this aspect, the present invention reduces the loading load of the global data line, thereby reducing the amount of current consumed and at the same time increasing the operation speed.

Hereinafter, a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.

The present invention is characterized by controlling the global data line divided into a shared routing area and a separate routing area. That is, the global data line of the chip center portion (ferry region) is configured as a shared routing region, and the global data lines connected to the bank at the chip center are configured as separate routing regions.

In the case of the chip center part, the space where all signals for chip operation are provided is followed by space constraints, and since the operation control signal is provided as a whole of the chip, the global data lines in this part are shared. Here, the definition of sharing indicates that the global data lines present in this section are commonly used in all banks.

However, in the portion connected to each bank in the chip center portion, the space constraint is relatively small, and since data input / output is performed only in relation to each bank, the global data line in this portion is separated. The definition of separate here indicates that the global data lines exist independently between the chip center and each bank and are used separately.

In general, a semiconductor memory device is largely composed of a cell array, a row path and its control logic, a column path and its control logic, a data path and its control logic. Among these, the row path and its control logic, the column path and its control logic, and the data path and its control logic are also called peri regions. Therefore, the chip center portion can be described as the ferry region.

2 is an overall block diagram of a semiconductor memory device according to an embodiment of the present invention.

As shown, the present invention consists of a plurality of banks BANK0, BANK1, .... The global data line GIO is used to transfer data for writing to a plurality of banks and data read from the banks.

Meanwhile, in the embodiment of the present invention, the global data line includes a write global line (WGIO) 280 for data transmission to the write driver WDRV which writes data to the bank 210 during a write operation. In the read operation, a read global line RGIO 280 that amplifies and transfers data read from the bank 210 in the input / output sense amplifier IOSA is included. The light global line and the lead global line are independently operated between the light driver WDRV and the input / output sense amplifier IOSA and the repeater 230 described later.

The global data line includes a global data line 270 configured as the same line in a write operation and a read operation to perform data transmission. The global data line 270 is commonly operated during the read / write operation between the repeater 230 and the data input / output unit 210 described later.

The repeater 120 includes a plurality of repeaters, and when a read / write operation is performed on an arbitrary bank, the repeater connected to the corresponding bank is turned on to control data transmission between the global data lines 270 and 280.

The data input / output unit 210 transmits data input into the semiconductor memory device through the pad 220 to the global data line 280, and transmits data transmitted from the global data line 280 to the pad 220. ) Is output to the outside of the semiconductor memory device.

The control signal generator 200 performs a control to enable a repeater to operate among a plurality of repeaters. The control signal generator 200 may use a mode register set (MRS) that is frequently used in a semiconductor memory device.

In the embodiment shown in FIG. 2, the case where only a large number of banks are provided is described as an example. In this case, therefore, one repeater is applied to one bank.

However, FIG. 3 to be described below shows an example of the case where the banks provided are located at the top and the bottom of the semiconductor memory design.

As shown in FIG. 2, the bank has a structure in which a plurality of banks are positioned above and below. In this case, one repeater is used to control data input and output for the upper and lower banks.

The semiconductor memory device configured as described above has a structure including a plurality of banks 110 to 113, ... as shown. In addition, a shared global data line 181 is provided at a chip center portion of the memory device. In the chip center portion connected to each bank, separate global data lines 180 and 182 are provided.

A plurality of repeaters (REPEATER; 120, 121,...) Capable of turning on / off are connected to a portion connecting the shared global data line 181 and the separated global data lines 180 and 182. That is, according to the on / off operation of the repeater 120, the global data lines connected to the respective banks in the chip center portion are driven or not driven. By selectively adjusting the global data line operated by such a control operation, the loading load according to the driving of the global data line is minimized.

Since the functions of the control signal generator 300, the data input / output unit 310, the pad 320, and the like are the same as those of FIG. 2, redundant descriptions are omitted, and detailed descriptions according to the embodiments will be described in detail with reference to the following drawings. do.

4 is a detailed block diagram of the repeater according to the first embodiment of the present invention. In the following description, a relationship between one repeater 120 and the upper bank 110 and the lower bank 111 connected to the repeater will be described as an example.

According to the first embodiment of the present invention, the repeater 120 is divided into a repeater part for reading operation control and a repeater part for writing operation control. The shared global data line 181 is commonly used in both reading and writing operations. The global data line 181 transfers data to or receives data from the data input / output unit 210 illustrated in FIG. 3.

The separated global data line 180 is connected to the upper bank 110 and includes a line RGIO_UP for reading data in a reading operation and a line WGIO_UP for writing data in a writing operation. The separated global data line 182 is connected to the lower bank 111 and includes a line RGIO_DN for reading data in a reading operation and a line WGIO_DN for writing data in a writing operation.

The repeater 120 generates a first signal generator 190 for amplifying the reading signal read from the upper bank 110 and a second signal generation for amplifying the reading signal read from the lower bank 111. A third signal generator 197 for generating a signal for writing a writing signal in the upper bank 110, and a fourth for generating a signal for writing a writing signal in the lower bank 111. Signal generation unit 185 is included.

In addition, the repeater 120 latches the signals of the first and second signal generators 190 and 194 to transmit them to the shared global data line 181, and inverts the signals input through the shared global data line 181. The latch unit 188 may further include a configuration of the latch unit 188 provided to the third and fourth signal generators 197 and 185. Accordingly, the signals generated by the first and second signal generation units 190 and 194 are inverted through the latch unit 188 and provided to the shared global data line 181, and are input through the shared global data line 181. The signal is inverted through the latch unit 188 and input to the third and fourth signal generators 197 and 185.

The latch unit 188 latching the data may include an inverter for inverting the data generated by the first and second signal generators 190 and 194 and transferring the data to the global data line, and inverting the data transmitted from the global data line for the third data. 4 may be configured as an inverter for transmitting to the signal generators 197 and 185.

The control signals input to the first, second, third, and fourth signal generators 190, 194, 197, and 185 are signals provided by the control signal generator 300 of FIG. 3. That is, the control signal generator 300 enables the RGIO_ONOFF_UP signal to control the first signal generator 190 in an activated state. The control signal generator 300 enables the RGIO_ONOFF_DN signal to control the second signal generator 194 in an activated state. The control signal generator 300 enables the WGIO_ONOFF_UP signal to control the third signal generator 197 in an activated state. In addition, the control signal generator 300 enables the WGIO_ONOFF_DN signal to control the fourth signal generator 185 in an activated state. Therefore, the control signal generation unit 200 predetermines the state of the output control signal according to the bank address, the input command, and the like by using an MRS, and then enters the predetermined state according to the input bank address and the input command. It is desirable to control the output control signal.

The first signal generation unit 190 may include an activation unit 192 for enabling an operation of the first signal generation unit 190 in response to the control signal RGIO_ONOFF_UP signal provided by the control signal generation unit 300, and a global unit. And a driver 191 for amplifying and driving the data input from the data line RGIO_UP 180. The driver 191 includes a PMOS transistor 130 and an NMOS transistor 141 connected in series between a supply power source and a ground power source. The PMOS transistor 131 and the NMOS transistor 140 are further connected in series between two transistors constituting the driving unit 191, and the two transistors 131 and 140 constitute an activation unit 192. An output terminal is constructed from the drain terminal between the two transistors 131 and 140.

According to the above configuration, the data transmitted from the global data line RGIO_UP 180 is amplified in response to the control signal RGIO_ONOFF_UP. That is, a current pass path is formed between the power supply voltage VDD line and the PMOS transistor 131 in response to data transmitted from the inverter 150 and the global input / output line RGIO_UP that inverts the control signal RGIO_ONOFF_UP. PMOS transistor 130 and PMOS transistor 131 forming a current path path between PMOS transistor 130 and an output terminal in response to a signal output from inverter 150, an output terminal and an N in response to control signal RGIO_ONOFF_UP. The NMOS transistor 140 forming a current path path between the NMOS transistor 141 and the NMOS transistor 140 and the ground voltage VSS line in response to data transmitted from the global input / output line RGIO_UP. The NMOS transistor 141 forms a current path path therebetween. The output terminal of the first signal generator is connected to the shared global data line 181.

In addition, the second signal generation unit 194 may include an activation unit 196 for enabling the operation of the second signal generation unit 194 in response to the control signal RGIO_ONOFF_DN signal provided by the control signal generation unit 300; And a driver 195 for amplifying and driving data input from the global data line RGIO_DN 182. The driver 195 includes a PMOS transistor 135 and an NMOS transistor 144 connected in series between a supply power source and a ground power source. The PMOS transistor 134 and the NMOS transistor 145 are further connected in series between two transistors constituting the driving unit 195, and the two transistors 134 and 145 constitute an activation unit 196. The output stage is constructed from the drain stage between the two transistors.

According to the above configuration, in response to the data transmitted from the inverter 152 and the global input / output line RGIO_DN 182 that inverts the control signal RGIO_ONOFF_DN, a current path path is provided between the ground power supply VSS line and the NMOS transistor 145. An NMOS transistor 144 to form, an NMOS transistor 145 forming a current path path between the NMOS transistor 144 and an output terminal in response to a control signal RGIO_ONOFF_DN, and an output terminal in response to an output signal of the inverter 152. PMOS transistor 134 forming a current path path between PMOS transistor 135 and between PMOS transistor 134 and power supply voltage VDD line in response to data transferred from global input / output line RGIO_DN. The PMOS transistor 135 may form a current path path. The output terminal of the second signal generator is connected to the shared global data line 181.

The third signal generator 197 may include an activation unit 199 for enabling the operation of the third signal generator 197 in response to the control signal WGIO_ONOFF_UP signal provided by the control signal generator 300, and a global signal. And a driver 198 for amplifying and driving the data to be transferred to the data line WGIO_UP 180. The driver 198 includes a PMOS transistor 132 and an NMOS transistor 143 connected in series between a supply power source and a ground power source. The PMOS transistor 133 and the NMOS transistor 142 are further connected in series between two transistors constituting the driver 198, and the two transistors 133 and 142 constitute an activation unit 199. An output terminal is constructed from the drain terminal between the two transistors 133 and 142.

According to the above configuration, in response to the control signal WGIO_ONOFF_UP, a writing signal corresponding to the data transmitted from the shared global data line RGIO 181 is generated. That is, a current path path is provided between the power supply voltage VDD line and the PMOS transistor 133 in response to data transmitted from the inverter 151 and the global input / output line GIO 181 which inverts the control signal WGIO_ONOFF_UP. PMOS transistor 132 to form, PMOS transistor 133 to form a current path path between the PMOS transistor 132 and the output terminal in response to the signal output from the inverter 151, the output terminal in response to the control signal WGIO_ONOFF_UP And the NMOS transistor 142 forming a current path path between the NMOS transistor 143 and the NMOS transistor 142 and the ground voltage in response to data transmitted from the global input / output line (GIO) 181. And the NMOS transistor 143 forming a current pass path between the (VSS) lines. The output terminal of the third signal generator is connected to a separate global data line 180 that provides a writing signal to the upper bank 116.

In addition, the fourth signal generation unit 185 may include an activation unit 186 for enabling the operation of the fourth signal generation unit 185 in response to the control signal WGIO_ONOFF_DN signal provided by the control signal generation unit 300; And a driver 187 for amplifying and driving data input from the global data line WGIO_DN 182. The driver 187 includes a PMOS transistor 137 and an NMOS transistor 146 connected in series between a supply power supply and a ground power supply. The PMOS transistor 136 and the NMOS transistor 147 are further connected in series between two transistors constituting the driving unit 187, and the two transistors 136 and 147 constitute the activator 186. The output terminal is configured from the drain terminal between the two transistors 136 and 147.

According to the above configuration, a current pass path is provided between the ground voltage VSS line and the NMOS transistor 147 in response to data transmitted from the inverter 153 and the global input / output line GIO 181 inverting the control signal WGIO_ONOFF_DN. An NMOS transistor 146 to form, an NMOS transistor 147 forming a current path path between the NMOS transistor 146 and the output terminal in response to the control signal WGIO_ONOFF_DN, and an output terminal in response to the output signal of the inverter 153. PMOS transistor 136 forming a current path path between PMOS transistor 137 and PMOS transistor 136 and power supply voltage VDD line in response to data transmitted from global input / output line (GIO) 181. The PMOS transistor 137 may form a current path path therebetween. The output terminal of the fourth signal generator is connected to a separate global data line 182 that provides a writing signal to the lower bank 117.

The operation control process of the global data line in the read / write operation process in the semiconductor memory device having the above configuration is as follows.

First, the reading operation of the bank 110 will be described.

When the bank BANK0 read command is generated by an external command and an address, data stored in the corresponding memory cell of the bank 110 is amplified by the input / output sense amplifier IOSA and transferred to the global input / output line RGIO_UP 180. At this time, when the data is high level, the global input / output line RGIO_UP rises to a high level.

In addition, the control signal RGIO_ONOFF_UP generated by the control signal generator 300 is enabled. The enabled control signal is inverted via the inverter 150 to provide a low signal to the gate terminal of the PMOS transistor 131. In this operation, the PMOS transistor 131 is turned on. Also, the enabled control signal provides a high signal to the gate terminal of the NMOS transistor 140. This operation also turns on the NMOS transistor 140.

The high level data transmitted from the global input / output line RGIO_UP 180 is applied to the gate terminals of the PMOS transistor 130 and the NMOS transistor 141 so that the PMOS transistor 130 is controlled to be in an off state. The NMOS transistor 141 is controlled in an on state.

Therefore, the remaining transistors 131, 140, and 141 except for the PMOS transistor 130 are controlled to be in an on state. However, since the PMOS transistor directly connected to the supply power supply VDD has an off state, a low level is applied to the output terminal of the first signal generator 190. The low signal output from the output terminal of the first signal generator 190 is inverted via the latch unit 188 to become a high level signal. As a result, the high level data read from the upper bank 110 is shared globally. Is transmitted to the data line 181.

As such, the signal read from the upper bank 110 is input to the repeater 120 through an independent global data line 180 existing between the upper bank 110 and the repeater 120, and the repeater 120 After the amplification through the data input / output unit 310 and the input / output pad 220 via the shared global data line (GIO) 181 is output to the outside.

In the read operation of the bank 110, only one repeater 120 has an operational state among the plurality of repeaters configured on the shared global data line 181, and all other repeaters have an inoperative state. . To this end, the control signal generator 200 adjusts the control signal RGIO_ONOFF_UP supplied to the repeater 120 to be active among the plurality of repeaters to the enabled state, and all other control signals to the disabled state. do.

In addition, only the configuration of the first signal generator 190 controlled by the control signal RGIO_ONOFF_UP in the repeater 120 has an active state, and the second, third, and fourth signal generators 194, 197, and 185 which are controlled by other control signals. ) Has an off state. By such control, only the global data line 181 and the global data line 180 between the bank 110 and the repeater 120 are loaded in the operation process of the first signal generator 190. All other separate global data lines are in the floating state. Therefore, it is possible to reduce the loading load of the global data line in the operating state, thereby reducing the operating current of the global data line.

To this end, the control signal generator 200 selects a control signal to be enabled according to a bank address, an input command, and the like, and supplies the control signal to the corresponding repeater. For example, when a bank address corresponding to the bank BANK0 and a read command are provided to the control signal generator 200 from the outside, the control signal generator 200 generates the first signal in the repeater 120. The control signal RGIO_ONOFF_UP for controlling the unit 190 to the active state is controlled to the enabled state. Therefore, the control signal generation unit 200 predetermines the state of the output control signal according to the bank address, the input command, and the like by using an MRS, and then enters the predetermined state according to the input bank address and the input command. It is desirable to control the output control signal.

Next, a writing operation process of writing data in the bank 110 will be described.

When the bank 110 write command is generated by an input command and a bank address input from the outside, data is input into the memory chip through the input / output pad 220 and the data input / output unit 210. Data input through the input / output pad is input through the shared global data line 181. The data input to the global data line 181 is inverted by the latch unit 188 and then input to the repeater 120. Therefore, when the data input through the input / output pad is in the high level state, the data input to the repeater 120 is in the low level state.

At the same time, the control signal WGIO_ONOFF_UP is enabled (high level). The enabled control signal is inverted via the inverter 151 to provide a low signal to the gate terminal of the PMOS transistor 133. In this operation, the PMOS transistor 133 is turned on. Also, the enabled control signal provides a high signal to the gate terminal of the NMOS transistor 142. In this operation, the NMOS transistor 142 is also turned on.

The low level data input to the repeater 120 is applied to the gate terminals of the PMOS transistor 132 and the NMOS transistor 143 so that the PMOS transistor 132 is controlled in an on state and the NMOS transistor is in an ON state. 143 controls the off state.

Accordingly, the remaining transistors 132, 133, and 142 except for the NMOS transistor 143 are controlled to be in an on state. Therefore, the power supplied to the supply power supply VDD is provided to the output terminal through the transistors in the on state. Therefore, a high level is applied to the output terminal of the third signal generator. The high level signal output from the output terminal of the third signal generator is output to the separated global data line 180. In this way, the externally input data is output through the independent global data line 180 and recorded in the bank 110.

In the writing operation of the bank 110, only the repeater 120 configured on the shared global data line 181 has an operating state, and all other repeaters have an inoperative state. To this end, the control signal generator 200 adjusts the control signal WGIO_ONOFF_UP supplied to the repeater 120 to be active among the plurality of repeaters to the enabled state, and all other control signals to the disabled state. do.

In addition, only the configuration of the third signal generator 197 under the control of the control signal WGIO_ONOFF_UP in the repeater 120 has an operating state, and the first, second, and fourth signal generators under the control of other control signals ( 190, 194, and 185 have an off state. By such control, only the global data line 181 and the global data line 180 between the bank 116 and the repeater 120 are loaded while the third signal generator 197 is in operation. All other separate global data lines are in the floating state. Therefore, it is possible to reduce the loading load of the global data line in the operating state, thereby reducing the operating current of the global data line.

To this end, the control signal generator 200 selects a control signal to be enabled according to a bank address, an input command, and the like, and supplies the control signal to the corresponding repeater. For example, when a bank address corresponding to a bank BANK0 and a write command are provided to the control signal generator 200 from the outside, the control signal generator 200 may be a third signal generator in the repeater 120. The control signal WGIO_ONOFF_UP for controlling (197) to the active state is controlled to the enabled state. Therefore, the control signal generation unit 200 predetermines the state of the output control signal according to the bank address, the input command, and the like by using an MRS, and then enters the predetermined state according to the input bank address and the input command. It is desirable to control the output control signal.

Next, Fig. 4 shows a detailed circuit of the repeater according to the second embodiment of the present invention.

The illustrated embodiment is a control configuration that shares the reading and writing operations of two banks. In this case the two banks would preferably share the upper side bank and the lower side bank. In the following description, a relationship between one repeater 120 and the upper bank 110 and the lower bank 111 connected to the repeater will be described as an example.

According to the second embodiment of the present invention, the repeater 120 is divided into a repeater part for reading operation control and a repeater part for writing operation control. The shared global data line 181 is commonly used in both reading and writing operations.

The separated global data line 180 is connected to the banks 110 and 111, and is a line RGIO that reads data from the two banks during a reading operation. The separated global data line 182 is connected to the banks 110 and 111 and is a line WGIO for writing data during a writing operation.

The repeater 120 generates a first signal generator 170 for amplifying a reading signal read from the banks 110 and 111 and a second signal generator for generating a signal for writing a writing signal to the banks 110 and 111. Part 175 is included.

In addition, the repeater 120 latches the signal of the first signal generator 170 and transmits the signal to the shared global data line 181, and inverts the signal input through the shared global data line 181. The latch unit 174 may further include a configuration of the latch unit 174 provided to the two signal generator 175. Accordingly, the signal generated by the first signal generator 170 is inverted through the latch unit 174 to be provided to the shared global data line 181, and the signal input through the shared global data line 181 is Inverted through the latch unit 174 is input to the second signal generation unit 175.

The latch unit 174 latching the data may include an inverter for inverting data generated by the first signal generator 170 and transferring the data to the global data line, and inverting data transmitted from the global data line to generate the second signal. It may be configured as an inverter for transferring to the unit 175.

The control signals input to the first and second signal generators 170 and 175 are signals provided by the control signal generator 300 of FIG. 3. That is, the control signal generator 300 enables the RGIO_ONOFF signal to control the first signal generator 170 in an activated state. The control signal generator 300 enables the WGIO_ONOFF signal to control the second signal generator 175 in an activated state. Therefore, the control signal generation unit 200 predetermines the state of the output control signal according to the bank address, the input command, and the like by using an MRS, and then enters the predetermined state according to the input bank address and the input command. It is desirable to control the output control signal.

The first signal generator 170 may include an activation unit 172 for enabling an operation of the first signal generator 170 in response to a control signal RGIO_ONOFF signal provided from the control signal generator 300, and a global signal generator. And a driver 171 for amplifying and driving the data input from the data line RGIO_UP 180. The driver 111 includes a PMOS transistor 160 and an NMOS transistor 171 connected in series between a supply power source and a ground power source. The PMOS transistor 161 and the NMOS transistor 170 are further connected in series between two transistors constituting the driving unit 171, and the two transistors 161 and 171 form the activator 172. The output stage is constructed from the drain stage between two transistors 161 and 172.

According to the above configuration, the data transmitted from the global data line RGIO 180 is amplified in response to the control signal RGIO_ONOFF. That is, a current pass path is formed between the power supply voltage VDD line and the PMOS transistor 161 in response to the data transmitted from the inverter 154 and the global input / output line RGIO that inverts the control signal RGIO_ONOFF. PMOS transistor 160, PMOS transistor 161 forming a current path path between PMOS transistor 160 and an output terminal in response to a signal output from inverter 154, an output terminal and an N in response to a control signal RGIO_ONOFF. The NMOS transistor 170 forming a current path path between the NMOS transistor 171, and the NMOS transistor 170 and the ground voltage VSS line in response to data transmitted from the global input / output line RGIO. The NMOS transistor 171 forms a current path path therebetween. The output terminal of the first signal generator 170 is connected to the shared global data line 181.

 The second signal generator 175 may include an activation unit 177 for enabling the operation of the second signal generator 175 in response to the control signal WGIO_ONOFF signal provided from the control signal generator 300, and global data. And a driver 176 for amplifying and driving the data to be transferred to the line WGIO_UP 180. The driver 176 includes a PMOS transistor 162 and an NMOS transistor 173 connected in series between a supply power source and a ground power source. The PMOS transistor 163 and the NMOS transistor 172 are further connected in series between two transistors constituting the driving unit 176, and the two transistors 163 and 172 constitute an activation unit 177. The output stage is constructed from the drain stage between two transistors 163 and 172.

According to the above configuration, a writing signal corresponding to the data transmitted from the shared global data line (GIO) 181 is generated in response to the control signal WGIO_ONOFF. That is, in response to the data transmitted from the inverter 155 and the global input / output line GIO 181, which inverts the control signal WGIO_ONOFF, a current path path is provided between the power supply voltage VDD line and the PMOS transistor 163. PMOS transistor 162 to form, PMOS transistor 163 to form a current path path between the PMOS transistor 162 and the output terminal in response to the signal output from the inverter 155, the output terminal in response to the control signal WGIO_ONOFF The NMOS transistor 172 forming a current path path between the NMOS transistor 173 and the NMOS transistor 172 and the ground voltage in response to data transmitted from the global input / output line (GIO) 181. The NMOS transistor 173 forms a current path path between the (VSS) lines. The output terminal of the second signal generator 175 is connected to a separate global data line 182 that provides a writing signal to the banks 116 and 117.

According to the above configuration, the operation process of the second embodiment of the present invention is the same as the first embodiment described above, but briefly described as follows.

The data read from the bank 110 or the bank 111 is amplified by the input / output sense amplifier (IOSA) and then input to the repeater 120 through the global data line 180. Thereafter, when a data read command of the banks 110 and 111 is generated by the read command and the bank address, the control signal generator 300 enables RGIO_ONOFF, which is a corresponding control signal according to the input read command and the bank address.

In the enable operation of the RGIO_ONOFF control signal, the repeater 120 is selectively activated, so that the read data transferred from the global input / output line RGIO 180 is amplified through the repeater 120 and then shared. A global input / output line (GIO) 181 is transmitted. The data input / output unit 210 and the input / output pad 220 connected to the global input / output line 181 are output to the outside.

On the contrary, the data input through the input / output pad 220 is transmitted to the global input / output line 181 through the data input / output unit 210. Data transmitted from the global input / output line 181 is input to the repeater 120. Thereafter, when a data write command of the banks 110 and 111 is generated by the write command and the bank address, the control signal generator 300 enables the corresponding control command WGIO_ONOFF according to the input write command and the bank address.

In the enable operation of the WGIO_ONOFF control signal, the repeater 120 is in an active state. Therefore, the data transmitted from the global input / output line 181 is amplified through the repeater 120 and then separated from the global input / output line 182. Is sent). Data is recorded by the write driver WDRV in the bank 110 or the bank 111.

The above-described preferred embodiment of the present invention has been disclosed for the purpose of illustration, and in controlling the global data line of the semiconductor memory device, some global data lines are controlled to be shared during read / write operations, and some global The data line may be applied to the control in an independent state. Therefore, those skilled in the art will be able to improve, change, substitute or add other embodiments within the technical spirit and scope of the present invention disclosed in the appended claims.

1 is a global data line routing structure diagram of a conventional semiconductor memory device;

2 is a block diagram of a semiconductor memory device according to an embodiment of the present invention;

3 is a block diagram illustrating a semiconductor memory device in accordance with another embodiment of the present invention;

4 is a detailed configuration diagram of the first embodiment of the repeater shown in FIG.

5 is a detailed configuration diagram of a second embodiment of the repeater shown in FIG.

Explanation of symbols on the main parts of the drawings

110 ~ 113, ...: Bank 120,121, ...: Repeater

130 to 137: PMOS transistor 140 to 147: NMOS transistor

181,182,183: global data line 300: control signal generator

310: data input / output unit 320: pad

Claims (15)

A global data line for transmitting data on the same line during read and write operations; A repeater that regulates read data and write data transfer between the global data line and the bank; A write global data line transferring write data transferred from the repeater to a write driver of a bank; And And a read global data line transferring read data transferred from the bank to the repeater. The method of claim 1, And a latch unit for latching data transmitted between the global data line and the repeater. The method of claim 1, Input and output pads for inputting and outputting data to and from the outside; And a data input / output unit configured to control data input / output between the input / output pad and the global data line. The method of claim 1, And a control signal generator for controlling the operation state of the repeater to an active state. A global data line for transmitting data on the same line during read and write operations; A plurality of repeaters for controlling read data and write data transmission between the global data lines and the plurality of banks; A write global data line configured to transmit write data transmitted from each repeater to a write driver of a corresponding bank; And And a read global data line transferring read data transferred from each bank to a corresponding repeater. The method of claim 5, And a latch unit for latching data transmitted between the global data line and the repeater. The method of claim 5, Input and output pads for inputting and outputting data to and from the outside; And a data input / output unit configured to control data input / output between the input / output pad and the global data line. The method of claim 5, And a control signal generator for controlling an operation state of the plurality of repeaters to an active state. The method of claim 8, And the control signal generator selects and controls a repeater to be controlled to an active state from among the plurality of repeaters by using a bank address and an input command. The method of claim 9, The repeater may include: a first signal generator configured to amplify the bank reading data transmitted through the read global data line and output the amplified bank data to the global data line; And a second signal generator configured to output the bank writing data transmitted through the global data line to the write global data line. The method of claim 9, The plurality of banks are divided into an upper side and a lower side, And the plurality of repeaters are commonly used for the upper bank and the lower bank. The method of claim 11, The repeater may include: a first signal generator configured to amplify the upper bank reading data transmitted through the lead global data line and output the amplified bank data to the global data line; A second signal generator for amplifying the lower bank reading data transmitted through the read global data line and outputting the amplified bank data to the global data line; A third signal generation unit configured to output upper bank writing data transmitted through the global data line to the write global data line; And a fourth signal generator configured to output the lower bank writing data transmitted through the global data line to the write global data line. 13. The method of claim 12, The first signal generator may include an activator configured to enable an operation of the first signal generator in response to a control signal generated by the control signal generator; And a driving unit driven according to the bank reading data. The method of claim 11, The repeater may include a first signal generator configured to amplify the upper bank reading data and the lower bank reading data transmitted through the read global data line and output the amplified signal to the global data line; And a second signal generator configured to output upper bank writing data and lower bank writing data transmitted through the global data line to the write global data line. The method of claim 14, The second signal generator may include an activator for enabling the operation of the second signal generator in response to a control signal generated by the control signal generator; And a driving unit driven according to the bank writing data.

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