TWI534825B - Semiconductor memory - Google Patents

Description

Memory device

The present invention relates to integrated circuits, and more particularly to memory devices and methods therefor.

Almost all current electronic devices include some kind of memory for storing data. Memory typically implements many types of memory in modern electronic devices with semiconductor hardware, examples of which may include, but are not limited to, DRAM.

Due to the large amount of data that needs to be stored, traditional memory uses a large number of windings for data access. The invention provides a semiconductor memory structure for reducing winding, effectively reducing wafer area and manufacturing cost.

Based on the above objects, the present invention discloses a semiconductor storage device including a plurality of sense amplifiers, a plurality of array main data line segments, and a plurality of memory segments. The complex array main data line segments are arranged in the column direction. Each memory segment includes a plurality of memory cells, each memory segment being coupled to a corresponding set of main data line segments via a corresponding sense amplifier, and adjacent corresponding main data line segments are mutually Coupling. When the memory data is accessed, the memory data is transmitted by the main data line segment corresponding to the interconnected array.

The invention further discloses a semiconductor storage device, including plural Input and output ports, a global data bus, and a plurality of memory banks. The global data bus is connected to the plurality of input ports to access the memory data. Each memory bank includes a plurality of sense amplifiers, a complex array of main data line segments, and a plurality of memory segments. The complex array main data line segments are arranged in the column direction. Each memory segment includes a plurality of memory cells, each of which is coupled to a corresponding set of main data line segments via a corresponding sense amplifier, and adjacent main data line segments are coupled to each other. And one of the main data line segments is coupled to the global data bus. When the memory data is accessed, the memory data is transmitted by the main data line segment corresponding to the interconnected array.

1‧‧‧Semiconductor memory

2, 3, 4‧‧‧ memory blocks

10‧‧‧DQ data contacts

12‧‧‧Global data bus

140, 141, ..., 147‧‧ memory

1420, 1422, ..., 1438, SA‧‧‧ sense amplifiers

1421, 1423, ..., 1437, seg‧‧‧ memory segments

1440, 1442, ..., 1447‧‧‧ local main data line

16‧‧‧Instruction data contacts

180, 182, 184, 186, SSA‧ ‧ secondary sense amplifier

190, 192‧‧‧ column control line

30, 34‧‧‧Reading amplifier

32, 36‧‧‧ write driver

382, 380‧‧‧ memory blocks

CSL‧‧‧ column control line

MDQ/bMDQ‧‧‧Master data line

MDQ ₀ /bMDQ ₀ , MDQ ₁ /bMDQ ₁ ‧‧‧Local main data line

Seg‧‧‧ memory block

Fig. 1 is a schematic view showing a semiconductor memory 1 in an embodiment of the present invention.

Fig. 2 is a schematic view showing a memory block 2 in the embodiment of the present invention.

Fig. 3 is a view showing another memory block 3 in the reading operation in the embodiment of the present invention.

Fig. 4 is a view showing another memory block 4 in the writing operation in the embodiment of the present invention.

The various embodiments and examples set forth in the following disclosure are intended to illustrate various technical features disclosed herein, and the specific examples or arrangements described herein are used to simplify the invention. It is not intended to limit the invention. In addition, the same parameters may be reused in different embodiments or examples. The reference numerals and symbols used in the drawings are used to illustrate the disclosure of the present invention and are not intended to represent the relationship between different embodiments or examples.

1 is a schematic diagram showing a semiconductor memory 1 in an embodiment of the present invention, including a DQ data contact 10, a global data bus 12, a plurality of memory banks 140, 141, ..., 147, and instructions. Data contact 16. The DQ data contact 10 is coupled to the global data bus 12, and the plurality of memory banks 140 to the memory bank 147, and the plurality of memory banks 140 to the memory bank 147 are also coupled to the command data contacts 16.

The DQ data contact 10 includes a plurality of memory data contacts, and the memory data enters and leaves the semiconductor memory 1 by the DQ data contacts 10. The command data contact 16 includes a plurality of command data contacts for receiving command data, such as writing or receiving instructions. The command data contact 16 is coupled to the memory bank 140 to the memory bank 147 for controlling the memory bank 140 to the memory bank 147 for data reading, writing, or other data processing.

Each memory bank of memory bank 140 to memory bank 147 includes a plurality of memory cells (not shown) for storing memory data, using bit lines representing column C and column R, respectively (not The figure) and word lines (not shown) are used to enable or disable the memory unit to control access to the memory data. In addition, each memory bank includes a plurality of columns, each column having a pair of master data line MDQ/bMDQ and column control line CSL (not shown). For example, each memory bank can include 128 columns. Figure 2 shows a portion of a column in the memory of Figure 1.

The main data line MDQ/bMDQ is a data transmission line. A secondary sense amplifier (not shown) passes through all adjacent banks along the column direction for transferring memory 140 to memory data in memory bank 147. For example, the memory bank 140 of the left half to the memory bank 143 passes through the corresponding data line MDQ/bMDQ through the corresponding secondary sense amplifier through the memory bank 140 to the memory unit in the memory bank 143, and the memory bank in the right half. The 144 to memory 147 is also passed through the corresponding secondary sense amplifier through the data master data line MDQ/bMDQ through the access memory bank 144 to the memory unit in the memory bank 147. Each main data line MDQ/bMDQ transfers memory data between the global data bus 12 and the memory 140 to the memory 147. The main data line MDQ/bMDQ is a pair of data lines MDQ and bMDQ. In some embodiments, when the memory cell is idle, both the primary data line pair MDQ and bMDQ are logic "HIGH"; when writing to the memory cell logic "HIGH" or by the memory cell read logic "HIGH" When the main data line MDQ is logic "HIGH" and the main data line bMDQ is logic "LOW"; when writing to the memory unit logic "LOW" or reading the logic "LOW" by the memory unit, the main data line MDQ It is logical "LOW" and the main data line bMDQ is logic "HIGH".

Each memory bank is additionally controlled by a plurality of dedicated column control lines CSL with column control signals for controlling the enabling or disabling of specific columns of a particular memory bank. When the column control signal enables a particular column of a particular memory bank, the memory cells in that particular column of that particular memory bank can be accessed. When the column control signal is in addition to a specific column of a particular memory bank, the memory cells in that particular column of the particular memory bank are not accessed. Each time a data access is made, only a specific column of a particular memory is enabled. For example, when the column controls the first column of the signal enable memory 143, the first column of the memory bank 140 to the memory bank 142, the memory bank 144 to the memory bank 147 will be controlled by its dedicated column. In addition to energy. Therefore, at this time, only the memory unit of the first column of the memory bank 143 can be accessed through the main data line MDQ/bMDQ.

The plurality of memories 140 to the memory bank 147 are directly connected to the global data bus 12 by the main data line MDQ/bMDQ. The global data bus 12 is connected to the DQ data contact 10. All memory data in the semiconductor memory 1 is accessed through the global data bus 12 .

In Fig. 1, the left half memory 140 to the memory bank 143 and the right half memory bank 144 to the memory bank 147 respectively display only two main data lines MDQ/bMDQ, and the memory banks adjacent to each half are implemented. There are a plurality of main data lines MDQ/bMDQ penetrating through the corresponding secondary sense amplifiers. When reading data, the memory data in each memory unit in the memory is directly transmitted to the global data bus 12 through the plurality of main data lines MDQ/bMDQ and the corresponding secondary sense amplifier 12 by the DQ data contact 10 Output; when writing data, the global data bus 12 transmits the memory data directly to each memory unit in the memory through a plurality of main data lines MDQ/bMDQ and corresponding secondary sense amplifiers.

Since the semiconductor memory 1 directly transfers the memory data between the memory bank and the global data bus 12 through the main data line MDQ/bMDQ running through all adjacent memories, the memory and the global data bus 12 can be reduced. The wire and the winding area effectively reduce the manufacturing cost of the semiconductor memory.

2 is a schematic diagram showing a memory 2 in an embodiment of the present invention, including the same column of two memory banks, including a plurality of sense amplifiers (SA) 1420, 1422, ..., 1438, complex array main data line segments. , a plurality of memory segments 1421, 1423, ..., 1437, column control line (CSL) 190 And 192, and secondary sense amplifiers (SSA) 180, 182, 184, and 186. Wherein, the plurality of sense amplifiers 1420, 1422, ..., 1428, the complex array main data line segment, the plurality of memory segments 1421, 1423, ..., 1427, the secondary sense amplifiers 180 and 182, and the column control line 190 belong to Upper half memory; a plurality of sense amplifiers 1430, 1432, ..., 1438, complex array main data line segments, a plurality of memory segments 1431, 1433, ..., 1437, secondary sense amplifiers 184 and 186, and columns Control line 192 belongs to the lower half of the memory.

First, please refer to the lower half memory. The main data line MDQ/bMDQ is arranged in the column direction. The data line on the left is the main data line MDQ, the data line on the right is the main data line bMDQ, and the main data line MDQ/bMDQ includes the complex array main. Data line segment. Each group of main data line segments includes two local main data lines (only the following half main data line segments are illustrated as an example to show corresponding local main data lines 1440 to local main data lines 1447). The memory operates in either inductive mode or re-driver mode. In the sensing mode, the main data line MDQ/bMDQ carries a set of differential signals; in the re-drive mode, one of the main data lines MDQ/bMDQ carries the data signals transmitted to the adjacent memory. Each memory segment 1431, 1433, ..., 1437 includes a plurality of memory cells (not shown) for storing memory data. Each memory segment is coupled to a corresponding set of main data line segments via a corresponding inductive amplifier, and each two adjacent sets of corresponding main data line segments are coupled to each other. When all adjacent main data line segments are coupled, a main data line MDQ/bMDQ is formed through all adjacent memory banks for direct transmission between the memory cells of the respective memory banks and the global data bus 12 Data path. Taking the memory segment 1435 as an example, the memory segment 1435 is coupled to the corresponding local main data line 1444 through the corresponding sense amplifier 1436 and 1445, and adjacent local main data lines 1442, 1444, and 1446 are coupled to each other, and adjacent local main data lines 1443, 1445, and 1447 are coupled to each other. When all adjacent local main data lines 1440, 1442, 1444 and 1446, and the local main data lines of other memories are coupled, they will be the main data line MDQ. When all the adjacent local main data lines 1441, 1443, 1445 and 1447, and the local main data lines of other memories are coupled, it will be the main data line bMDQ. The main data line MDQ/bMDQ is used to directly connect to the global data bus 12 and directly access each of the penetrating memory segments.

In some embodiments, adjacent local main data lines are coupled to each other through a sense amplifier. Taking memory section 1435 as an example, adjacent local main data lines 1442 and 1444 and 1444 and 1446 are coupled to each other through sense amplifiers 1434 and 1436, respectively; and adjacent local main data lines 1443 and 1445, and 1445 and 1447, respectively. They are coupled to each other through sense amplifiers 1434 and 1436.

As described in the first figure above, each column of each memory bank has its own column control line with a column control signal for controlling all the memory cells on the column of the memory bank. When accessing the memory data of the field in the lower half of the memory of FIG. 2, all the memory cells in the field of the lower half memory are enabled through the column control line 192, and directly through the main data line MDQ. And bMDQ access a plurality of memory cells. For example, when writing the lower half of the memory data, the memory data to be written will enter the global data bus 12 from the DQ data contact, and the memory segment 1431 to the memory segment will be enabled through the column control line 192. 1437, the memory segment 1421 to the memory segment 1427 are disabled by the column control line 190, and the memory cells to be written into the memory segment 1431 to the memory segment 1437 are activated through the word line and the bit line, and Through local capitalism coupled to each other The main data lines MDQ and bMDQ formed by the feed lines and the secondary sense amplifier 180 to the secondary sense amplifier 186 directly write the above-mentioned memory data from the global data bus 12 to the activated memory unit. When the lower half of the memory data is read, the memory block 2 enables the memory segment 1431 to the memory segment 1437 through the column control line 192, and the memory segment 1421 is removed by the column control line 190 to the memory. The body segment 1427 activates the memory cell to read the memory segment 1431 to the memory segment 1437 through the word line and the bit line, and transmits the main data line MDQ formed by the local main data lines coupled to each other. And the bMDQ and the secondary sense amplifier 180 to the secondary sense amplifier 186 read the memory data from the activated memory unit, and finally directly to the global data bus 12 for output by the DQ data contact 10.

3 is a schematic view showing another memory portion 3 in the reading operation in the embodiment of the present invention, including a read amplifier 30 (sense amplifier), a write driver 32, a read amplifier 34 (sense amplifier), and write Driver 36, and memory sections 380 and 382.

The sense amplifiers 30 and 34 can operate in either an inductive mode or a re-driver mode, and can convert the input analog memory data into digital memory data. When operating in the sensing mode, the read amplifier will read the analog memory data from the corresponding memory segment via the two local main data lines, and convert the read memory data into digital memory data. One of the two partial primary data lines of the first level transmits the digital memory data. When operating in the re-drive mode, the read amplifier will only read the analog memory data from one of the two local main data lines, and enhance or directly send the read digital memory data to the next two levels. One of the local master data lines, or directly to the global data bus 12 .

For example, when reading data from memory section 382, read amplifier 34 operates in an inductive mode, reading analog memory data from memory section 382 via local main data lines MDQ ₀ and bMDQ ₀ , and reading The obtained memory data is converted into digital memory data, and the digital memory data is transferred from the local primary data line MDQ _{1 of} the next stage to the next-stage read amplifier 30 through the adjacent memory segment 380. The read amplifier 30 operates in the re-drive mode, and reads only the digital memory data from the local main data line MDQ ₁ and enhances the read digital memory data and directly sends it to the global data bus 12 .

4 is a schematic view showing another memory portion 4 in a write operation in the embodiment of the present invention, including a read amplifier 30 (sense amplifier), a write driver 32, a read amplifier 34 (sense amplifier), and write Driver 36, and memory sections 380 and 382.

The write driver 32 can operate in either the write mode or the redrive mode, and can convert the input digital memory data into analog memory data. When operating in write mode, the write driver converts the digital memory data into analog memory data and writes the two local main data lines into the memory segment. When operating in the re-drive mode, the write driver will only read the digital memory data from one of the two local main data lines, and enhance or directly send the read digital memory data to the next two levels. One of the local main data lines.

For example, when data is to be written to the memory section 382, the write driver 32 operates in the re-drive mode, reads the digital memory data from the global data bus 12, and transmits the data only to the local main data line bMDQ ₁ to The next stage is written to the drive 36. The write driver 36 operates in a write mode, converts the digital memory data into analog memory data, and simultaneously stores the data into the corresponding memory segment 382 through the two local main data lines MDQ ₀ and bMDQ ₀ .

Referring to Figures 3 and 4, in some embodiments, the read drive amplifier and write driver redrive modes are output with different main data lines MDQ and bMDQ. For example, the read drive amplifier's redrive mode uses only the main data line MDQ output; the write drive's redrive mode uses only the main data line bMDQ output.

The operations and functions of the various logic blocks, modules, units, and circuits described herein can be implemented using circuit hardware or embedded software code that can be accessed and executed by a processor.

The present invention has been described above by way of a preferred embodiment, and is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

2‧‧‧ memory block

180, 182, 184, 186‧ ‧ secondary sense amplifier

190, 192‧‧‧ column control line

1420, 1422, ..., 1438‧‧‧ sense amplifier

1421, 1423, ..., 1437‧‧‧ memory segments

1440, 1442, ..., 1447‧‧‧ local main data line

MDQ/bMDQ‧‧‧Master data line

Seg‧‧‧ memory block

SA‧‧‧Sense Amplifier

SSA‧‧‧Secondary Amplifier

CSL‧‧‧ column control line

Claims (7)

A semiconductor storage device comprising: a plurality of sense amplifiers; a complex array of main data line segments arranged in a column direction; and a plurality of memory segments, wherein each memory segment comprises a plurality of memory cells, each memory The body segment is coupled to a corresponding set of main data line segments via a corresponding sense amplifier, and the adjacent corresponding main data line segments are coupled to each other; wherein, when accessing the memory data, by interconnecting The memory data is transmitted on the main data line segment corresponding to the complex array, and the adjacent corresponding main data line segments are coupled to each other through the sense amplifiers between adjacent memory segments; each group corresponds to the main The data line segment includes two local main data lines; and when a read operation is performed, one of the first unmatched memory segments transmits the first corresponding sense amplifier through one of the two local main data lines The above memory data. The semiconductor storage device of claim 1, further comprising: a plurality of write drive circuits; wherein each memory segment is coupled to a corresponding set of main data line regions via a corresponding write drive circuit a segment; the adjacent corresponding main data line segments are coupled to each other by the write drive circuit between adjacent memory segments; and when a write operation is performed, the first corresponding write drive circuit transmits the above The other of the two local main data lines transmits the above memory data. The semiconductor storage device of claim 1, further comprising: a plurality of input and output ports; a global data bus for connecting to the plurality of input and output ports to access the memory data; wherein one of the main data line segments is coupled to the global data bus. The semiconductor storage device of claim 1, further comprising: a plurality of memory banks, wherein each memory bank comprises the plurality of sense amplifiers, the complex array main data line segment, and the plurality of memory segments And a column selection line; wherein the column selection line runs through all of the plurality of memory segments in each memory bank in a column direction; when accessing the memory data from one of the plurality of memory banks The above column selection line will be opened, and the column selection lines of the other remaining plurality of memories will be closed. A semiconductor storage device comprising: a plurality of input and output ports; a global data bus bar for connecting to the plurality of input and output ports to access the memory data; a plurality of memory banks, each memory bank comprising: a plurality of memory cells a sense amplifier; a complex array of main data line segments arranged in a column direction; and a plurality of memory segments, wherein each memory segment includes a plurality of memory cells, each memory segment via a corresponding sense amplifier Coupling to a corresponding set of main data line segments, adjacent corresponding main data line segments are coupled to each other, and one of the main data line segments is coupled to the global data sink a row; wherein, when the memory data is accessed, the adjacent main data line segment passes through the adjacent memory by transmitting the memory data on the main data line segment due to the interconnected complex array The sense amplifiers between the segments are coupled to each other; each set of corresponding main data line segments includes two local main data lines; and when the read operation is performed, one of the memory segments that are not accessed is first The corresponding sense amplifier transmits the memory data from one of the two local main data lines. The semiconductor storage device of claim 5, further comprising: a plurality of write drive circuits; wherein each memory segment is coupled to a corresponding set of main data line regions via a corresponding write drive circuit a segment; the adjacent corresponding main data line segments are coupled to each other by the write drive circuit between adjacent memory segments; and when a write operation is performed, the first corresponding write drive circuit transmits the above The other of the two local main data lines transmits the above memory data. The semiconductor storage device of claim 5, wherein each of the memory banks further selects a column selection line that runs through all of the plurality of memory segments in each memory bank in a column direction; When one of the plurality of memories accesses the memory data, the column selection line is opened, and the remaining column selection lines of the remaining plurality of memories are closed.