TWI534825B - Semiconductor memory - Google Patents
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Description
本發明係有關於積體電路,尤指適用於記憶體裝置以及其方法。 The present invention relates to integrated circuits, and more particularly to memory devices and methods therefor.
當前幾乎所有的電子裝置都會包括某種記憶體用於儲存資料。記憶體通常以半導體硬體實現現代電子裝置使用許多種類的記憶體,其實施例可包括,但不限定於DRAM。 Almost all current electronic devices include some kind of memory for storing data. Memory typically implements many types of memory in modern electronic devices with semiconductor hardware, examples of which may include, but are not limited to, DRAM.
由於需要儲存大量資料,傳統的記憶體都要使用大量繞線進行資料存取。本發明提出一種半導體記憶體結構用以減少繞線,有效降低晶片面積以及製造費用。 Due to the large amount of data that needs to be stored, traditional memory uses a large number of windings for data access. The invention provides a semiconductor memory structure for reducing winding, effectively reducing wafer area and manufacturing cost.
基於上述目的,本發明揭露了一種半導體儲存裝置,包括複數個感應放大器、複數組主資料線區段、以及複數個記憶體區段。該複數組主資料線區段以欄方向排列。每個記憶體區段包括複數個記憶體單元,每個記憶體區段經由一對應的感應放大器耦接至一組對應的主資料線區段,以及相鄰的對應的主資料線區段互相耦接。當存取記憶體資料時,藉由於互相連接的該複數組對應的主資料線區段上傳送上述記憶體資料。 Based on the above objects, the present invention discloses a semiconductor storage device including a plurality of sense amplifiers, a plurality of array main data line segments, and a plurality of memory segments. The complex array main data line segments are arranged in the column direction. Each memory segment includes a plurality of memory cells, each memory segment being coupled to a corresponding set of main data line segments via a corresponding sense amplifier, and adjacent corresponding main data line segments are mutually Coupling. When the memory data is accessed, the memory data is transmitted by the main data line segment corresponding to the interconnected array.
本發明更揭露了一種半導體儲存裝置,包括複數 個輸出入埠、一全域資料匯流排、以及複數個記憶庫。該全域資料匯流排連接至上述複數個輸出入埠以存取上述記憶體資料。每個記憶庫包括複數個感應放大器、複數組主資料線區段、以及複數個記憶體區段。該複數組主資料線區段以欄方向排列。每個記憶體區段包括複數個記憶體單元,每個記憶體區段經由一對應的感應放大器耦接至一組對應的主資料線區段,相鄰對應的主資料線區段互相耦接,以及其中一組主資料線區段耦接上述全域資料匯流排。當存取記憶體資料時,藉由於互相連接的該複數組對應的主資料線區段上傳送上述記憶體資料。 The invention further discloses a semiconductor storage device, including plural Input and output ports, a global data bus, and a plurality of memory banks. The global data bus is connected to the plurality of input ports to access the memory data. Each memory bank includes a plurality of sense amplifiers, a complex array of main data line segments, and a plurality of memory segments. The complex array main data line segments are arranged in the column direction. Each memory segment includes a plurality of memory cells, each of which is coupled to a corresponding set of main data line segments via a corresponding sense amplifier, and adjacent main data line segments are coupled to each other. And one of the main data line segments is coupled to the global data bus. When the memory data is accessed, the memory data is transmitted by the main data line segment corresponding to the interconnected array.
1‧‧‧半導體記憶體 1‧‧‧Semiconductor memory
2、3、4‧‧‧記憶體區塊 2, 3, 4‧‧‧ memory blocks
10‧‧‧DQ資料接點 10‧‧‧DQ data contacts
12‧‧‧全域資料匯流排 12‧‧‧Global data bus
140、141、…、147‧‧‧記憶庫 140, 141, ..., 147‧‧ memory
1420、1422、…、1438、SA‧‧‧感應放大器 1420, 1422, ..., 1438, SA‧‧‧ sense amplifiers
1421、1423、…、1437、seg‧‧‧記憶體區段 1421, 1423, ..., 1437, seg‧‧‧ memory segments
1440、1442、…、1447‧‧‧局部主資料線 1440, 1442, ..., 1447‧‧‧ local main data line
16‧‧‧指令資料接點 16‧‧‧Instruction data contacts
180、182、184、186、SSA‧‧‧二次感應放大器 180, 182, 184, 186, SSA‧ ‧ secondary sense amplifier
190、192‧‧‧欄控制線 190, 192‧‧‧ column control line
30、34‧‧‧讀取放大器 30, 34‧‧‧Reading amplifier
32、36‧‧‧寫入驅動器 32, 36‧‧‧ write driver
382、380‧‧‧記憶體區塊 382, 380‧‧‧ memory blocks
CSL‧‧‧欄控制線 CSL‧‧‧ column control line
MDQ/bMDQ‧‧‧主資料線 MDQ/bMDQ‧‧‧Master data line
MDQ0/bMDQ0、MDQ1/bMDQ1‧‧‧局部主資料線 MDQ 0 /bMDQ 0 , MDQ 1 /bMDQ 1 ‧‧‧Local main data line
seg‧‧‧記憶體區塊 Seg‧‧‧ memory block
第1圖係顯示本發明實施例中一種半導體記憶體1的示意圖。 Fig. 1 is a schematic view showing a semiconductor memory 1 in an embodiment of the present invention.
第2圖係顯示本發明實施例中一種記憶體區塊2的示意圖。 Fig. 2 is a schematic view showing a memory block 2 in the embodiment of the present invention.
第3圖係顯示本發明實施例中另一種記憶體區塊3在讀取動作時的示意圖。 Fig. 3 is a view showing another memory block 3 in the reading operation in the embodiment of the present invention.
第4圖係顯示本發明實施例中另一種記憶體區塊4在寫入動作時的示意圖。 Fig. 4 is a view showing another memory block 4 in the writing operation in the embodiment of the present invention.
在此必須說明的是,於下揭露內容中所提出之不同實施例或範例,係用以說明本發明所揭示之不同技術特徵,其所描述之特定範例或排列係用以簡化本發明,然非用以限定本發明。此外,在不同實施例或範例中可能重覆使用相同之參 考數字與符號,此等重覆使用之參考數字與符號係用以說明本發明所揭示之內容,而非用以表示不同實施例或範例間之關係。 The various embodiments and examples set forth in the following disclosure are intended to illustrate various technical features disclosed herein, and the specific examples or arrangements described herein are used to simplify the invention. It is not intended to limit the invention. In addition, the same parameters may be reused in different embodiments or examples. The reference numerals and symbols used in the drawings are used to illustrate the disclosure of the present invention and are not intended to represent the relationship between different embodiments or examples.
第1圖係顯示本發明實施例中一種半導體記憶體1的示意圖,包括DQ資料接點10、一全域資料匯流排12、複數個記憶庫(memory bank)140、141、…、147、以及指令資料接點16。DQ資料接點10耦接全域資料匯流排12、以及複數個記憶庫140到記憶庫147、複數個記憶庫140到記憶庫147也耦接指令資料接點16。 1 is a schematic diagram showing a semiconductor memory 1 in an embodiment of the present invention, including a DQ data contact 10, a global data bus 12, a plurality of memory banks 140, 141, ..., 147, and instructions. Data contact 16. The DQ data contact 10 is coupled to the global data bus 12, and the plurality of memory banks 140 to the memory bank 147, and the plurality of memory banks 140 to the memory bank 147 are also coupled to the command data contacts 16.
DQ資料接點10包括複數個記憶體資料接點,記憶體資料由DQ資料接點10進入及離開半導體記憶體1。指令資料接點16包括複數個指令資料接點,用於接收指令資料,例如寫入或接收指令。指令資料接點16耦接記憶庫140到記憶庫147,用以控制記憶庫140到記憶庫147進行資料讀取、寫入、或其他資料處理。 The DQ data contact 10 includes a plurality of memory data contacts, and the memory data enters and leaves the semiconductor memory 1 by the DQ data contacts 10. The command data contact 16 includes a plurality of command data contacts for receiving command data, such as writing or receiving instructions. The command data contact 16 is coupled to the memory bank 140 to the memory bank 147 for controlling the memory bank 140 to the memory bank 147 for data reading, writing, or other data processing.
記憶庫140到記憶庫147中每個記憶庫都包括複數個記憶體單元(未圖示),用於儲存記憶體資料,分別使用表示欄C和列R的位元線(bit lines)(未圖示)以及字線(word lines)(未圖示)來啟動或關閉記憶體單元,進而控制中記憶體資料的存取。另外,每個記憶庫都包括複數欄,每欄都有一對主資料線(master data line)MDQ/bMDQ和欄控制線CSL(未圖示)。例如,每個記憶庫可包括128個欄。第2圖顯示第1圖記憶庫中一欄的一部分。 Each memory bank of memory bank 140 to memory bank 147 includes a plurality of memory cells (not shown) for storing memory data, using bit lines representing column C and column R, respectively (not The figure) and word lines (not shown) are used to enable or disable the memory unit to control access to the memory data. In addition, each memory bank includes a plurality of columns, each column having a pair of master data line MDQ/bMDQ and column control line CSL (not shown). For example, each memory bank can include 128 columns. Figure 2 shows a portion of a column in the memory of Figure 1.
主資料線MDQ/bMDQ係為一種資料傳輸線,透過 二次感應放大器(未圖示)穿過沿著欄方向所有相鄰的記憶庫,用於傳送記憶庫140到記憶庫147中的記憶體資料。例如,左半部的記憶庫140到記憶庫143由主資料線MDQ/bMDQ透過對應的二次感應放大器穿過存取記憶庫140到記憶庫143內的記憶體單元,右半部的記憶庫144到記憶庫147也由資料主資料線MDQ/bMDQ透過對應的二次感應放大器貫過存取記憶庫144到記憶庫147內的記憶體單元。每條主資料線MDQ/bMDQ在全域資料匯流排12和記憶庫140到記憶庫147間傳送記憶體資料。主資料線MDQ/bMDQ係為一對資料線MDQ和bMDQ。在某些實施例中,當記憶體單元閒置時,主資料線對MDQ和bMDQ兩者皆為邏輯”HIGH”;當寫入記憶體單元邏輯”HIGH”或由記憶體單元讀取邏輯”HIGH”時,主資料線MDQ為邏輯”HIGH”且主資料線bMDQ為邏輯”LOW”;當寫入記憶體單元邏輯”LOW”或由記憶體單元讀取邏輯”LOW”時,主資料線MDQ為邏輯”LOW”且主資料線bMDQ為邏輯”HIGH”。 The main data line MDQ/bMDQ is a data transmission line. A secondary sense amplifier (not shown) passes through all adjacent banks along the column direction for transferring memory 140 to memory data in memory bank 147. For example, the memory bank 140 of the left half to the memory bank 143 passes through the corresponding data line MDQ/bMDQ through the corresponding secondary sense amplifier through the memory bank 140 to the memory unit in the memory bank 143, and the memory bank in the right half. The 144 to memory 147 is also passed through the corresponding secondary sense amplifier through the data master data line MDQ/bMDQ through the access memory bank 144 to the memory unit in the memory bank 147. Each main data line MDQ/bMDQ transfers memory data between the global data bus 12 and the memory 140 to the memory 147. The main data line MDQ/bMDQ is a pair of data lines MDQ and bMDQ. In some embodiments, when the memory cell is idle, both the primary data line pair MDQ and bMDQ are logic "HIGH"; when writing to the memory cell logic "HIGH" or by the memory cell read logic "HIGH" When the main data line MDQ is logic "HIGH" and the main data line bMDQ is logic "LOW"; when writing to the memory unit logic "LOW" or reading the logic "LOW" by the memory unit, the main data line MDQ It is logical "LOW" and the main data line bMDQ is logic "HIGH".
每個記憶庫另外由複數條專用的欄控制線CSL控制,上面帶有欄控制訊號,用於分別控制特定記憶庫之特定欄的致能(enablement)或除能(disablement)。當欄控制訊號致能特定記憶庫之特定欄時,則該特定記憶庫之該特定欄中的記憶體單元可被存取。當欄控制訊號除能特定記憶庫之特定欄時,則該特定記憶庫之該特定欄中的記憶體單元不會被存取。每次的資料存取都只會致能一個特定記憶庫的特定欄。例如,當欄控制訊號致能記憶庫143的第1欄時,記憶庫140到記憶庫142、記憶庫144到記憶庫147的第1欄都會被其專用的欄控制訊號 除能。因此,此時只有記憶庫143的第1欄的記憶體單元可透過主資料線MDQ/bMDQ存取。 Each memory bank is additionally controlled by a plurality of dedicated column control lines CSL with column control signals for controlling the enabling or disabling of specific columns of a particular memory bank. When the column control signal enables a particular column of a particular memory bank, the memory cells in that particular column of that particular memory bank can be accessed. When the column control signal is in addition to a specific column of a particular memory bank, the memory cells in that particular column of the particular memory bank are not accessed. Each time a data access is made, only a specific column of a particular memory is enabled. For example, when the column controls the first column of the signal enable memory 143, the first column of the memory bank 140 to the memory bank 142, the memory bank 144 to the memory bank 147 will be controlled by its dedicated column. In addition to energy. Therefore, at this time, only the memory unit of the first column of the memory bank 143 can be accessed through the main data line MDQ/bMDQ.
複數個記憶庫140到記憶庫147藉由主資料線MDQ/bMDQ直接連接到全域資料匯流排12。全域資料匯流排12連接到DQ資料接點10。半導體記憶體1內所有的記憶體資料都會透過全域資料匯流排12而進行存取。 The plurality of memories 140 to the memory bank 147 are directly connected to the global data bus 12 by the main data line MDQ/bMDQ. The global data bus 12 is connected to the DQ data contact 10. All memory data in the semiconductor memory 1 is accessed through the global data bus 12 .
在第1圖中,左半部記憶庫140到記憶庫143和右半部記憶庫144到記憶庫147僅分別顯示兩條主資料線MDQ/bMDQ,實作上各半邊相鄰的記憶庫都有複數條主資料線MDQ/bMDQ透過對應之二次感應放大器縱向貫穿。在讀取資料時,將記憶庫內之各個記憶體單元內的記憶體資料透過複數條主資料線MDQ/bMDQ和對應之二次感應放大器直接傳送至全域資料匯流排12由DQ資料接點10輸出;在寫入資料時,由全域資料匯流排12透過複數條主資料線MDQ/bMDQ和對應之二次感應放大器將記憶體資料直接傳送至記憶庫內之各個記憶體單元儲存。 In Fig. 1, the left half memory 140 to the memory bank 143 and the right half memory bank 144 to the memory bank 147 respectively display only two main data lines MDQ/bMDQ, and the memory banks adjacent to each half are implemented. There are a plurality of main data lines MDQ/bMDQ penetrating through the corresponding secondary sense amplifiers. When reading data, the memory data in each memory unit in the memory is directly transmitted to the global data bus 12 through the plurality of main data lines MDQ/bMDQ and the corresponding secondary sense amplifier 12 by the DQ data contact 10 Output; when writing data, the global data bus 12 transmits the memory data directly to each memory unit in the memory through a plurality of main data lines MDQ/bMDQ and corresponding secondary sense amplifiers.
由於半導體記憶體1透過貫穿所有相鄰記憶庫的主資料線MDQ/bMDQ直接將記憶體資料在記憶庫和全域資料匯流排12間傳送,因此可減少記憶庫和全域資料匯流排12間的繞線以及繞線面積,有效降低半導體記憶體的製造費用。 Since the semiconductor memory 1 directly transfers the memory data between the memory bank and the global data bus 12 through the main data line MDQ/bMDQ running through all adjacent memories, the memory and the global data bus 12 can be reduced. The wire and the winding area effectively reduce the manufacturing cost of the semiconductor memory.
第2圖係顯示本發明實施例中一段記憶體2的示意圖,包括兩個記憶庫的相同欄,其包括複數個感應放大器(SA)1420、1422、…、1438、複數組主資料線區段、複數個記憶體區段(memory segment)1421、1423、…、1437、欄控制線(CSL)190 和192、以及二次感應放大器(SSA)180、182、184及186。其中,複數個感應放大器1420、1422、…、1428、複數組主資料線區段、複數個記憶體區段1421、1423、…、1427、二次感應放大器180和182、以及欄控制線190屬於上半部記憶庫;複數個感應放大器1430、1432、…、1438、複數組主資料線區段、複數個記憶體區段1431、1433、…、1437、二次感應放大器184和186、以及欄控制線192屬於下半部記憶庫。 2 is a schematic diagram showing a memory 2 in an embodiment of the present invention, including the same column of two memory banks, including a plurality of sense amplifiers (SA) 1420, 1422, ..., 1438, complex array main data line segments. , a plurality of memory segments 1421, 1423, ..., 1437, column control line (CSL) 190 And 192, and secondary sense amplifiers (SSA) 180, 182, 184, and 186. Wherein, the plurality of sense amplifiers 1420, 1422, ..., 1428, the complex array main data line segment, the plurality of memory segments 1421, 1423, ..., 1427, the secondary sense amplifiers 180 and 182, and the column control line 190 belong to Upper half memory; a plurality of sense amplifiers 1430, 1432, ..., 1438, complex array main data line segments, a plurality of memory segments 1431, 1433, ..., 1437, secondary sense amplifiers 184 and 186, and columns Control line 192 belongs to the lower half of the memory.
首先請參考下半部記憶庫,主資料線MDQ/bMDQ以欄方向排列,左邊的資料線為主資料線MDQ,右邊的資料線為主資料線bMDQ,主資料線MDQ/bMDQ包括複數組主資料線區段。每組主資料線區段包括兩條局部主資料線(圖示僅以下半部主資料線區段為示例繪示對應的局部主資料線1440到局部主資料線1447)。記憶庫會以感應模式或是重驅動(re-driver)模式運作。在感應模式下,主資料線MDQ/bMDQ載有一組差動訊號;在重驅動模式下,主資料線MDQ/bMDQ之其一載有傳遞到相鄰記憶庫的資料訊號。每個記憶體區段1431、1433、…、1437包括複數個記憶體單元(未圖示),該記憶體單元用於儲存記憶體資料。每個記憶體區段經由一對應的感應放大器耦接至一組對應的主資料線區段,每兩組相鄰對應的主資料線區段互相耦接。當所有相鄰的主資料線區段耦接起來後便形成貫穿所有相鄰記憶庫的主資料線MDQ/bMDQ,用於在各個記憶庫之記憶體單元和全域資料匯流排12間作為直接傳送的資料路徑。以記憶體區段1435為例,記憶體區段1435透過對應的感應放大器1436耦接對應的局部主資料線1444和 1445,且相鄰的局部主資料線1442、1444和1446互相耦接,以及相鄰的局部主資料線1443、1445和1447互相耦接。當所有相鄰的局部主資料線1440、1442、1444及1446,以及其他記憶庫之局部主資料線耦接起來後就會是主資料線MDQ。當所有相鄰的局部主資料線1441、1443、1445及1447,以及其他記憶庫之局部主資料線耦接起來後就會是主資料線bMDQ。主資料線MDQ/bMDQ用於直接連接到全域資料匯流排12以及直接存取各個貫穿的記憶體區段。 First, please refer to the lower half memory. The main data line MDQ/bMDQ is arranged in the column direction. The data line on the left is the main data line MDQ, the data line on the right is the main data line bMDQ, and the main data line MDQ/bMDQ includes the complex array main. Data line segment. Each group of main data line segments includes two local main data lines (only the following half main data line segments are illustrated as an example to show corresponding local main data lines 1440 to local main data lines 1447). The memory operates in either inductive mode or re-driver mode. In the sensing mode, the main data line MDQ/bMDQ carries a set of differential signals; in the re-drive mode, one of the main data lines MDQ/bMDQ carries the data signals transmitted to the adjacent memory. Each memory segment 1431, 1433, ..., 1437 includes a plurality of memory cells (not shown) for storing memory data. Each memory segment is coupled to a corresponding set of main data line segments via a corresponding inductive amplifier, and each two adjacent sets of corresponding main data line segments are coupled to each other. When all adjacent main data line segments are coupled, a main data line MDQ/bMDQ is formed through all adjacent memory banks for direct transmission between the memory cells of the respective memory banks and the global data bus 12 Data path. Taking the memory segment 1435 as an example, the memory segment 1435 is coupled to the corresponding local main data line 1444 through the corresponding sense amplifier 1436 and 1445, and adjacent local main data lines 1442, 1444, and 1446 are coupled to each other, and adjacent local main data lines 1443, 1445, and 1447 are coupled to each other. When all adjacent local main data lines 1440, 1442, 1444 and 1446, and the local main data lines of other memories are coupled, they will be the main data line MDQ. When all the adjacent local main data lines 1441, 1443, 1445 and 1447, and the local main data lines of other memories are coupled, it will be the main data line bMDQ. The main data line MDQ/bMDQ is used to directly connect to the global data bus 12 and directly access each of the penetrating memory segments.
在某些實施例中,相鄰的局部主資料線會透過感應放大器互相耦接。以記憶體區段1435為例,相鄰的局部主資料線1442和1444以及1444和1446分別透過感應放大器1434和1436互相耦接;且相鄰的局部主資料線1443和1445以及1445和1447分別透過感應放大器1434和1436互相耦接。 In some embodiments, adjacent local main data lines are coupled to each other through a sense amplifier. Taking memory section 1435 as an example, adjacent local main data lines 1442 and 1444 and 1444 and 1446 are coupled to each other through sense amplifiers 1434 and 1436, respectively; and adjacent local main data lines 1443 and 1445, and 1445 and 1447, respectively. They are coupled to each other through sense amplifiers 1434 and 1436.
如前面第1圖所述,每個記憶庫的每個欄都各有專屬的欄控制線,上面帶有欄控制訊號,用於分別控制該記憶庫的欄上之所有記憶體細胞。當存取第2圖下半部記憶庫之欄位的記憶體資料時,會透過欄控制線192致能下半部記憶庫之欄位上的所有記憶體單元,並直接透過主資料線MDQ和bMDQ存取複數個記憶體單元。例如,當寫入下半部記憶庫資料時,要寫入的記憶體資料會由DQ資料接點進入全域資料匯流排12,透過欄控制線192致能記憶體區段1431到記憶體區段1437,透過欄控制線190除能記憶體區段1421到記憶體區段1427,透過字線和位元線啟動要寫入記憶體區段1431到記憶體區段1437中之記憶體單元,並透過於互相耦接的局部主資 料線所形成的主資料線MDQ和bMDQ和二次感應放大器180到二次感應放大器186直接從全域資料匯流排12將上述記憶體資料寫入啟動的記憶體單元。當讀取下半部記憶庫資料時,記憶體區塊2會透過欄控制線192致能記憶體區段1431到記憶體區段1437,透過欄控制線190除能記憶體區段1421到記憶體區段1427,透過字線和位元線啟動要讀取記憶體區段1431到記憶體區段1437之記憶體單元,並透過於互相耦接的局部主資料線所形成的主資料線MDQ和bMDQ和二次感應放大器180到二次感應放大器186從啟動的記憶體單元讀取記憶體資料,最後直接送到全域資料匯流排12由DQ資料接點10輸出。 As described in the first figure above, each column of each memory bank has its own column control line with a column control signal for controlling all the memory cells on the column of the memory bank. When accessing the memory data of the field in the lower half of the memory of FIG. 2, all the memory cells in the field of the lower half memory are enabled through the column control line 192, and directly through the main data line MDQ. And bMDQ access a plurality of memory cells. For example, when writing the lower half of the memory data, the memory data to be written will enter the global data bus 12 from the DQ data contact, and the memory segment 1431 to the memory segment will be enabled through the column control line 192. 1437, the memory segment 1421 to the memory segment 1427 are disabled by the column control line 190, and the memory cells to be written into the memory segment 1431 to the memory segment 1437 are activated through the word line and the bit line, and Through local capitalism coupled to each other The main data lines MDQ and bMDQ formed by the feed lines and the secondary sense amplifier 180 to the secondary sense amplifier 186 directly write the above-mentioned memory data from the global data bus 12 to the activated memory unit. When the lower half of the memory data is read, the memory block 2 enables the memory segment 1431 to the memory segment 1437 through the column control line 192, and the memory segment 1421 is removed by the column control line 190 to the memory. The body segment 1427 activates the memory cell to read the memory segment 1431 to the memory segment 1437 through the word line and the bit line, and transmits the main data line MDQ formed by the local main data lines coupled to each other. And the bMDQ and the secondary sense amplifier 180 to the secondary sense amplifier 186 read the memory data from the activated memory unit, and finally directly to the global data bus 12 for output by the DQ data contact 10.
第3圖係顯示本發明實施例中另一種記憶體部分3在讀取動作時的示意圖,包括讀取放大器30(感應放大器)、寫入驅動器32、讀取放大器34(感應放大器)、寫入驅動器36、以及記憶體區段380和382。 3 is a schematic view showing another memory portion 3 in the reading operation in the embodiment of the present invention, including a read amplifier 30 (sense amplifier), a write driver 32, a read amplifier 34 (sense amplifier), and write Driver 36, and memory sections 380 and 382.
讀取放大器30和34可以使用感應模式或是重驅動(re-driver)模式運作,並可將輸入的類比記憶體資料轉為數位記憶體資料。當使用感應模式運作時,讀取放大器會從對應的記憶體區段經由兩條局部主資料線和讀取類比記憶體資料,並將讀到的記憶體資料轉換為數位記憶體資料,從下一級的兩條局部主資料線中之一者傳送該數位記憶體資料。當使用重驅動模式運作時,讀取放大器會只從上述兩條局部主資料線中之一者讀取類比記憶體資料,並將讀到的數位記憶體資料加強或直接送到下一級兩條局部主資料線之一者,或直接送到全域資料匯流排12。 The sense amplifiers 30 and 34 can operate in either an inductive mode or a re-driver mode, and can convert the input analog memory data into digital memory data. When operating in the sensing mode, the read amplifier will read the analog memory data from the corresponding memory segment via the two local main data lines, and convert the read memory data into digital memory data. One of the two partial primary data lines of the first level transmits the digital memory data. When operating in the re-drive mode, the read amplifier will only read the analog memory data from one of the two local main data lines, and enhance or directly send the read digital memory data to the next two levels. One of the local master data lines, or directly to the global data bus 12 .
例如,當由記憶體區段382中讀取資料時,讀取放大器34以感應模式運作,從記憶體區段382經由局部主資料線MDQ0和bMDQ0讀取類比記憶體資料,並將讀到的記憶體資料轉換為數位記憶體資料,並只從下一級的局部主資料線MDQ1傳送該數位記憶體資料經過相鄰記憶體區段380傳送到下一級讀取放大器30。讀取放大器30以重驅動模式運作,只從局部主資料線MDQ1讀取數位記憶體資料,並將讀到的數位記憶體資料加強並直接送到全域資料匯流排12。 For example, when reading data from memory section 382, read amplifier 34 operates in an inductive mode, reading analog memory data from memory section 382 via local main data lines MDQ 0 and bMDQ 0 , and reading The obtained memory data is converted into digital memory data, and the digital memory data is transferred from the local primary data line MDQ 1 of the next stage to the next-stage read amplifier 30 through the adjacent memory segment 380. The read amplifier 30 operates in the re-drive mode, and reads only the digital memory data from the local main data line MDQ 1 and enhances the read digital memory data and directly sends it to the global data bus 12 .
第4圖係顯示本發明實施例中另一種記憶體部分4在寫入動作時的示意圖,包括讀取放大器30(感應放大器)、寫入驅動器32、讀取放大器34(感應放大器)、寫入驅動器36、以及記憶體區段380和382。 4 is a schematic view showing another memory portion 4 in a write operation in the embodiment of the present invention, including a read amplifier 30 (sense amplifier), a write driver 32, a read amplifier 34 (sense amplifier), and write Driver 36, and memory sections 380 and 382.
寫入驅動器32可以使用寫入模式或是重驅動模式運作,並可將輸入的數位記憶體資料轉為類比記憶體資料。當使用寫入模式運作時,寫入驅動器將數位記憶體資料轉換為類比記憶體資料,並由兩條局部主資料線寫入記憶體區段。當使用重驅動模式運作時,寫入驅動器會只從上述兩條局部主資料線中之一者讀取數位記憶體資料,並將讀到的數位記憶體資料加強或直接送到下一級的兩條局部主資料線之一者。 The write driver 32 can operate in either the write mode or the redrive mode, and can convert the input digital memory data into analog memory data. When operating in write mode, the write driver converts the digital memory data into analog memory data and writes the two local main data lines into the memory segment. When operating in the re-drive mode, the write driver will only read the digital memory data from one of the two local main data lines, and enhance or directly send the read digital memory data to the next two levels. One of the local main data lines.
例如,欲寫入資料至記憶體區段382時,寫入驅動器32以重驅動模式運作,從全域資料匯流排12讀取數位記憶體資料,並只由局部主資料線bMDQ1將資料傳送至下一級寫入驅動器36。寫入驅動器36以寫入模式運作,將數位記憶體資料轉換為類比記憶體資料,並透過兩條局部主資料線 MDQ0和bMDQ0同時將資料存入相應的記憶體區段382。 For example, when data is to be written to the memory section 382, the write driver 32 operates in the re-drive mode, reads the digital memory data from the global data bus 12, and transmits the data only to the local main data line bMDQ 1 to The next stage is written to the drive 36. The write driver 36 operates in a write mode, converts the digital memory data into analog memory data, and simultaneously stores the data into the corresponding memory segment 382 through the two local main data lines MDQ 0 and bMDQ 0 .
請參考第3和第4圖,在某些實施例中,讀取放大器和寫入驅動器的重驅動模式以不同的主資料線MDQ和bMDQ輸出。例如讀取放大器的重驅動模式只使用主資料線MDQ輸出;寫入驅動器的重驅動模式只使用主資料線bMDQ輸出。 Referring to Figures 3 and 4, in some embodiments, the read drive amplifier and write driver redrive modes are output with different main data lines MDQ and bMDQ. For example, the read drive amplifier's redrive mode uses only the main data line MDQ output; the write drive's redrive mode uses only the main data line bMDQ output.
本發明描述之各種邏輯區塊、模組、單元、以及電路的操作以及功能可以利用電路硬體或嵌入式軟體碼加以實現,該嵌入式軟體碼可以由一處理器存取以及執行。 The operations and functions of the various logic blocks, modules, units, and circuits described herein can be implemented using circuit hardware or embedded software code that can be accessed and executed by a processor.
本發明雖以較佳實施例揭露如上,然其並非用以限定本發明,任何熟習此項技藝者,在不脫離本發明之精神和範圍內,當可做些許的更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 The present invention has been described above by way of a preferred embodiment, and is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.
2‧‧‧記憶體區塊 2‧‧‧ memory block
180、182、184、186‧‧‧二次感應放大器 180, 182, 184, 186‧ ‧ secondary sense amplifier
190、192‧‧‧欄控制線 190, 192‧‧‧ column control line
1420、1422、…、1438‧‧‧感應放大器 1420, 1422, ..., 1438‧‧‧ sense amplifier
1421、1423、…、1437‧‧‧記憶體區段 1421, 1423, ..., 1437‧‧‧ memory segments
1440、1442、…、1447‧‧‧局部主資料線 1440, 1442, ..., 1447‧‧‧ local main data line
MDQ/bMDQ‧‧‧主資料線 MDQ/bMDQ‧‧‧Master data line
seg‧‧‧記憶體區塊 Seg‧‧‧ memory block
SA‧‧‧感應放大器 SA‧‧‧Sense Amplifier
SSA‧‧‧二次感應放大器 SSA‧‧‧Secondary Amplifier
CSL‧‧‧欄控制線 CSL‧‧‧ column control line
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