KR100525109B1 - A Device of Global I/O line repair for a high speed DRAM - Google Patents

Abstract

The present invention relates to an internal I / O device capable of smooth data transfer in a high speed DRAM. In particular, a spare global I / O line is provided to select a global I / O line that is less susceptible to skew and transmits data, thereby preventing defects in transmission data. The present invention relates to a global I / O line repair device that can improve the yield reduction.

In an embodiment of the present invention, a global DRAM input / output line repair apparatus for high-speed DRAM includes N local data input / output units for receiving and amplifying data from a pair of bit lines of a memory device; A global input / output unit configured to receive an output signal of the local data input / output unit; A register unit for receiving data of the global input / output unit; A N output predriver section for receiving the output signal of the register unit and transmitting the output signal to an output main driver, wherein each local data input / output unit comprises a pair of local data lines; And a first amplifier and a second amplifier for receiving and amplifying data on the local data line in common. The global input / output unit includes N + 1 global I / O lines, and any i, i + 1 th (i Is an integer of 1, 2, 3,..., N) The global line corresponds to receive the output signals of the first and second amplifiers respectively provided in the i-th local data input and output unit, Each output predriver section includes a first driver and a second driver, and the first driver and the second driver included in the arbitrary i-th output predriver section are provided on the N + 1 lines on a global line, respectively. A global input / output line repair apparatus for a high speed DRAM, which receives output signals of the i and i + 1th registers among the registers and has a common output line.

Description

Global I / O line repair device for high speed DRAM {A Device of Global I / O line repair for a high speed DRAM}

The present invention relates to a global I / O line repair device for a high speed DRAM, and to avoid data transmission through a global I / O line with a large skew effect, and to transmit data through an extra global I / O line with less skew influence. The present invention relates to a high speed DRAM global input / output line repair apparatus.

1 shows a data input / output device according to the prior art using four input / output lines.

As illustrated, an internal data input / output device of a conventional semiconductor memory includes four local data input / output units 100, 110, 120, and 130 that output and amplify data from a pair of bit lines of a memory device, and output signals of the local data input / output unit. It consists of a global input and output unit 140 for receiving the output unit, a register unit 150 for receiving the output signal of the global input and output unit, and an output pre-driver unit 160 for receiving the output signal of the register unit.

Each local data input / output unit (100, 110, 120, 130) is composed of a pair of local data lines and the sense amplifiers (101, 111, 121, 131) receiving them, the received data to the external power supply (VDD) level Amplify.

The global input / output unit 140 is composed of four global input / output lines gio0, gio1, gio2, and gio3, and receives the output signals of the local data input / output unit, respectively.

The register unit 150 is composed of registers 151, 152, 153, and 154 existing on each global line, and participates in the smooth transfer of data transmitted to the global input / output lines.

The output predriver section 160 is composed of drivers 161, 162, 163, and 164 respectively receiving the output signals of the register section, and each driver has an output enable signal, which is a DRAM control signal, in common. When a high level is applied to the output enable signal, the data is transmitted to the output main driver 170.

However, when the conventional technology is applied to a high speed DRAM SDRAM or a graphic DRAM having a large number of input / output lines, the resistance of a global line designed with a long metal line or a coupling capacitance between peripheral global input / output lines is applied. The skew may cause a problem, and the skew may cause a problem of lowering the efficiency of data transmission.

The present invention has been proposed to solve the above-described problem, and to provide a global input / output line repair apparatus for a high speed DRAM that enables a smooth data transmission in a high speed DRAM.

In particular, the present invention provides a global I / O line repair device that can increase the yield by reducing the skew between transmission data by selecting a good global I / O line that is provided with an extra global I / O line and less influenced by skew.

In an embodiment of the present invention, a global DRAM input / output line repair apparatus for high-speed DRAM includes N local data input / output units for receiving and amplifying data from a pair of bit lines of a memory device; A global input / output unit configured to receive an output signal of the local data input / output unit; A register unit for receiving data of the global input / output unit; A N output predriver section for receiving the output signal of the register unit and transmitting the output signal to an output main driver, wherein each local data input / output unit comprises a pair of local data lines; And a first amplifier and a second amplifier for receiving and amplifying data on the local data line in common. The global input / output unit includes N + 1 global I / O lines, and any i, i + 1 th (i Is an integer of 1, 2, 3,..., N) The global line corresponds to receive the output signals of the first and second amplifiers respectively provided in the i-th local data input and output unit, Each output predriver section includes a first driver and a second driver, and the first driver and the second driver included in the arbitrary i-th output predriver section are provided on the N + 1 global lines, respectively. A global input / output line repair apparatus for a high speed DRAM, which receives output signals of the i and i + 1th registers among the registers and has a common output line.

(Example)

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

2 illustrates a global input / output line repair apparatus for a high speed DRAM according to the present invention.

As shown in the drawing, five global input / output lines gio0, gio1, gio2, gio3, and gio4 are used to generate 4 bit output signals DQ0, DQ1, DQ2, and DQ3.

The global input / output line repair apparatus for a high speed DRAM according to the present invention receives four local data input / output units 200, 210, 220, and 230 and output signals of the local data input / output unit for receiving and amplifying data from a pair of bit lines of a memory device. Four output pre-drivers 260, 270, 280, and 290 that receive the global input / output unit 240, the register unit 250 that receives data from the global input / output unit, and the output signal of the register unit to the output main driver 300. ).

Each local data input / output unit 200, 210, 220, 230 includes a pair of local data lines, and a first amplifier and a second amplifier (hereinafter, a sense amplifier) for receiving and amplifying data on the local data line in common. A first amplifier and a second amplifier).

The global input / output unit 240 is composed of five global lines, and each global input / output line includes the first amplifiers 201, 211, 221, and 231 and the second amplifiers 202, 212, and 222 provided in each local data input / output unit. , 232) output signal.

Each output pre-driver section 260, 270, 280, 290 has a first driver (261, 271, 281, 291) and a second driver (262, 272, 282, 292), each driver on a global line Receive the output signals of the registers 251, 252, 253, 254, and 255, respectively, and have common output lines DQ0, DQ1, DQ2, and DQ3.

Each of the first amplifiers 201, 211, 221, and 231 and the second amplifiers 202, 212, 222, and 232 included in each local data input / output unit may include a first control signal for turning on / off an amplifier. Operated by s0, s1, s2, s3, s4, s5, s6, s7, the first drivers 261, 271, 281, 291 and the second drivers 262, 272, 282 included in each output free driver. 292 is operated by second control signals t0, t1, t2, t3, t4, t5, t6 and t7 for turning on / off the driver.

3 illustrates the output predriver control logic.

As shown, the second control signals t0, t2, t2, t3, t4, t5, t6, t7 are each of the first control signals s0, s1, s2, s3, s4, s5, s6, s7. It is generated by the end (AND) operation of the output enable signal oe which is a DRAM control signal.

4 illustrates a switch control method according to a global input / output line failure.

Hereinafter, the operation of the inventive circuit shown in FIG. 2 will be described with reference to FIG. 4.

In the operation of the circuit according to the failure of the global input / output line gio0, the first amplifier 201 is applied by applying a low level to the control signal s0 of the first amplifier 201 provided in the local data input / output unit 200. The data received from the bit line pair of the memory device by turning off the second amplifier 202 by applying a high level to s1 is received to the global input / output line gio1 through the second amplifier 202.

A low level is applied to the first control signals s2, s4, and s6 to turn off the first amplifiers 211, 221, and 231 to avoid transmission of duplicated data on the same global I / O line. A high level is applied to the signals s3, s5, and s7 to turn on the second amplifiers 212, 222, and 232 so that the global input / output lines gio2, gio3, and gio4 receive data.

 Each register 251, 252, 253, 254 receives data on each global input / output line and outputs an output signal in synchronization with an internal clock.

The first control signal s0, s2, s4, s6 to which the low level is applied is the second control signal that is low level by the end operation of the output enable signal oe to which the high level is applied in synchronization with the read command of the DRAM. (t0, t2, t4, t6) are output, and the output second control signal turns off the first drivers 261, 271, 281, and 291. The first control signal to which the high level is applied, the output enable oe, and the second control signal t1, t3, t5, t7 that are output by the end operation are the second drivers 262, 272, 282. 292 is turned on to transmit the data received from the register unit 250 to the output main driver 300.

Next, after examining the difference between the conventional circuit and the circuit of the present invention, the superiority of the circuit of the present invention will be described.

First, while the conventional circuit shown in FIG. 1 has one amplifier in the local data input / output unit, the circuit of the present invention shown in FIG. 2 has a double number of amplifiers and an extra global input / output line.

Due to this difference, the circuit of the present invention can transmit data avoiding a global input / output line having a large skew effect, and has an advantage of increasing data transmission efficiency by minimizing data loss coming from the line.

The present invention replaces each amplifier 201, 202, 211, 212, 221, 222, 231, and 232 provided in the local data input / output unit of FIG. 2 as well as a read path. In addition, each driver 261, 262, 271, 272, 281, 282, 291, and 292 included in the output predriver can be replaced with an input buffer and used as a write path.

As can be seen from the above, the present invention provides an extra global I / O line, selects a global I / O line with less skew effect, and transmits data, which is very positive for high speed graphic DRAM which is very sensitive to skew on the global I / O line. The effect is expected.

In particular, by providing a plurality of redundant global I / O lines, it is possible to repair bad I / O lines as many as the number of redundant I / O lines.

1 is a diagram illustrating a conventional data input / output device using four global input / output lines.

2 is a view showing a global input output line repair apparatus according to the present invention.

3 is a diagram illustrating an internal configuration of output pre-driver control logic of FIG.

4 is a switch control method according to a failure of the global input-output line of FIG.

Names of main parts in drawings

       200, 210, 220, 230: Local data input / output unit

       240: global input / output unit

       260, 261, 262, 263: output free driver

Claims (2)

Global I / O line repair device for high speed DRAM N local data input / output units for receiving and amplifying data from a pair of bit lines of the memory device; A global input / output unit configured to receive an output signal of the local data input / output unit; A register unit for receiving data of the global input / output unit; N output pre-driver section for receiving the output signal of the register unit and transmits to the output main driver, Each local data input / output unit Paired local data lines; A first amplifier and a second amplifier for receiving and amplifying data on the local data line in common; The global input / output unit It consists of N + 1 global I / O lines, Any i, i + 1th (i is an integer of 1,2,3, ..., N) global line And correspondingly receiving output signals of the first amplifier and the second amplifier provided in the i-th local data input / output unit, respectively. Each output predriver section It has a first driver and a second driver, The first driver and the second driver included in the arbitrary i-th output free driver And an output signal of the i and i + 1th registers among the registers provided on the N + 1 global lines, respectively, and having a common output line.        The method of claim 1, The first amplifier and the second amplifier is selectively operated by the first control signal,       The first driver and the second driver is selectively operated by a second control signal, The first amplifier and the first driver is operated in conjunction with, And the second amplifier and the second driver operate in conjunction with each other.