KR0153609B1 - Masking control circuit for semiconductor memory device - Google Patents

Abstract

A masking control circuit of a video memory device for masking data of a specific bit cell in a video memory cell array block. The masking control circuit is connected in series between a memory cell array, a bit line pair connected to the memory cell array, a data input / output line pair, the bit line pair and the data input / output line pair, and a masking control signal and a column selection. A column select transistor pair and an input / output masking transistor pair for connecting a channel in response to selection of a line, and a column address signal are decoded to select the column select line by an external system clock and simultaneously generate the column select line tracking clock. Column selection means and masking control signal generating means for supplying data input from the outside to the gate of the masking transistor in response to a system clock from the outside.

Description

Masking Control Circuit of Semiconductor Memory Device

1 is a diagram illustrating a relationship between a memory cell array and a peripheral circuit for masking control of a general semiconductor memory device.

2 is a block diagram of a masking control circuit used in a conventional semiconductor memory device.

3 is a timing diagram related to masking control of a conventional semiconductor memory device.

4A and 4B are circuit diagrams of a data input buffer for masking control of a semiconductor memory device according to the present invention.

5 is an operation timing diagram of the logic combination circuit shown in FIG. 4B.

6 is a masking control signal transmission circuit diagram according to the present invention.

7 is a timing diagram related to masking control of a semiconductor memory device according to the present invention.

The present invention relates to a control circuit of a semiconductor memory device, and more particularly to a masking control circuit of a video memory device for masking data of a specific bit cell in a memory cell array block.

Semiconductor memory devices used in the field of image processing, for example, dual port memories and the like, have a block write function as is well known. The block write function refers to a function that can write data corresponding to 16 bits at a time when the memory array block is divided into four blocks and accesses 4 bits of data by one access operation. This block write function is very useful when clearing a window, and is effectively used when writing a large amount of data.

In order to efficiently perform the above block write function, masking control should be performed. Control of masking in a semiconductor memory device writes data in the desired bit cell when executing a write per bit, which is a function for selectively writing data into a desired memory cell in a memory array block. This means that no data other than the bit cell is recorded. Such a masking function of a semiconductor memory device is widely used in a video memory device called a dual port memory. The configuration of the peripheral circuit of the memory cell array for masking in the video memory device is as shown in FIG. 1.

1 is a diagram illustrating a relationship between a memory cell array and a peripheral circuit for masking control of a general semiconductor memory device. This is a structure in which the N type sense amplifier (NSA) 12 connected between the bit line pair BL / BLB is shared by the memory cell arrays 14 and 16 connected to the left and right sides of the bit line pair BL / BLB. Is shown. Such a structure is commonly referred to as a shared N-sense amplifier memory structure. Each of the data line pairs (bit line pairs) of the memory cell array 14 and the data lines (bit lines) of another memory cell array 16 are connected via the pair of bit line isolation gates 18 and 20 to the bit line pair BL /. Respectively connected to the BLB. In this case, an equalizer circuit EQ 22 and a P type sense amplifier PSA independently assigned to each memory cell array are formed between the bit line pairs of the memory cell arrays 14 and 16. 24 are connected, respectively. The channels of the input / output masking transistor 26 and the color selection transistor 28 are connected in series between the lines of the bit line pair BL / BLB and the input / output line pair IO / IOB. The input / output masking transistor 26 and the column select transistor 28 are enMOS transistors, and their respective gates are connected to a masking control line (or masking control signal) IOMi and a column selection line (or column selection signal) CSL, respectively.

Among the above configurations, the input / output masking transistors 26 having drains connected to the bit lines BL and the bit lines BLB of the bit line pair BL / BLB can effectively layout the block light, which is one of the graphic functions of the video memory device. It is a tool for design, and is for pixel masking. The above disable and enable of the masking control signal IOMi should be located between the disable and enable periods of the column select line CSL to prevent invalid write.

Control of input / output masking of the semiconductor memory device having the configuration as shown in FIG. 1 is performed by a masking control circuit configured as shown in FIG.

2 is a block diagram of a masking control circuit used in a conventional semiconductor memory device.

3 is a timing diagram related to masking control of a conventional semiconductor memory device.

Referring to FIG. 3, the masking control operation of FIG. 1 according to FIG. 2 will be described.

Now, row address strobe bar RASB and column address strobe bar CASB and write enable bar WEB as shown in FIG. When input, the logic combination circuit 30 generates the internal write control signal PIWR, which is a predetermined delay when the three input signals are all low, as shown in FIG. 3 so that one side of the data input buffer 32 is generated. Supply to the input node.

The data input buffer 32 processes the data input to the external data input / output pad WIOi as shown in FIG. 3 in response to the activation of the internal write control signal PIWR to generate the masking control signal IOMi as shown in FIG. The masking control signal IOMi generated in this way is input to the gate of the input / output masking transistor 26 shown in FIG. Accordingly, it can be seen that the input / output masking transistor 26 is turned on / off by the masking control signal IOMi output from the data input buffer 32 to control the path of the input / output signal of the column selection transistor 28.

At this time, the disable and enable of the masking control signal IOMi outputted from the data input buffer 32 is disabled and enabled of the effective column select line CSL connected to the gate of the column select transistor 28 as shown in FIG. It must be located in between to prevent the recording of embedded data. The disable and enable of the column select line CSL is disabled and enabled by a column selector (or column decoder; not shown) that decodes the column address signal.

However, the conventional masking control signal generation circuit as shown in FIG. 2 is masked by a method of simply delaying the signal input to the external data input / output pad WIOi by the internal write control signal PIWR outputted from the logic combination circuit 30 as shown in FIG. By generating the control signal IOMi, skew occurs between the column selection line CSL outputted from the column decoder as shown in FIG. 3 and the masking control signal IOMi. That is, in the conventional masking control signal generation circuit, the masking control signal IOMi is generated by a simple signal delay method, thereby causing a problem that the embedded data is written into the memory cell.

Accordingly, an object of the present invention is to provide a masking control circuit of a semiconductor memory device which generates masking control signals of a video memory device in synchronization with an external system clock to eliminate skew with a column selection line to precisely control masking. .

Another object of the present invention is to provide a masking control circuit of a semiconductor memory device which generates a control signal of I / O masking and byte masking DQM masking in synchronization with an external system clock.

Another object of the present invention is to provide a data input buffer for generating column masking and byte masking control signals.

According to another aspect of the present invention, there is provided a masking control circuit for a semiconductor memory device including a memory cell array, a bit line pair connected to the memory cell array, and a data input / output line pair. A column select transistor pair and an input / output masking transistor pair which are connected in series between the data input / output line pairs and connect a channel in response to selection of a masking control signal and a column selection line, and a column address signal is decoded by the external system clock. Column selection means for generating a column selection line tracking clock at the same time as selecting a color selection line, and masking control signal generation means for supplying data input from the outside to the gate of the masking transistor in response to a system clock from the outside; It is characterized by the configuration.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4A and 4B are circuit diagrams of a data input buffer for masking control of a semiconductor memory device according to the present invention. 4A shows a configuration for activating the column select line CSL in synchronization with the external system clock CLK and generating a tracking pulse CSLB for tracking the selection of the column select line CSL. In addition, in FIG. 4B, a load mask register set is formed by logically combining the singer system clock CLK, the row address strobe signal RASB, the column address strobe CASB, the write enable signal WEB, and the control signals (address signals) A5 and A6. Data input for generating control signal PIWMiB for generating input / output masking control signal IOMI by data input from external data input / output pad WIOi including logic combination circuit 40 for generating LMR and load color register set The buffer is shown.

5 is an operation timing diagram of the logic combination circuit shown in FIG. 4B. The relationship between the system clock CLK, the row address strobe signal RASB, the column address strobe CASB, the write enable signal WEB, and the control signals A5 and A6 is shown in FIG. The output relationship of the mask load clock LMR and the color load clock LCR is shown.

6 is a masking control signal transmission circuit diagram according to the present invention, which transmits the control signal PIWMiB generated from FIG. 4b as a masking control signal IOMi by the tracking pulse CSLB output from the column selection tracking circuit 36 of FIG. 4a. It is shown. At this time, the final output of FIG. 6 is provided to the gate of the masking transistor pair 26 shown in FIG.

FIG. 7 is a timing diagram related to masking control of the semiconductor memory device according to the present invention, and is a diagram for explaining the operations of FIGS. 4A, 4B, and 6 more easily.

The operation of the embodiment according to the present invention will be described with reference to FIGS. 4A, 4B, 5 and 7.

Now, when the system clock CLK as shown in Fig. 7 is supplied from the outside, it is supplied to the clock combination 34 shown in Fig. 4A and the logic combination circuit 40 shown in Fig. 4B. The clock buffer 32 buffers the external system clock CLK to output the internal clock PICLK and the internal clock PICP as shown in FIG. The internal clock PICP is input to a column tracking circuit 36 and a column selector (or column decoder) 38 connected to the output node of the clock buffer 34. The color selector 38 decodes the input column address signal CAi and selects the corresponding column selection line CSL shown in FIG. 1 in synchronization with the internal clock PICP as shown in FIG. That is, the column selection line CSL is activated in synchronization with the internal clock PICP.

The column select tracking circuit 36 generates the tracking pulse CSLB as shown in FIG. 7 by the input of the internal clock PICP synchronized with the external system clock CLK. The column selection signal CSL generated as shown in FIG. 7 is supplied to the gate of the column transistor pair 28 shown in FIG. 1 to connect each line of the input / output line pair IO / IOB to the drain (or source) of the masking transistor pair 26. . The generated tracking pulse CSLB is supplied to the control signal terminal of the transmission gate 68 in the masking control signal transmission circuit constructed as shown in FIG.

On the other hand, the logic combination circuit 40 shown in FIG. 4B has an external system clock CLK inputted as shown in FIG. 5, a row address strobe signal RASB, a column address strobe CASB, a write enable signal WEB and a control signal (address signal) A5, A6. Are combined to generate a load mask register set LMR and a load color register set LCR as shown in FIG. Each of the mask load clock LMR and the color load clock LCRs generated as described above is supplied to the control terminals of the first and second transmission circuits 42 and 44 for inputting data synchronized by the internal clock PCLK. The input nodes of the first and second transfer circuits 42 and 44 are connected to an output node of data input means for inputting data from an external data input / output pad WIOi.

The data input means includes a buffering buffer 46 for inputting to an external data input / output pad WIOi, and a third transmission circuit 48 for transmitting the output of the buffer 46 to an output node in response to a first logic of an internal clock PICLK, for example, a row. And a fourth transmission circuit 48 connected to the output of the third transmission circuit 48 and transmitting to the output node in response to a second logic, for example, high, of the internal clock PICLK. The data input means configured as described above inverts and outputs the external data output from the buffer 46 according to the input of the internal clock PICLK, and outputs the signal with a predetermined delay. The delayed data includes the first, second transmission circuits, 44, 46. It is supplied to the input node of. In this case, each of the first and second transfer circuits 42, 44 and the third and fourth transfer circuits 48 and 50 is connected to a transfer gate composed of a PMOS transistor connected in parallel to an NMOS transistor and an output node of the transfer gate. It is configured to include an inverter and another inverter for controlling the gate of the PMOS transistor or the NMOS transistor, which can be easily understood by those skilled in the art without detailed description. Therefore, when the mask load clock LMR output from the logic combination circuit 40 is output at logic high as shown in FIG. 5, the first transmission circuit 42 is dependent on the state of the external data input in synchronization with the internal clock PICLK. The masking control signal is supplied to one input node of the NOA gate 54.

Another input node of Noah Gate 54 is supplied with a byte masking control signal DQMi (where i is a natural number) for controlling byte masking. When not in the byte masking mode, the byte masking control signal DQMi is supplied in a state of logic low. Accordingly, when data input to the external data input / output pad WIOi is input in a high state, the NOA gate 54 outputs the control signal PIWMiB, which is the output of the inverters 56 connected to the output node, to low as shown in FIG.

The control signal PIWMiB output from the data input buffer configured as shown in FIG. 4B is inverted by the inverter 66 in the masking control signal transmission circuit configured as shown in FIG. 6 and input to the transfer gate 68. At this time, the transfer gate 68 is transferred from the above-described column selection tracking circuit 36 to the input node of the inverter 72 by the tracking pulse CSLB output as shown in FIG. 7, and the inverter 72 inverts the masking transistor pair 26 of FIG. Off to mask the data records for that column. Therefore, the masking control signal IOMi and the gate of the column selection transistor pair 28 are controlled by transmitting the input / output masking control signal to the gate of the masking transistor pair 26 by a tracking pulse CSLB that tracks the deactivation of the column selection line CSL in synchronization with the external system clock. Since no skew occurs between the activation signals of the column select line CSL, the input / output masking can be precisely controlled.

On the other hand, the data input buffer configured as shown in FIG. 4 can easily mask the byte, and the operation process thereof is as follows. Byte masking control signal of video memory device DQMO masks data input to external I / O pads WIO0 to WIO7, DQM1 to external I / O pads WIO8 to WIO15, DQM2 to external I / O pads WIO16 to WIO23, and DQM3 to external I / O pads WIO24 to WI31 It is supposed to be done. This byte masking control signal is supplied to another input node of Noah gate 54 in the data input buffer connected to the input node to the corresponding external input / output pad WIOi through a DQM buffer (not shown). Therefore, when the byte masking control signal DQMi is input to logic high in order to byte-mask the data WIOi input to FIG. 4B, the masking control output from FIG. 6 by disabling the control signal PWIMiB output from Noagate 54 to low. The signal IOMi is also disabled low to perform byte masking for the write.

As described above, the present invention controls masking of input / output data by controlling the control of a masking transistor connected in series with a column select transistor connected between a bit line pair and an input / output line pair of a video memory cell array in synchronization with an external system clock. There is an advantage to be accurate.

Claims (4)

A masking control circuit of a semiconductor memory device having a memory cell array, a bit line pair connected to the memory cell array, and a data input / output line pair, the serial connection between the bit line pair and the data input / output line pair. A column select transistor pair and an input / output masking transistor pair for connecting a channel in response to selection of a masking control signal and a column select line, and a column address signal decoded to select the column select line by an external system clock and simultaneously Column selection means for generating a selection line tracking clock, and masking control signal generation means for supplying data input from the outside to a gate of the masking transistor in response to a system clock from the outside of the semiconductor memory device. Masking control circuit. The masking control signal generating means according to claim 1, wherein the masking control signal generating means generates a mask load clock and a color load clock at different periods by logically combining the access signals for accessing data of the memory cell array and the external system clock. A control clock generating means, data input means for transmitting data input from the outside as a masking control signal by the mask load clock, and the masking transistor in synchronization with the generated column selection line tracking clock; A masking control circuit of a semiconductor memory device, characterized in that it comprises a transfer means for supplying a pair of gates. 2. The semiconductor memory according to claim 1, wherein the masking control signal generating means comprises masking control signal generating means for supplying a byte masking control signal input from the outside to a gate of a masking transistor in response to the system clock. Masking control circuit of the device. 3. The masking control circuit of a semiconductor memory device according to claim 2, wherein said data input means further comprises means for supplying an input of a byte masking control signal input from the outside to said transfer means.