CN102129168A - Photoresist graph correction method - Google Patents
Photoresist graph correction method Download PDFInfo
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- CN102129168A CN102129168A CN2010100227197A CN201010022719A CN102129168A CN 102129168 A CN102129168 A CN 102129168A CN 2010100227197 A CN2010100227197 A CN 2010100227197A CN 201010022719 A CN201010022719 A CN 201010022719A CN 102129168 A CN102129168 A CN 102129168A
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Abstract
The invention discloses a photoresist graph correction method. The method comprises the following steps of: establishing a database of a relationship among the transmission rate of the area of a photoresist graph exposed from a substrate to the area of the substrate, a photoresist graph after develop inspection-critical dimension (ADI-CD) and an etching correction time; providing the substrate, wherein a dielectric layer is formed on the surface of the substrate; forming the photoresist graph on the surface of the dielectric layer; selecting the etching correction time from the database according to the transmission rate of the area of the photoresist graph exposed from the substrate to the area of the substrate and the photoresist graph ADI-CD; and performing etching correction on the photoresist graph by adopting the etching correction time. Grooves formed by the corrected photoresist graph provided by the method have small etching deviation and high efficiency.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly the modification method of photoresist figure.
Background technology
At present, development along with VLSI (very large scale integrated circuit), the circuit design size is more and more littler, when particularly having arrived the technology below the 65nm, the variation of the characteristic dimension of circuit (Critical Dimension) is also increasing for the influence of device performance, and for example the feature size variations of circuit can directly cause the variation of device travelling speed.
Owing to be exposed the influence of the resolution limit (ResolutionLimit) of board (Optical Exposure Tool), carrying out exposure technology when being transferred to circuitous pattern on the photoresist, just be easy to produce deviation to being formed on circuitous pattern on the mask (Mask).In U.S. Pat 6042973, can find to form the resolution of the inferior parsing fence (Sub-resolution Grating) of sub-circular in order to the raising circuitous pattern at the circuitous pattern edge, but the deviation that this method can't avoid circuitous pattern to shift.For fear of the deviation that mask pattern shifts, existing semiconductor technology all is to utilize drift correction to overcome the deviation that existing mask pattern shifts, and concrete steps comprise:
Semiconductor substrate is provided;
On described Semiconductor substrate, form photoresist layer;
Described photoresist layer is exposed, develops, form the photoresist figure;
(After Develop Inspection-CriticalDimension ADI-CD) checks to the characteristic dimension of the described photoresist figure after developing;
Determine to revise the deviation of photoresist figure according to ADI-CD.
But, development along with VLSI (very large scale integrated circuit), the existing modification method of determining to revise the deviation of photoresist figure according to ADI-CD has certain limitation, photoresist figure for different batches, all need to determine ADI-CD at every turn, determine the modification method of the deviation of correction photoresist figure then according to ADI-CD, above-mentioned modification method efficient is lower.
Summary of the invention
The problem that the present invention solves provides the modification method of the deviation of effective correction photoresist figure.
For addressing the above problem, the invention provides a kind of modification method of deviation of photoresist figure, comprising: set up the photoresist figure and expose the area of substrate and ratio, photoresist figure ADI-CD and the database of etching correction time of Substrate Area; Substrate is provided, and described substrate surface is formed with dielectric layer; Form the photoresist figure on described dielectric layer surface; Expose the area of substrate and the ratio and the described photoresist figure ADI-CD of Substrate Area according to described photoresist figure, the selective etching correction time from database, adopt the described etching correction time that described photoresist figure is carried out the etching correction.
Compared with prior art, the present invention has the following advantages: set up the photoresist figure and expose the area of substrate and ratio, photoresist figure ADI-CD and the database of etching correction time of Substrate Area, expose the area of substrate and the ratio selective etching correction time of Substrate Area according to the photoresist figure, the etching groove deviation that adopts revised photoresist figure to form is little.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by physical size equal proportion convergent-divergent.
Fig. 1 is the schematic flow sheet of photoresist figure modification method one embodiment provided by the invention;
Fig. 2 to Fig. 6 is the process synoptic diagram of photoresist figure modification method one embodiment provided by the invention;
Fig. 7 carries out the synoptic diagram that etching forms groove for being mask with the corrected photoresist figure of the present invention to described dielectric layer.
Embodiment
By background technology as can be known, development along with VLSI (very large scale integrated circuit), the existing modification method of determining to revise the deviation of photoresist figure according to ADI-CD has certain limitation, photoresist figure for different batches, all need to determine ADI-CD at every turn, determine to revise the modification method of the deviation of photoresist figure then according to ADI-CD, efficient is lower.
For this reason, the present inventor is through a large amount of experiments, above-mentioned experiment is analyzed, the photoresist figure that discovery has different batches has different pitch (Pitch), has intensity (Dense) and sparse type different graphical distribution situations such as (Iso), for this reason, the present inventor takes all factors into consideration the photoresist figure difference of different batches, propose a kind of photoresist figure modification method of optimization,, comprising with reference to figure 1:
Step S101 sets up the database that the photoresist figure exposes the area of substrate and the ratio of Substrate Area (Transmission Rate), photoresist figure ADI-CD and etching correction time relation;
Step S102 provides substrate, and described substrate surface is formed with dielectric layer;
Step S103 forms the photoresist figure on described dielectric layer surface;
Step S104 exposes the area of substrate and the ratio and the described photoresist figure ADI-CD of Substrate Area according to described photoresist figure, the selective etching correction time from database, adopts the described etching correction time that described photoresist figure is carried out the etching correction.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes synoptic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the sectional view of expression device architecture can be disobeyed general ratio and be done local the amplification, and described synoptic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 2 to Fig. 6 is the process synoptic diagram of photoresist figure modification method one embodiment provided by the invention, below in conjunction with Fig. 1 to Fig. 6 the specific embodiment of the present invention is described in detail.
Step S101 sets up the photoresist figure and exposes the area of substrate and the ratio of Substrate Area (Transmission Rate), photoresist figure ADI-CD and the database of etching correction time.
Described photoresist figure exposes the area of substrate and the ratio of Substrate Area (TransmissionRate) exposes the area of substrate and the ratio of Substrate Area for the photoresist figure that is formed on the substrate, but calculate described photoresist figure and expose the area of substrate and the ratio of Substrate Area for convenient, also can carry out mathematical statistics and be similar to and obtain the value that the photoresist figure exposes the ratio of the area of substrate and Substrate Area the mask that forms described photoresist figure.
The present inventor is through a large amount of experiments, find that etching deviation that different photoresist figures exposes the area of substrate and the ratio of Substrate Area (Transmission Rate) and the groove that adopts described photoresist to form as shown in Figure 2, experimental data to Fig. 2 is carried out the mathematics match, obtaining the relational expression that etching deviation and photoresist figure expose the area of substrate and the ratio of Substrate Area (Transmission Rate) is y=0.0017x-0.0465, for further understanding the present invention, with concrete data instance, shown in the A point of Fig. 2, when the photoresist figure exposed the area of substrate and the ratio of Substrate Area (Transmission Rate) and is 30.3 (unit is %), etching deviation was about 0.002 (unit is μ m); Shown in the B point of Fig. 2, when the photoresist figure exposed the area of substrate and the ratio of Substrate Area (Transmission Rate) and is 46.8 (unit is %), etching deviation was about 0.003 (unit is μ m).From above-mentioned data analysis as can be known, along with the photoresist figure exposes the variation of the ratio of the area of substrate and Substrate Area, etching deviation also changes thereupon.
For this reason, the inventor exposes the correction time that the area of substrate and the ratio of Substrate Area (Transmission Rate), photoresist figure ADI-CD determine etching according to the photoresist figure, and Fig. 3 is that the photoresist figure that the present invention sets up exposes the area of substrate and the ratio of Substrate Area (TransmissionRate), photoresist figure ADI-CD and the graph of a relation of etching correction time.As shown in Figure 3, make according to simulation or by actual process, collect data, set up the photoresist figure and expose the area of substrate and the ratio of Substrate Area (Transmission Rate), photoresist figure ADI-CD and the relational database of etching correction time.
Step S102 provides substrate, and described substrate surface is formed with dielectric layer.
With reference to figure 4, described substrate 100 can be substrate (part that comprises integrated circuit and other elements), the patterning of multi layer substrate (silicon substrate that for example, has covering dielectric and metal film), classification substrate, silicon-on-insulator substrate (SOI), epitaxial silicon substrate, section processes or the substrate that is not patterned.
Still with reference to figure 4, described substrate 100 surfaces are formed with dielectric layer 110, described dielectric layer 110 is used for active area in the substrate 100 and the isolation between the active area perhaps are used for lead on the substrate 100 and the isolation between the lead, and the thickness of described dielectric layer 110 is 20 nanometer to 5000 nanometers.
Concrete described dielectric layer 110 can be before-metal medium layer (Pre-Metal Dielectric, PMD), also can be interlayer dielectric layer (Inter-Metal Dielectric, ILD), it needs to be noted that described dielectric layer can also be that single coating also can be the multiple-level stack structure.
Before-metal medium layer is to be deposited on the substrate with MOS device, utilize depositing operation to form, can form groove at subsequent technique in before-metal medium layer, form connecting hole with metal filled groove, described connecting hole is used for connecting the electrode of MOS device and the plain conductor of upper layer interconnects layer.
Interlayer dielectric layer is the dielectric layer of postchannel process between metal interconnecting layer, can form groove in the interlayer dielectric layer in subsequent technique, forms connecting hole with metal filled groove, and described connecting hole is used for connecting the lead of adjacent metal interconnects layer.
The material of described dielectric layer 110 is selected from SiO usually
2The perhaps SiO of Can Zaing
2USG (Undoped Silicon Glass for example, the silex glass that does not have doping), BPSG (BorophosphosilicateGlass, the silex glass of boron phosphorus doped), BSG (Borosilicate Glass, the silex glass of doped with boron), PSG (Phosphosilitcate Glass, the silex glass of Doping Phosphorus) etc.
Described dielectric layer 110 generally selects for use the dielectric material of low-k, the material of described dielectric layer 110 specifically to be selected from the silit (BLOK) that monox (Black Diamond) that fluorine silex glass (FSG), carbon mix and nitrogen mix at 130 nanometers and following process node.
The formation technology of described dielectric layer 110 can be any conventional vacuum coating technology, for example atomic deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) or the like are not here done and are given unnecessary details.
Step S103 forms the photoresist figure on described dielectric layer surface.
In the present embodiment, described photoresist figure is used to define groove figure, and as the mask of groove figure, described photoresist figure thickness is 500 nanometers to 2 micron.
With reference to figure 5, the formation step of described photoresist figure 120 comprises: form photoresist layer (not shown) on described dielectric layer 110 surfaces; To described photoresist layer exposure imaging, form photoresist figure 120.
Step S104 exposes the area of substrate and the ratio and the described photoresist figure ADI-CD of Substrate Area according to described photoresist figure, the selective etching correction time from database, adopts the described etching correction time that described photoresist figure is carried out the etching correction.
With reference to figure 6, described etching correction also can consume certain photoresist figure 120 thickness when revising described photoresist figure 120, but because the thickness of photoresist figure 120 is enough thick, the etching correction can full consumption photoresist figure 120.
It needs to be noted, described etching correction using plasma etching technics, the concrete parameter of described plasma etch process comprises: the selective etching correction time from database, etching cavity pressure is 10 millitorr to 300 millitorrs, etching power is 50 watts to 200 watts, and etching gas is CF
4, CF
4Flow is 10SCCM to 50SCCM, and assist gas is Ar, and the Ar flow is 10SCCM to 50SCCM.
With reference to figure 7, after above-mentioned technology is finished, with described corrected photoresist figure 120 is mask, described dielectric layer 110 is carried out etching, form groove 111, by narration before as can be known, expose the area of substrate and ratio of Substrate Area (Transmission Rate) and ADI-CD owing to take all factors into consideration the photoresist figure, the etching deviation of described groove 111 is less.
The present invention exposes the ratio of the area of substrate and Substrate Area and described photoresist figure ADI-CD, the database of etching correction time according to described photoresist figure, the selective etching correction time from database, described photoresist figure is carried out the etching correction, and the etching groove deviation that adopts revised photoresist figure to form is little.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (9)
1. the modification method of a photoresist figure comprises:
Set up the database of ratio, photoresist figure ADI-CD and etching correction time relation that the photoresist figure exposes the area of substrate and Substrate Area;
Substrate is provided, and described substrate surface is formed with dielectric layer;
Form the photoresist figure on described dielectric layer surface;
Expose the area of substrate and the ratio and the described photoresist figure ADI-CD of Substrate Area according to described photoresist figure, the selective etching correction time from database, adopt the described etching correction time that described photoresist figure is carried out the etching correction.
2. the modification method of photoresist figure as claimed in claim 1 is characterized in that, also comprises step: with described corrected photoresist figure is mask, and described dielectric layer is carried out etching, forms groove.
3. the modification method of photoresist figure as claimed in claim 1 is characterized in that, described photoresist figure is used to define groove figure.
4. the modification method of photoresist figure as claimed in claim 1 is characterized in that, the technology of described etching correction is plasma etch process.
5. the modification method of photoresist figure as claimed in claim 4 is characterized in that, the concrete parameter of described plasma etch process comprises: etching cavity pressure is 10 millitorr to 300 millitorrs, and etching power is 50 watts to 200 watts, and etching gas is CF
4, CF
4Flow is 10SCCM to 50SCCM, and assist gas is Ar, and the Ar flow is 10SCCM to 50SCCM.
6. the modification method of photoresist figure as claimed in claim 1 is characterized in that, the formation step of described photoresist figure comprises: form photoresist layer on described dielectric layer surface; To described photoresist layer exposure imaging, form the photoresist figure.
7. the modification method of photoresist figure as claimed in claim 1 is characterized in that, described photoresist layer thickness is 500 nanometers to 2 micron.
8. the modification method of photoresist figure as claimed in claim 1 is characterized in that, described dielectric layer is single coating or multiple-level stack structure.
9. the modification method of photoresist figure as claimed in claim 1 is characterized in that, described substrate is multi layer substrate, classification substrate, silicon-on-insulator substrate (SOI), epitaxial silicon substrate, substrate, the patterning of section processes or the substrate that is not patterned.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010022719 CN102129168B (en) | 2010-01-12 | 2010-01-12 | Photoresist graph correction method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010022719 CN102129168B (en) | 2010-01-12 | 2010-01-12 | Photoresist graph correction method |
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| CN102129168A true CN102129168A (en) | 2011-07-20 |
| CN102129168B CN102129168B (en) | 2012-12-05 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108020991A (en) * | 2016-10-31 | 2018-05-11 | 无锡中微掩模电子有限公司 | Mask plate for integrated circuit carries on the back exposure method |
| CN110928149A (en) * | 2018-09-20 | 2020-03-27 | 长鑫存储技术有限公司 | Control method and control system for critical dimension |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6320402B1 (en) * | 2000-02-03 | 2001-11-20 | Advanced Micro Devices Inc | Parallel inspection of semiconductor wafers by a plurality of different inspection stations to maximize throughput |
| CN1141732C (en) * | 2000-10-17 | 2004-03-10 | 联华电子股份有限公司 | Method of improving outline of photoresist pattern |
| US7305651B2 (en) * | 2005-06-17 | 2007-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mask CD correction based on global pattern density |
| US7759136B2 (en) * | 2006-03-29 | 2010-07-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Critical dimension (CD) control by spectrum metrology |
| CN101430566B (en) * | 2007-11-08 | 2010-12-22 | 中芯国际集成电路制造(上海)有限公司 | Method for controlling etching deviation |
| CN101592858B (en) * | 2008-05-30 | 2011-05-04 | 中芯国际集成电路制造(北京)有限公司 | Method for amending photoresist pattern error |
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2010
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108020991A (en) * | 2016-10-31 | 2018-05-11 | 无锡中微掩模电子有限公司 | Mask plate for integrated circuit carries on the back exposure method |
| CN110928149A (en) * | 2018-09-20 | 2020-03-27 | 长鑫存储技术有限公司 | Control method and control system for critical dimension |
| CN110928149B (en) * | 2018-09-20 | 2024-04-19 | 长鑫存储技术有限公司 | Control method and control system for critical dimension |
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Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20121102 |
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Effective date of registration: 20121102 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Patentee after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |