CN102110028A - NAND flash memory as well as data checking method and device thereof - Google Patents
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Abstract
The invention is suitable for the memory field, and provides an NAND flash memory as well as a data checking method and device thereof. The method comprises the following steps: checking the row and the column of each 256-byte datum written to an NAND flash memory file to generate a first check code; checking the row and the column of each 256-byte datum read from the NAND flash memory file to generate a second check code; and processing the first check code and the second check code by XOR treatment, and determining whether the datum in the NAND flash memory has a fault according to the XOR treatment result. According to the embodiment of the invention, the method can check the data in the NAND flash memory in the software form, and is suitable for any platform.
Description
Technical field
The invention belongs to memory area, relate in particular to the method for calibration and the device of a kind of nand flash memory and data thereof.
Background technology
Because the technology of nand flash memory can not guarantee the storage in the nand flash memory and arrange (MemoryArray) keeps performance in its life cycle reliability, therefore, can bad piece of generation in the production of NAN type flash memory and use.When time sequential routine and circuit stability are relatively poor, if there is bad piece in nand flash memory, then may will cause whole flash block or Hash memory pages not to read or all to make mistakes, if then NAND time sequential routine and circuit stability are better, generally exist in the Hash memory pages (as 512 bytes) of bad piece and have only one or several data to make mistakes.In nand flash memory was handled, (Error Checking and Correction ECC) checked even corrects the mistake that exists in the nand flash memory generally to adopt bug check and correct algorithm.
Prior art provides the hardware circuit implementation of ECC, the hardware circuit implementation of this ECC can be corrected the single-bit error in the nand flash memory and be detected the dibit mistake, and computing velocity is fast, but can't correct the mistake more than 1 bit, and the mistake more than 2 bits is not guaranteed to detect.Because prior art is to realize the ECC of nand flash memory by hardware circuit, it can only finish on development board when making and produce firm file, therefore, efficient is low, and finishes owing to being transplanted on other platforms, thereby makes the use of ECC verification be restricted.
Summary of the invention
The purpose of the embodiment of the invention is to provide the method for calibration of data in a kind of nand flash memory, is intended to solve the problem that existing hardware realization method of calibration can't be transplanted to other platforms.
The embodiment of the invention is achieved in that the method for calibration of data in a kind of nand flash memory, and described method comprises the steps:
When in the nand flash memory page or leaf, writing data, the data of per 256 bytes of writing are carried out row verification and row verification respectively, generate first check code, described first check code comprises the first row check code and the first row check code;
When reading of data from the nand flash memory page or leaf, the data of per 256 bytes of reading from nand flash memory are carried out row verification and row verification respectively, generate second check code, described second check code comprises the secondary series check code and the second row check code;
First check code and the second check code step-by-step are carried out the XOR processing, and judge according to the XOR result whether the data in the nand flash memory make mistakes.
Another purpose of the embodiment of the invention is to provide the calibration equipment of data in a kind of nand flash memory, and described device comprises:
The first check code generation unit is used for when the nand flash memory page or leaf writes data, and the data of per 256 bytes of writing are carried out row verification and row verification respectively, generates first check code, and described first check code comprises the first row check code and the first row check code;
The second check code generation unit, be used for the time from nand flash memory page or leaf reading of data, the data of per 256 bytes of reading from nand flash memory are carried out row verification and row verification respectively, generate second check code, described second check code comprises the secondary series check code and the second row check code;
The data check unit is used for first check code and the second check code step-by-step are carried out the XOR processing, and judges according to the XOR result whether the data in the nand flash memory make mistakes.
Another purpose of the embodiment of the invention is to provide a kind of nand flash memory, and described flash memory comprises the calibration equipment of data in the described nand flash memory.
In embodiments of the present invention, carry out verification by realize the data in the nand flash memory according to the software of said method flow performing, when making the image file of nand flash memory, by increase this data check software for data according to the said method flow performing, can realize verification to the data of nand flash memory, this method of calibration is owing to realize by software, thereby and platform independence, make it applicable to any platform.
Description of drawings
Fig. 1 is the realization flow figure of the method for calibration of data in the nand flash memory that provides of the embodiment of the invention;
Fig. 2 is the exemplary plot of the row verification rule that provides of the embodiment of the invention;
Fig. 3 is the exemplary plot of the capable verification rule that provides of the embodiment of the invention;
Fig. 4 is the structured flowchart of the calibration equipment of data in the nand flash memory that provides of the embodiment of the invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
In embodiments of the present invention, when in the nand flash memory page or leaf, writing data, data according to per 256 bytes that write generate first check code, this first check code comprises first row check code and the secondary series check code, when reading of data from the nand flash memory page or leaf, data according to per 256 bytes that read from nand flash memory generate second check code, this second check code comprises second row check code and the secondary series check code, first check code and the second check code step-by-step are carried out the XOR processing, and judge according to the XOR result whether the data in the nand flash memory make mistakes.
Fig. 1 shows the realization flow of the method for calibration of data in the nand flash memory that the embodiment of the invention provides, and details are as follows:
In step S101, when in the nand flash memory page or leaf, writing data, the data of per 256 bytes of writing are carried out row verification and row verification respectively, generate first check code, this first check code comprises the first row check code and the first row check code.
It is specific as follows wherein the data of per 256 bytes of writing to be carried out the step of row verification:
See also Fig. 2, the exemplary plot of the row verification rule that provides for the embodiment of the invention, details are as follows:
The data ordering of A, per 256 bytes that will write becomes the matrixes of 256 row and 8 row, and each element is represented a bit in 256 bytes in the matrix.
B, the default row verification rule of employing are carried out the row verification to the bit in the matrix, generate the first row check code, and wherein Yu She row verification rule is specially:
B1, the bit that XOR in the above-mentioned matrix is handled 1 row are skipped the bit of 1 row again, and circulation is carried out, and all row all dispose in matrix, generate the row polar code of correspondence; As adopting following row polarity to generate formulate:
CP0=Bit0^Bit2^Bit4^Bit6; Wherein CP0 is the row polar code of generation.Bit0, Bit2, Bit4, Bit6 are respectively the bit in the row of the 0th in the above-mentioned matrix, the 2nd row, the 4th row, the 6th row.Symbol " ^ " expression carrying out XOR is handled.Therefore formula CP0=Bit0^Bit2^Bit4^Bit6 is meant that all bits in the 0th row, the 2nd row, the 4th row and the 6th row in this matrix are carried out XOR to be handled, and obtains corresponding row polar code.Be that the actual 256*4=1024 of being of a CP0 bit carries out the row polar code that XOR is handled the back generation.
B2, to behind the bit of skipping 1 row in the above-mentioned matrix again XOR handle the bit of 1 row, circulation is carried out, all row all dispose in matrix, generate the row polar code of correspondence; As adopting following row polarity to generate formulate:
CP1=Bit1^Bit3^Bit5^Bit7; Wherein CP1 is the row polar code of generation.Bit1, Bit3, Bit5, Bit7 are respectively the bit in the row of the 1st in the above-mentioned matrix, the 3rd row, the 5th row, the 7th row.Symbol " ^ " expression carrying out XOR is handled.Therefore formula CP1=Bit1^Bit3^Bit5^Bit7 is meant that all bits in the 1st row, the 3rd row, the 5th row and the 7th row in this matrix are carried out XOR to be handled, and obtains corresponding row polar code.Be that the actual 256*4=1024 of being of a CP0 bit carries out the row polar code that XOR is handled the back generation.
B3, the bits that XOR in the above-mentioned matrix is handled 2 row are skipped the bits of 2 row again, and circulation is carried out, and all row all dispose in matrix, generate the row polar code of correspondence; As adopting following row polarity to generate formulate:
CP2=Bit0^Bit1^Bit4^Bit5; Wherein CP2 is the row polar code of generation.
B4, to the bits of skipping 2 row in the above-mentioned matrix again XOR handle the bits of 2 row, circulation is carried out, all row all dispose in matrix, generate the row polar code of correspondence; As adopting following row polarity to generate formulate:
CP3=Bit2^Bit3^Bit6^Bit7; Wherein CP3 is the row polar code of generation.
B5, the bits that XOR in the above-mentioned matrix is handled 4 row are skipped the bits of 4 row again, and circulation is carried out, and all row all dispose in matrix, generate the row polar code of correspondence; As adopting following row polarity to generate formulate:
CP4=Bit0^Bit1^Bit2^Bit3; Wherein CP4 is the row polar code of generation.
B6, to the bits of skipping 4 row in the above-mentioned matrix again XOR handle the bits of 4 row, circulation is carried out, all row all dispose in matrix, generate the row polar code of correspondence; As adopting following row polarity to generate formulate:
CP5=Bit4^Bit5^Bit6^Bit7; Wherein CP5 is the row polar code of generation.
C, all row polar codes that will obtain are combined into the first row check code.Wherein Zu He mode is exactly that the row polar code that will obtain each bit directly is combined into first a row check code that comprises a plurality of bits.As can obtaining the row polar code of 6 bits by step B, the row polar code of 6 bits obtaining is directly made up, obtain first a row check code that comprises 6 bits.
It is specific as follows wherein the data of per 256 bytes of writing to be gone the step of verification:
See also Fig. 3, the exemplary plot of the row verification rule that provides for the embodiment of the invention, details are as follows:
The data ordering of D, per 256 bytes that will write becomes the matrixes of 256 row and 8 row, and each element is represented a bit in 256 bytes in the matrix.
The capable verification rule that E, employing are preset generates corresponding capable polar code to the capable verification of the bit in the matrix, in embodiments of the present invention, adopts RP0-RP15 to represent the capable polar code of correspondence.Wherein Yu She capable verification rule is specific as follows:
E1, the bit that XOR in the above-mentioned matrix is handled 1 row are skipped the bit of 1 row again, and circulation is carried out, and all row all dispose in matrix, generate corresponding capable polar code;
E2, to behind the bit of skipping 1 row in the above-mentioned matrix again XOR handle the bit of 1 row, circulation is carried out, all row all dispose in matrix, generate corresponding capable polar code;
E3, the bits that XOR in the above-mentioned matrix is handled 2 row are skipped the bits of 2 row again, and circulation is carried out, and all row all dispose in matrix, generate corresponding capable polar code;
E4, to the bits of skipping 2 row in the above-mentioned matrix again XOR handle the bits of 2 row, circulation is carried out, all row all dispose in matrix, generate corresponding row polar code;
E5, the bits that XOR in the above-mentioned matrix is handled 4 row are skipped the bits of 4 row again, and circulation is carried out, and all row all dispose in matrix, generate corresponding capable polar code;
E6, to the bits of skipping 4 row in the above-mentioned matrix again XOR handle the bits of 4 row, circulation is carried out, all row all dispose in matrix, generate corresponding capable polar code;
E7, the bits that XOR in the above-mentioned matrix is handled 8 row are skipped the bits of 8 row again, and circulation is carried out, and all row all dispose in matrix, generate corresponding capable polar code;
E8, to behind the bits of skipping 8 row in the above-mentioned matrix again XOR handle the bits of 8 row, circulation is carried out, all row all dispose in matrix, generate corresponding capable polar code;
E9, the bits that XOR in the above-mentioned matrix is handled 16 row are skipped the bits of 16 row again, and circulation is carried out, and all row all dispose in matrix, generate corresponding capable polar code;
E10, to the bits of skipping 16 row in the above-mentioned matrix again XOR handle the bits of 16 row, circulation is carried out, all row all dispose in matrix, generate corresponding row polar code;
E11, the bits that XOR in the above-mentioned matrix is handled 32 row are skipped the bits of 32 row again, and circulation is carried out, and all row all dispose in matrix, generate corresponding capable polar code;
E12, to the bits of skipping 32 row in the above-mentioned matrix again XOR handle the bits of 32 row, circulation is carried out, all row all dispose in matrix, generate corresponding capable polar code;
E13, the bits that XOR in the above-mentioned matrix is handled 64 row are skipped the bits of 64 row again, and circulation is carried out, and all row all dispose in matrix, generate corresponding capable polar code;
E14, to the bits of skipping 64 row in the above-mentioned matrix again XOR handle the bits of 64 row, circulation is carried out, all row all dispose in matrix, generate corresponding row polar code;
E15, the bits that XOR in the above-mentioned matrix is handled 128 row are skipped the bits of 128 row again, and circulation is carried out, and all row all dispose in matrix, generate corresponding capable polar code;
E16, to the bits of skipping 128 row in the above-mentioned matrix again XOR handle the bits of 128 row, circulation is carried out, all row all dispose in matrix, generate corresponding capable polar code.
F, all row polar codes that will obtain are combined into the first row check code.Wherein Zu He mode is exactly that the capable polar code that will obtain each bit directly is combined into first a row check code that comprises a plurality of bits.As can obtaining the row polar code of 16 bits by step e, the row polar code of 16 bits obtaining is directly made up, obtain first a row check code that comprises 16 bits.
In sum, when the data that write to the nand flash memory page or leaf being gone after the verification of check code row, can generate first row check code of 6 bits and the first row check code of 16 bits, row check code and the row result who generates directly made up, can obtain first check code.In order to preserve first check code that will generate, generally comprise the data field of 512 bytes and the outer data field (out-of-band of band of 16 bytes in each nand flash memory page or leaf, OOB), in embodiments of the present invention, first check code that generates is stored to the OOB district of nand flash memory page or leaf.Owing to generally comprise the data field of 512 bytes in the nand flash memory page or leaf, therefore, according to said method, can generate first check code of 3 bytes according to the data of preceding 256 bytes that write to the nand flash memory page or leaf, the data that write to back 256 bytes of nand flash memory page or leaf generate first check code of 3 bytes, therefore, can obtain first check code of two 3 bytes, first check code of these two 3 bytes is stored to the OOB district of nand flash memory page or leaf according to all data that write to the nand flash memory page or leaf.As the 0th, 1,2 and the 3rd, 6,7 bytes in the OOB district of nand flash memory page or leaf being used to store first check code.
In step S102, when reading of data from the nand flash memory page or leaf, the data of per 256 bytes of reading are carried out row verification and row verification respectively from nand flash memory, generate second check code, this second check code comprises the secondary series check code and the second row check code.
Wherein the detailed process that the data of per 256 bytes of reading from nand flash memory are carried out the capable verification of row check code does not respectively repeat them here with that the data of per 256 bytes of writing are carried out the capable verification of row check code respectively is identical.
In step S103, first check code and the second check code step-by-step are carried out the XOR processing, and judge according to the XOR result whether the data in the nand flash memory make mistakes.Its concrete steps are as follows:
Carry out after XOR handles when first check code and the second check code step-by-step, the XOR result is 0, judges that then there is not mistake in nand flash memory, the mistake that can't detect perhaps occurred; Carry out after XOR handles when first check code and the second check code step-by-step, having 11 bits in the XOR result is 1, judges to have a bit mistake, and can correct; Carry out after XOR handles when first check code and the second check code step-by-step, only having 1 bit in the XOR result is 1, judges that the OOB district makes mistakes; Other situations are all judged and the mistake that can't correct occurred.
In embodiments of the present invention, carry out verification by realize the data in the nand flash memory according to the software of said method flow performing, when making the image file of nand flash memory, by increase this data check software for data according to the said method flow performing, can realize verification to the data of nand flash memory, this method of calibration is owing to realize by software, thereby and platform independence, make it applicable to any platform.
Fig. 4 shows the structure of the calibration equipment of data in the nand flash memory that the embodiment of the invention provides, and for convenience of explanation, only shows the part relevant with the embodiment of the invention.This device can be to be built in the unit that software unit, hardware cell or software and hardware in the nand flash memory combine, and perhaps is integrated in the nand flash memory as suspension member independently.Wherein:
The first check code generation unit 1 carries out the capable verification of row check code respectively to the data of per 256 bytes of writing when writing data in the nand flash memory page or leaf, generate first check code, and this first check code comprises the first row check code and the first row check code.This first check code generation unit 1 comprises the first row verification module 11 and the first row verification module 12.Wherein:
The data ordering of per 256 bytes that the first row verification module 11 will write becomes the matrix of 256 row and 8 row, and adopt default row verification rule that the bit in the matrix is carried out the row verification, generate corresponding row polar code, the row polar code that generates is combined into the first row check code.Wherein each element is represented a bit in 256 bytes in the matrix.Default row verification rule does not repeat them here as mentioned above.
The data ordering of per 256 bytes that the first row verification module 12 will write becomes the matrix of 256 row and 8 row, adopt default capable verification rule to the capable verification of the bit in the matrix, generate corresponding capable polar code, all row polar codes that generate are combined into the first row check code.Wherein each element is represented a bit in 256 bytes in the matrix.Default capable verification rule does not repeat them here as mentioned above.
The second check code generation unit 2 is when reading of data from the nand flash memory page or leaf, data to per 256 bytes of reading from nand flash memory are carried out the capable verification of row check code respectively, generate second check code, this second check code comprises the secondary series check code and the second row check code.This second check code generation unit 2 comprises the secondary series verification module 21 and the second row verification module 22.Wherein:
The data ordering of per 256 bytes that secondary series verification module 21 will read becomes the matrix of 256 row and 8 row, and adopts default row verification rule that the bit in the matrix is carried out the row verification, generates the secondary series check code.Wherein each element is represented a bit in 256 bytes in the matrix.Default row verification rule does not repeat them here as mentioned above.
The data ordering of per 256 bytes that the second row verification module 22 will read becomes the matrix of 256 row and 8 row, adopts default capable verification rule to the capable verification of the bit in the matrix, generates the second row check code.Wherein each element is represented a bit in 256 bytes in the matrix.Default capable verification rule does not repeat them here as mentioned above.
Data check unit 3 carries out the XOR processing with first check code of first check code generation unit generation and the second check code step-by-step of second check code generation, and judges according to the XOR result whether the data in the nand flash memory make mistakes.Its concrete steps do not repeat them here as mentioned above.
One of ordinary skill in the art will appreciate that all or part of flow process that realizes in the foregoing description method, be to instruct relevant hardware to finish by computer program, described program can be stored in the computer read/write memory medium, this program can comprise the flow process as the embodiment of above-mentioned each side method when carrying out.Wherein, described storage medium can be magnetic disc, CD, read-only storage memory body (Read-Only Memory, ROM) or at random store memory body (Random Access Memory, RAM) etc.
In embodiments of the present invention, carry out verification by realize the data in the nand flash memory according to the software of said method flow performing, when making the image file of nand flash memory, by increase this data check software for data according to the said method flow performing, can realize verification to the data of nand flash memory, this method of calibration is owing to realize by software, thereby and platform independence, make it applicable to any platform.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. the method for calibration of data in the nand flash memory is characterized in that described method comprises the steps:
When in the nand flash memory page or leaf, writing data, the data of per 256 bytes of writing are carried out row verification and row verification respectively, generate first check code, described first check code comprises the first row check code and the first row check code;
When reading of data from the nand flash memory page or leaf, the data of per 256 bytes of reading from nand flash memory are carried out row verification and row verification respectively, generate second check code, described second check code comprises the secondary series check code and the second row check code;
First check code and the second check code step-by-step are carried out the XOR processing, and judge according to the XOR result whether the data in the nand flash memory make mistakes.
2. the method for claim 1 is characterized in that, the step of the data of per 256 bytes of writing being carried out the row verification is specially:
The data ordering of per 256 bytes of writing is become 256 row and 8 matrixes that are listed as, and each element is represented a bit in 256 bytes in the matrix;
Adopt default row verification rule that the bit in the matrix is carried out the row verification, generate corresponding row polar code;
All row polar codes that generate are combined into the first row check code.
3. method as claimed in claim 2 is characterized in that, described default row verification rule is:
XOR in the matrix is handled the bit of 1 row and skipped 1 bit that is listed as again, circulation is carried out, and all row all dispose in matrix, generate corresponding row polar code;
To behind the bit of skipping 1 row in the matrix again XOR handle the bit of 1 row, circulation is carried out, all row all dispose in matrix, generate the row polar code of correspondence;
XOR in the matrix is handled the bit of 2 row and skipped 2 bits that are listed as again, circulation is carried out, and all row all dispose in matrix, generate corresponding row polar code;
To skipping 2 bits that the are listed as bits of XOR processing 2 row again in the matrix, circulation is carried out, and all row all dispose in matrix, generate corresponding row polar code;
XOR in the matrix is handled the bit of 4 row and skipped 4 bits that are listed as again, circulation is carried out, and all row all dispose in matrix, generate corresponding row polar code;
To skipping 4 bits that the are listed as bits of XOR processing 4 row again in the matrix, circulation is carried out, and all row all dispose in matrix, generate corresponding row polar code.
4. the method for claim 1 is characterized in that, the data of per 256 bytes of writing is gone the step of verification be specially:
The data ordering of per 256 bytes of writing is become 256 row and 8 matrixes that are listed as, and each element is represented a bit in 256 bytes in the matrix;
Adopt default capable verification rule to the capable verification of the bit in the matrix, generate corresponding capable polar code;
All row polar codes that generate are combined into the first row check code.
5. method as claimed in claim 4 is characterized in that, described default capable verification rule is:
XOR in the matrix is handled the bit of 1 row and skipped 1 bit of going again, circulation is carried out, and all row all dispose in matrix, generate corresponding capable polar code;
To behind the bit of skipping 1 row in the matrix again XOR handle the bit of 1 row, circulation is carried out, all row all dispose in matrix, generate corresponding capable polar code;
XOR in the matrix is handled the bit of 2 row and skipped 2 bits of going again, circulation is carried out, and all row all dispose in matrix, generate corresponding capable polar code;
To skipping 2 bits of the going bits of XOR processing 2 row again in the matrix, circulation is carried out, and all row all dispose in matrix, generate the row polar code of correspondence;
XOR in the matrix is handled the bit of 4 row and skipped 4 bits of going again, circulation is carried out, and all row all dispose in matrix, generate corresponding capable polar code;
To skipping 4 bits of the going bits of XOR processing 4 row again in the matrix, circulation is carried out, and all row all dispose in matrix, generate the capable polar code of correspondence;
XOR in the matrix is handled the bit of 8 row and skipped 8 bits of going again, circulation is carried out, and all row all dispose in matrix, generate corresponding capable polar code;
To behind the bits of skipping 8 row in the matrix again XOR handle the bits of 8 row, circulation is carried out, all row all dispose in matrix, generate corresponding capable polar code;
XOR in the matrix is handled the bit of 16 row and skipped 16 bits of going again, circulation is carried out, and all row all dispose in matrix, generate corresponding capable polar code;
To skipping 16 bits of the going bits of XOR processing 16 row again in the matrix, circulation is carried out, and all row all dispose in matrix, generate the row polar code of correspondence;
XOR in the matrix is handled the bit of 32 row and skipped 32 bits of going again, circulation is carried out, and all row all dispose in matrix, generate corresponding capable polar code;
To skipping 32 bits of the going bits of XOR processing 32 row again in the matrix, circulation is carried out, and all row all dispose in matrix, generate the capable polar code of correspondence;
XOR in the matrix is handled the bit of 64 row and skipped 64 bits of going again, circulation is carried out, and all row all dispose in matrix, generate corresponding capable polar code;
To skipping 64 bits of the going bits of XOR processing 64 row again in the matrix, circulation is carried out, and all row all dispose in matrix, generate the row polar code of correspondence;
XOR in the matrix is handled the bit of 128 row and skipped 128 bits of going again, circulation is carried out, and all row all dispose in matrix, generate corresponding capable polar code;
To skipping 128 bits of the going bits of XOR processing 128 row again in the matrix, circulation is carried out, and all row all dispose in matrix, generate the capable polar code of correspondence.
6. as each described method of claim 1-5, it is characterized in that, describedly XOR is carried out in first check code and the second check code step-by-step handle, and judge that according to the XOR result step whether data in the nand flash memory make mistakes is specially:
Carry out after XOR handles when first check code and the second check code step-by-step, the XOR result is 0, judges that there is not mistake in nand flash memory, the mistake that can't detect perhaps occurred;
Carry out after XOR handles when first check code and the second check code step-by-step, having 11 bits in the XOR result is 1, judges to have a bit mistake, and can correct;
Carry out after XOR handles when first check code and the second check code step-by-step, only having 1 bit in the XOR result is 1, judges that the OOB district makes mistakes;
When first check code and the second check code step-by-step are carried out after XOR handles, the XOR result is all judged for other situations and the mistake that can't correct occurred.
7. the calibration equipment of data in the nand flash memory is characterized in that described device comprises:
The first check code generation unit is used for when the nand flash memory page or leaf writes data, and the data of per 256 bytes of writing are carried out row verification and row verification respectively, generates first check code, and described first check code comprises the first row check code and the first row check code;
The second check code generation unit, be used for the time from nand flash memory page or leaf reading of data, the data of per 256 bytes of reading from nand flash memory are carried out row verification and row verification respectively, generate second check code, described second check code comprises the secondary series check code and the second row check code;
The data check unit is used for first check code and the second check code step-by-step are carried out the XOR processing, and judges according to the XOR result whether the data in the nand flash memory make mistakes.
8. device as claimed in claim 7 is characterized in that, the described first check code generation unit comprises:
The first row verification module, the data ordering that is used for per 256 bytes that will write becomes 256 row and 8 matrixes that are listed as, and adopt default row verification rule that the bit in the matrix is carried out the row verification, and generate corresponding row polar code, all row polar codes that generate are combined into the first row check code;
The first row verification module, the data ordering that is used for per 256 bytes that will write becomes 256 row and 8 matrixes that are listed as, and adopt default capable verification rule to the capable verification of the bit in the matrix, and generate corresponding capable polar code, all row polar codes that generate are combined into the first row check code.
9. a nand flash memory is characterized in that, described flash memory comprises the calibration equipment of data in described claim 7 or the 8 described nand flash memories.
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