CN105183579B - A kind of data verification method and device, electronic equipment - Google Patents

Abstract

The invention discloses a kind of data verification method and devices, electronic equipment, which comprises obtains 256 data；Obtain 13 first verifications relevant to the data of acquisition and data generated according to the first checksum algorithm；The data of the acquisition are verified and calculated according to first checksum algorithm, generate 13 second verifications and data；First verification and data and second verification and data are compared, comparison result is obtained；The correctness of 256 data obtained is determined according to the comparison result.

Description

A kind of data verification method and device, electronic equipment

Technical field

The present invention relates to data check technology more particularly to a kind of data verification methods and device, electronic equipment.

Background technique

Memory (Memory) is one of the ost important components in electronic equipment, it is and the central processing unit in electronic equipment (CPU) bridge linked up.The effect of memory is external for temporarily storing the operational data in CPU, and with hard disk etc. The data of memory transactions.In operation, CPU will be transferred to the data for needing operation in memory and carry out operation electronic equipment, Result is sent out memory again by CPU after the completion of operation, and the operation of memory also determines the stable operation of computer.

Memory is a kind of electronic device, inevitably will appear mistake in the work course, and high for stability requirement For user, EMS memory error may cause fatefulue problem.EMS memory error can also be divided into hard error and soft according to its reason Mistake.Hardware error is as caused by the damage or defect of hardware, and data are always incorrect, and such mistake is can not to entangle Positive；Soft error occurs at random, such as near memory occurs the factors such as electronic interferences suddenly all and may cause memory and is soft The generation of mistake.

In order to detect with the soft error in correcting memory, to the verification of data in EMS memory, there are commonly even-odd checks (Parity), cyclic redundancy check code (Cyclic Redundancy Check, CRC) verification, error checking and correction (Error Checking and Correcting, ECC) verification etc. modes.Parity check system and ECC check are introduced below Mode.

The smallest unit is bit in memory, also referred to as " position (Bit) ", and position has only two states to carry out table respectively with 1 and 0 Show, every 8 continuous bits are called a byte (Byte).The each byte of the memory of tape parity check does not only have 8, if its A certain position stores the value of mistake, and the corresponding data that will lead to its storage changes, and then it is wrong to cause application program to occur Accidentally.Memory with parity function is known as Parity memory, and in Parity memory, even-odd check is exactly in each byte One is increased except (8) again as error detection bits.In certain byte after storing data, stored on its 8 positions Data are fixed, because position can only be there are two types of state 1 or 0, it is assumed that the data bit of storage is expressed as 1,1,1,0,0,1,0,1, So each addition (1+1+1+0+0+1+0+1=5), the result is that odd number.For even parity check, check bit is just defined as 1, instead Then be 0；For odd, then on the contrary.When CPU reads the data of storage, it can be again the data phase stored in first 8 Add, whether calculated result is consistent with check bit.To detect EMS memory error to a certain extent, even-odd check can only be detected Make mistake and it can not be modified, although while dibit simultaneously occur mistake probability it is at a fairly low, even-odd check can not Detect double bit error.

Known by analysis above, Parity memory is by increasing a data bit on the basis of original data bit Check the correctness of current 8 data, but as the data bit that the increase Parity of data bit is used to examine also is multiplied, That is it needs to increase by 2 for checking when data bit is 16, then need to increase by 4 when data bit is 32, according to this Analogize.Especially when data volume is very big, the probability of corrupt data is also bigger, for that can only correct the odd even of easy bugs The method of inspection just seems unable to do what one wishes, is based under such a case and ECC check occurs, ECC check be also Additional check bit is realized in data bit originally.The difference is that the increased method of the two is different, this also has led to two The major function of person is not quite alike.ECC check, if data bit is 8, needs to increase by 5 unlike Parity verification ECC error inspection and correction are carried out, data bit often doubles, ECC only increases by a bit trial position, that is to say, that works as data bit When being 16 ECC when being 6,32 ECC be 7, ECC are 8 when data bit is 64, and so on, data bit It often doubles, ECC only increase by one.In short, ECC can allow mistake in memory, and can by error correction, make be System is able to continue normally to operate, not reason mistake and interrupt, and ECC has the ability corrected automatically, can by Parity without Method checks that the error bit come is found and by error correction.

From the above, it can be seen that the digit of ECC check is directly related with the digit of the data bit in memory, current In the electronic equipment of mainstream, (i.e. with the memory of ECC check function, memory is dual inline memory module to ECC memory The digit of data bit is 64 in (Dual-Inline-Memory-Modules, DIMM), then the check bit of ECC is 8, such as Fruit uses 8 chip (Chip) Lai Shixian ECC memory, then (64+8) ÷ (8)=9 chip is at least needed, this 9 chips In 8 chips position for storing data, remaining 1 chip in this 9 chips is for storing ECC.Number in ECC memory Digit according to position is 32, then ECC are 7, if using 8 chips (Chip, also known as monolithic device, monolithic devices Part can use or x8 dynamic random access memory DRAM is realized) Lai Shixian ECC memory, then at least need (32+7) ÷ (8)=5 chip, 4 chips in this 5 chips position for storing data, remaining 1 chip in this 5 chips For storing ECC.In order to improve the operation efficiency of electronic equipment, in general, the data bit of ECC memory is relatively common at present 64.

When the data bit of ECC memory is 64, the digit of each chip is 8 in memory, then electronic equipment needs 9 Chip, when carrying out ECC check for this case in the prior art, checking algorithm is typically designed to the data bit of every reading 512 Carry out an ECC data verification.When ECC check algorithm is designed as 512 data bit of verification, then for storing when ECC check The digit of check bit is then 64.There was only a root memory DIMM in electronic equipment, and DIMM is capable of providing 64 data In the case where channel, then electronic equipment needs to carry out DIMM 8 read-writes, i.e. electronic equipment needs 8 burst read-write cycles, 512 data can be written, and then complete an ECC check.There was only two root memory DIMM, and each DIMM in electronic equipment In the case where being capable of providing 64 data channel, then electronic equipment needs to carry out DIMM 4 read-writes, could be written 512 Data, and then complete an ECC check.

But present inventor during inventive technique scheme, has found above-mentioned technology extremely in realizing the embodiment of the present application It has the following technical problems less: when electronic equipment only has the digit of each chip in a root memory DIMM and memory to be 8, 512 data are needed due to carrying out an ECC data verification, then need to carry out DIMM 8 read-writes, it is seen then that in the prior art In the presence of the time longer technical problem for completing the verification of an ECC data.

Summary of the invention

In view of this, the embodiment of the present invention provides a kind of data verification method to solve problems of the prior art And device, electronic equipment, it can be avoided the time longer disadvantage for completing the verification of an ECC data in the prior art, to mention Rise user experience.

The technical solution of the embodiment of the present invention is achieved in that

In a first aspect, the embodiment of the present invention provides a kind of data verification method, comprising:

Obtain 256 data；

Obtain 13 first verifications relevant to the data of acquisition and data generated according to the first checksum algorithm；

The data of the acquisition are verified and calculated according to first checksum algorithm, generate 13 second verifications And data；

First verification and data and second verification and data are compared, comparison result is obtained；

The correctness of 256 data obtained is determined according to the comparison result.

Second aspect, the embodiment of the present invention provide a kind of electronic equipment, comprising:

Verification and data generating unit, for obtaining 256 data；Obtain generated according to the first checksum algorithm with obtain Relevant 13 first verifications of the data taken and data；School is carried out according to data of first checksum algorithm to the acquisition It tests and calculates, generate 13 second verifications and data；First verification and data and second verification and data are carried out Compare, obtains comparison result；The correctness of 256 data obtained is determined according to the comparison result

Data storage cell, for storing 256 data obtained；

Verification and data storage cell, for storing the data with acquisition generated according to the first checksum algorithm obtained Relevant 13 first verifications and data.

The third aspect, the embodiment of the present invention provide a kind of data calibration device, which includes first acquisition unit, second Acquiring unit, generation unit, comparing unit and determination unit, in which:

The first acquisition unit, for obtaining 256 data；

The second acquisition unit, for obtaining generate according to the first checksum algorithm relevant to the data of acquisition 13 The first verification of position and data；

The generation unit, by the data of the acquisition are verified according to first checksum algorithm and based on It calculates, generates 13 second verifications and data；

The comparing unit is obtained for being compared first verification and data and second verification and data Obtain comparison result；

The determination unit, for determining the correctness of 256 data obtained according to the comparison result.

Data verification method and device provided in an embodiment of the present invention, electronic equipment, wherein obtain 256 data；It obtains 13 first verifications relevant to the data of acquisition and data generated according to the first checksum algorithm；According to first verification It is verified and is calculated with data of the algorithm to the acquisition, generate 13 second verifications and data；By it is described first verification and Data and second verification and data are compared, and obtain comparison result；It is determined according to the comparison result described in obtaining The correctness of 256 data so, it is possible to avoid the time longer disadvantage for completing the verification of an ECC data in the prior art, To promote user experience.

Detailed description of the invention

Fig. 1 is the flow chart of the data verification method in the embodiment of the present invention；

Fig. 2 is the configuration schematic diagram of the storage unit in the embodiment of the present invention；

Fig. 3 is the structural schematic diagram of the electronic equipment in the embodiment of the present invention；

Fig. 4 is that verification indicates to be intended to one in the embodiment of the present invention；

Fig. 5 is that verification indicates to be intended to two in the embodiment of the present invention；

Fig. 6 is that verification indicates to be intended to three in the embodiment of the present invention；

Fig. 7 is that verification indicates to be intended to four in the embodiment of the present invention；

Fig. 8 is the composed structure schematic diagram of data calibration device in the embodiment of the present invention.

Specific embodiment

The embodiment of the present invention provides a kind of data verification method and electronic equipment, just carries out one by reading 256 data Secondary ECC check solves the time longer technical problem of completion existing in the prior art ECC data verification, realizes Shorten the technical effect for completing the time of ECC data verification.

Technical solution in the embodiment of the present invention in order to solve the above technical problems, provides a kind of data verification method, packet It includes:

Obtain 256 data, and 13 the first schools relevant to the data of acquisition generated according to the first checksum algorithm It tests and data；

The data of the acquisition are verified and calculated according to first checksum algorithm, generate 13 second verifications And data；

First verification and data and second verification and data are compared, comparison result is obtained；

The correctness of 256 data obtained is determined according to the comparison result.

From above scheme as can be seen that in the scheme of the embodiment of the present application, gets 256 data and just carry out an ECC Data check, compared to the prior art in need to get 512 data, for just carrying out the verification of ECC data, can contract The short time for completing the verification of an ECC data.

In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.

Embodiment one

The embodiment of the present invention provides a kind of data verification method, is applied to electronic equipment, which is realized Function can be realized by hardware mode, can also be realized by the processor caller code in electronic equipment, Certain program code can be stored in computer storage medium, it is seen then that the electronic equipment includes at least processor and storage is situated between Matter.

Fig. 1 is the implementation process schematic diagram of one data verification method of the embodiment of the present invention, as shown in Figure 1, the data check Method includes:

Step S101 obtains 256 data；

Step S102, obtain according to the first checksum algorithm generates it is relevant to the data of acquisition 13 first verify and Data；

Step S103 is verified and is calculated to the data of the acquisition according to first checksum algorithm, generates 13 The second verification of position and data；

First verification and data and second verification and data are compared by step S104, and knot is compared in acquisition Fruit；

Step S105 determines the correctness of 256 data obtained according to the comparison result.

Here, the step S105 determines the correctness of 256 data obtained, packet according to the comparison result It includes:

When the comparison result shows first verification and data and second verification and data difference, determination is obtained There are the data that mistake occurs in 256 data taken；When the comparison result show it is described first verification and data with it is described When second verification is identical with data, determine that there is no the data that mistake occurs in 256 data obtained.

In electronic equipment in the embodiment of the present application, the chip that memory uses is x8 dynamic random access memory DRAM (Dynamic Random Access Memory), wherein x8 indicates 8, then in the embodiment of the present application, is made up of x8 DRAM 256 data storage positions need 32 x8 DRAM.

Embodiment two

Based on embodiment one above-mentioned, the embodiment of the present invention by embodiment one step S101 and step S102 carry out Illustrate, at least there are two types of implementations during specific implementation.Specifically, the data check side in the embodiment of the present application Method can be used as the data check in data write-in and reading process, can also be used as the data check in data transmission procedure, Then step S101 includes at least following two situation.

The first situation carries out data check to the data read from data storage cell, then the step S101, is obtained Take 256 data, comprising: by the storage region of the data storage cell of 256 data write-in electronic equipment, and will be from described 256 data read out in storage region are as the data obtained；

Accordingly, step S102 obtains generate according to the first checksum algorithm 13 relevant to the data of acquisition the One verification and data, comprising: verified and calculated according to 256 data of first checksum algorithm to write-in, generated 13 first verifications and data；By the memory block of 13 first verifications and the data storage cell of data write-in electronic equipment In domain, and using 13 data read out from the storage region as the data obtained.

Specifically, firstly, the processor of electronic equipment is by the data storage cell of 256 data write-in electronic equipment In storage region.In the embodiment of the present application, data storage cell is 32 monolithic devices, i.e. 32 x8 DRAM, wherein each Monolithic device includes 8 bits, therefore, constitutes 256 data storages and needs 32 monolithic devices.Then, according to the first school It tests and is verified and calculated with 256 data of the algorithm to write-in, generate 13 first verifications and data；And it will be from described 256 data read out in storage region are as the data obtained.

Second situation carries out error detection to the data in data transmission procedure.The then step S101 obtains 256 Position data, comprising: receive 256 data and 13 first verifications and data that another electronic equipment is sent, wherein described 13 first verifications and data are that another electronic equipment sets needs to the electronics according to first checksum algorithm 256 data that preparation is sent are verified and are calculated, the verification and data of generation.

Specifically, another electronic equipment can be another computer, then 256 data obtained and 13 are the first school of position Test the data sent with data for the computer.

Next, the configuration of the storage unit to the embodiment of the present application for storing data is illustrated.As shown in Fig. 2, For the configuration schematic diagram of storage unit in the embodiment of the present application.

In the prior art, when electronic equipment only includes a root memory DIMM, and DIMM is capable of providing 64 data In the case where channel, then electronic equipment needs to carry out DIMM 8 read-writes, i.e. electronic equipment needs 8 burst read-write cycles, 512 data can be written, and then complete an ECC check.There was only two root memory DIMM, and each DIMM in electronic equipment In the case where being capable of providing 64 data channel, then electronic equipment needs to carry out DIMM 4 read-writes, could be written 512 Data, and then complete an ECC check.

In the embodiment of the present application, data storage cell includes 32 monolithic devices, and respectively Dev0 to Dev31 is specific next It says, 256 data is constituted by x8 DRAM and store position 32 x8 DRAM of needs, i.e. 32 monolithic devices, each monolithic device In include 8 bits, respectively b0 to b7.When electronic equipment only includes a root memory DIMM, and DIMM is capable of providing In the case where 64 data channel, then electronic equipment needs to carry out DIMM 4 read-writes, i.e. electronic equipment needs 4 bursts Read-write cycle can be written 256 data, and then complete an ECC check.There was only two root memory DIMM in electronic equipment, And in the case that each DIMM is capable of providing 64 data channel, then electronic equipment needs to carry out DIMM 2 read-writes, just 256 data can be written.From the above, it can be seen that an either root memory item or two memory bars, completed in the present embodiment ECC check, compared with prior art, speed is doubled.

It should be noted that Dev0 to the Dev31 in Fig. 2 is after repeatedly reading and writing as a result, for example when electronic equipment only wraps Include a root memory DIMM, and in the case that DIMM is capable of providing 64 data channel, then electronic equipment is needed to DIMM 4 read-writes are carried out, Dev0 to Dev31 can be just obtained.There was only two root memory DIMM in electronic equipment, and each DIMM can In the case where providing 64 data channel, then electronic equipment needs to carry out DIMM 2 read-writes, can just obtain Dev0 and arrive Dev31。

Further, verification and data storage cell include 4 monolithic devices, respectively Check0, Check1, Spare0 and The verification and data that Spare1, verification and data storage cell generate in checking procedure for storing data.Each monolithic device In include 8 bits, respectively b0 to b7.

In the prior art, it reads 512bits and just carries out an ECC check, in the embodiment of the present application, reading 256bits is just Carry out an ECC check, in the embodiment of the present application, two DIMM memory bars are can be used in the DIMM memory bar of use, and DIMM is mentioned 64 data channel are supplied.An ECC check is just carried out due to only needing to read 256 data in the embodiment of the present application, That is every 1/2 cache lines (being directed to 512 bit cache rows) carry out an ECC check.And in the prior art, it needs to read 512 data just carry out an ECC check, that is to say, that each cache lines (being directed to 512 bit cache rows) just carry out primary ECC check.

In the embodiment of the present application, Memory Controller Hub can have multiple operating modes, by taking the memory processor of Intel as an example, Under precise synchronization mode and autonomous channel mode, the period for carrying out an ECC check is different.For 256 data, Under precise synchronization mode (LockStep Channel Mode), data are read simultaneously by two DIMM, it is only necessary to 2 bursts Read-write cycle (burst) is read at autonomous channel mode (Independent Channel Mode) by a DIMM simultaneously Access evidence, it is only necessary to 4 burst read-write cycles.And in the prior art, for 512 data, under precise synchronization mode, pass through Two DIMM read data simultaneously, need 4 burst read-write cycles, under the mode of autonomous channel, read simultaneously by a DIMM Access evidence, needs 8 burst read-write cycles.As it can be seen that compared to existing technologies, utilization is less in the embodiment of the present application Time can complete an ECC check.

Further, in the embodiment of the present application, under precise synchronization mode, the monolithic device of 32 x8 in two DIMM is needed Storing data then includes the DIMM of 18 monolithic devices for two, wherein 16 monolithic devices are as data bit, it is 2 remaining Monolithic device is used as ECC check.Under the mode of autonomous channel, a DIMM is needed to carry out twi-read, and will be therein 16bits is used as ECC check.

In the embodiment of the present application, 32 monolithic devices can not be practical monolithic device, if using a DIMM, and There was only 8+1 monolithic device on DIMM, needs to read 4 data that could obtain 256bits, then practical monolithic device only has 8 A, in this case, 32 monolithic devices are not practical monolithic devices.If using two DIMM, and having 16+2 on DIMM A monolithic device then only needs to read 2 data that can obtain 256bits, and in this case, 32 monolithic devices are also It is not practical monolithic device.

In the embodiment of the present application, for 256 data, 13 bit checks and data only can be generated, therefore, are used as ECC check 4 monolithic devices in, remaining 19bits may be used as standby functions.Although precise synchronization mode and autonomous channel mode There will be 19bits remaining, still, autonomous channel mode needs 32bits just to may be used as standby functions, therefore, independently logical Under road mode, the 19bits can not be utilized, and precise synchronization mode, 16bits can serve as standby functions and carry out using then When there is monolithic device damage, the 16bits in remaining 19bits can substitute the function of the monolithic device to break down.

Also, for autonomous channel mode, in the case where reading 4 times, the data of Check 0 and Check1 can be stored in On same physics monolithic device, but data will not cover mutually, but carry out interleaved.

Implement three

Based on embodiment above-mentioned, checksum algorithm in embodiment one will be described in detail in the embodiment of the present invention.Tool For body, verification and the following formula of formula (1-1) to (1-13):

Check0b0=checksum { Dev 0~31bit 0and x }； (1-1)；

Check0b1=checksum { Dev 0~31bit y and z }； (1-2)；

Check0b2=checksum { Dev 0~31bit p and q }； (1-3)；

Check0b3=checksum { Dev 0~31bit s and t }； (1-4)；

Check0b4=checksum { Dev 0,4,8,12,16,20,24,28all bit }； (1-5)；

Check0b5=checksum { Dev 1,5,9,13,17,21,25,29all bit }； (1-6)；

Check0b6=checksum { Dev 2,6,10,14,18,22,26,30all bit }； (1-7)；

Check0b7=checksum { Dev 3,7,11,15,19,23,27,31all bit }； (1-8)；

Check1b0=checksum { Dev 0,1,2,3all bit 0, y, p and s }； (1-9)；

Check1b1=checksum { Dev 0~31all bit x, z, q and t }； (1-10)；

Check1b2=checksum Dev 8,9,10,11,12,13,14,15,24,25,26,27,28,29,30, 31all bit}； (1-11)；

Check1b3=checksum { Dev 4,5,6,7,12,13,14,15,20,21,22,23,28,29,30,31all bit}； (1-12)；

Check1b4=checksum Dev 16,17,18,19,20,21,22,23,24,25,26,27,28,29,30, 31all bit}； (1-13)；

Wherein, x, y, z, the value of p, q, s and t be more than or equal to 1 be less than or equal to 7 between integer, and x, y, z, p, Q, s and t are not mutually equal two-by-two, and in other words, x, y, z, p, q, s and t have following relationship:

y≠x；

z≠x,z≠y；

p≠x,p≠y,p≠z；

q≠x,q≠y,q≠z,q≠p；

s≠x,s≠y,s≠z,s≠p,s≠q；

t≠x,t≠y,t≠z,t≠p,t≠q,t≠s.

Wherein, Check0b0~b7 indicates the 12nd ratio in verification and storage unit in 13 first verifications and data To the 5th bit, Check1b0~b4 indicates the 4th in 13 first verifications and data in verification and storage unit for special position Bit is to the 0th bit, wherein it includes 13 that the first verification and data, which have altogether, Dev 0~31 is indicated in data storage cell 32 monolithic devices, 0~bit of bit 7 indicate the 0th bit in data storage cell in 32 monolithic devices to the 7th ratio Special position.Checksum is checksum algorithm, in the embodiment of the present application, can using exclusive or XOR or or non-NOR by the way of carry out Verification and calculating, then can generate the data of a bit, that is to say, that the value of Check0b0 is 0 or 1.

It should be noted that verification in the embodiment of the present invention and the digit occupied are 13, this 13 bit check and depositing Two dev are only needed when storage.In the above-described embodiments, be by this 13 verification and be stored in check0 and In check1, wherein check0 is all occupied, and check1 occupies the bit0 to bit4 in 8；In another of the invention In embodiment, it is also possible that check0 is all occupied, and the bit1 to bit5 in 8 of occupancy check1, or Check1 is fully occupied and occupies in check0 5 in 8.It will be understood by those of skill in the art that this 13 Verification is stored with two memory storage chips are only needed, and specifically uses check0 and check1, or use Check1 and check2 etc., can be depending on the concrete condition of electronic equipment, and the present embodiment does not do any restriction.

Likewise, Check0b1~b7 to Check1b0~b4 is also carried out using checksum algorithm identical with Check0b0 Verification and calculating.Wherein, Check0b0 to Check0b7 be 64 data verification and, Check1b0 be 16 data verification With the verification that, Check1b1 to Check1b4 is 128 data and.

Assignment is carried out to x, y, z, p, q, s and t below, so that it may obtain a specific verification and formula, such as work as x= 4, when y=1, z=5, p=2, q=6, s=3 and t=7, according to verification and formula (1-1) to (1-13) obtain as follows verify and Formula (2-1) to (2-13):

Check0b0=checksum { 0~31bit0and of Dev 4 }； (2-1)；

Check0b1=checksum { 0~31bit1and of Dev 5 }； (2-2)；

Check0b2=checksum { 0~31bit2and of Dev 6 }； (2-3)；

Check0b3=checksum { 0~31bit3and of Dev 7 }； (2-4)；

Check0b4=checksum { Dev 0,4,8,12,16,20,24,28all bit 0~7 }； (2-5)；

Check0b5=checksum { Dev 1,5,9,13,17,21,25,29all bit 0~7 }； (2-6)；

Check0b6=checksum { Dev 2,6,10,14,18,22,26,30all bit 0~7 }； (2-7)；

Check0b7=checksum { Dev 3,7,11,15,19,23,27,31all bit 0~7 }； (2-8)；

Check1b0=checksum { Dev 0,1,2,3all bit 0~3 }； (2-9)；

Check1b1=checksum { bit4~7 0~31all of Dev }； (2-10)；

Check1b2=checksum Dev 8,9,10,11,12,13,14,15,24,25,26,27,28,29,30, 31all bit 0~7 }； (2-11)；

Check1b3=checksum { Dev 4,5,6,7,12,13,14,15,20,21,22,23,28,29,30,31all Bit 0~7 }； (2-12)；

Check1b4=checksum Dev 16,17,18,19,20,21,22,23,24,25,26,27,28,29,30, 31all bit 0~7 }； (2-13).

Specifically, using the checksum algorithm in the embodiment of the present application, according to 256bits, can generate 13 bit checks and Data are respectively stored in Check0 to Check1, then remaining two monolithic devices Spare0 and Spare1 can be used as standby Monolithic device, when there is monolithic device damage, Spare0 and Spare1 can substitute the function of the monolithic device to break down.

Next, read data instance from memory with processor, to the data verification method in the embodiment of the present application into Row explanation, memory here, i.e. data storage cell in above-described embodiment.

As shown in figure 3, while processor 10 writes data into data storage cell 20, send the data to verification and Data generating unit 30, verification and data generating unit 30 based on the received data generate verification and data (i.e. first verification and Data), and these verifications and data write-in are verified and data storage cell 40, wherein 50 be data storage cell 20 and school The data transmission bus between data generating unit 30 is tested, 60 generate for verification and data storage cell 40 and verification and data Data transmission bus between unit 30.

When processor 10 reads data from data storage cell 20, the data of reading can be sent to verification and data are raw Verification and data (the i.e. second verification and data) are regenerated at unit 30, and according to the data of reading, then will be regenerated Verification (i.e. second verification and data) and data with verify and data storage cell 40 in the verification that stores and data ((i.e. the One verification and data)) it is compared, if verification twice is identical with data, directly by the number in data storage cell 20 According to processor 10 is sent to, if verification and data difference twice, verification and data generating unit 30 can store data Data in unit 20 are corrected, and the data after correction are sent to processor 10.

In above-described embodiment, the checksum algorithm for generating verification and data is illustrated, specifically, is write to memory When entering data and reading data from memory, the checksum algorithm of use is identical.Next, to the verification that generates twice and The comparison of data is illustrated.

It specifically, will be in 13 second verifications that generated when reading data and data and verification and data storage cell 40 13 first verification and data compare one by one according to check bit, obtain comparison result, i.e. 13 bit-errors check code (such as Fig. 4 It is shown), it should be noted that table shown in Fig. 4 is realized based on formula (2-1) to (2-13).

Wherein, when first verification and data are with second verification and identical data, the comparison result is to be all 0 Or it is all 1, when first verification and data are with second verification and data difference, the comparison result is 13 bit-errors schools Test coding.

Specifically, any a data when to verification and data are compared twice, in Dev 0 to Dev 31 When mistake occurs, corresponding error checking coding is as shown in the table in Fig. 4.Table in Fig. 4 is the knot obtained with the algorithm of XOR Fruit, if can obtain antipodal content with NOR algorithm, i.e. 1 in table becomes 0,0 and becomes 1.

As seen in Figure 4, when mistake occurs for each data in Dev 0 to Dev 31, there is unique ECC wrong Therefore accidentally check code during data check, is compiled according to the 13 bit-errors verification verified twice and data relatively obtain The corresponding relationship of code and each data and error checking coding in Dev 0 to Dev 31, can determine to occur wrong Data bit accidentally, such as: obtained error checking coding Check0- (b0, b1, b2, b3, b4, b5, b6, b7), Check1- (b0, b1, b2, b3, b4) is 1000100010000, it is determined that the data bit for going out in Dev 0 to Dev 31 to occur mistake is Dev 0Bit0, another example is: obtained error checking coding Check0- (b0, b1, b2, b3, b4, b5, b6, b7), Check1- (b0, B1, b2, b3, b4) it is 1000010010000, it is determined that and the data bit for going out in Dev 0 to Dev 31 to occur mistake is Dev 1Bit 0.For another example, error checking coding Check0- (b0, b1, b2, b3, b4, b5, b6, b7) obtained, Check1- (b0, b1, b2, B3, b4) it is 1000001001000, it is determined that and the data bit for going out in Dev 0 to Dev 31 to occur mistake is Dev 2Bit 4.

In the embodiment of the present application, after the data bit for determining to occur mistake, need to correct data.Then, will Data after correction are sent to processor 10.

Next, the checksum algorithm in the embodiment of the present application is further described, above-mentioned verification and formula are removed It outside, can also include following situations.

The first situation, for (Dev0~Dev3), (Dev4~Dev7), (Dev8~Dev11), (Dev12~ Dev15), (Dev16~Dev19), (Dev20~Dev23), (Dev24~Dev27), the grouping of (Dev28~Dev31), every group In any two monolithic device can be exchanged with each other, such as: Dev 0 and Dev 1 are swapped, in another example, by Dev4 and Dev7 is swapped.

Next, swap and be illustrated with Dev 0 and Dev 1, then the school that changes in above-mentioned verification and formula Testing with data is Check1b0 and Check1b1, specific as follows:

Check0b4=checksum { Dev 1,4,8,12,16,20,24,28all bit }； (2-5)；

Check0b5=checksum { Dev 0,5,9,13,17,21,25,29all bit }； (2-6)；

Corresponding, error checking coding can also change, and be that Dev 0 and Dev 1 is carried out as shown in the table in Fig. 5 Error checking coding schedule (i.e. checklist) after exchange, it can be seen that the error checking corresponding with data bit in Dev 1 of Dev 0 Coding is exchanged, and the corresponding error checking coding of the data bit in other monolithic devices will not change.

Second situation, for following grouping Dev (0,4,8,12,16,20,24,28), (1,5,9,13,17,21,25, 29), (2,6,10,14,18,22,26,30), (3,7,11,15,19,23,27,31) are grouped, any two monolithic in every group Device can be exchanged with each other.Such as: Dev 0 and Dev 4 are swapped, in another example, Dev4 and Dev12 are swapped.

Next, Dev 0 and Dev 4 are swapped and are illustrated, then the verification that changes in above-mentioned verification and formula It is Check2b0 and Check2b1 with data, specific as follows:

Check1b0=checksum { Dev 4,1,2,3all bit 0~3 }； (2-9)；

Check1b3=checksum { Dev 0,5,6,7,12,13,14,15,20,21,22,23,28,29,30,31all Bit 0~7 }； (2-12)；

Corresponding, error checking coding can also change, and be that Dev 0 and Dev 4 is carried out as shown in the table in Fig. 6 Checklist after exchange, it can be seen that the error checking coding corresponding with data bit in Dev 4 of Dev 0 is exchanged, and its The corresponding error checking coding of data bit in his monolithic device will not change.

The third situation swaps monolithic device in conjunction with the first situation and second situation.Such as: 0 He of Dev Dev 1 can be swapped, and Dev 0 and Dev 4 are swapped, then can be swapped Dev 1 and Dev4.

Next, Dev 1 and Dev 4 are swapped and are illustrated, then the verification that changes in above-mentioned verification and formula With data be Check0b4, Check0b5, Check1b0 and Check1b3, it is specific as follows:

Check0b4=checksum { Dev 0,1,8,12,16,20,24,28all bit 0~7 }； (2-5)；

Check0b5=checksum { Dev 4,5,9,13,17,21,25,29all bit 0~7 }； (2-6)；

Check1b0=checksum { Dev 0,4,2,3all bit 0~3 }； (2-9)；

Check1b3=checksum { Dev 1,5,6,7,12,13,14,15,20,21,22,23,28,29,30,31all Bit 0~7 }； (2-12)；

Corresponding, error checking coding can also change, and be that Dev 1 and Dev 4 is carried out as shown in the table in Fig. 7 Checklist after exchange, it can be seen that the error checking coding corresponding with data bit in Dev 4 of Dev 1 is exchanged, and its The corresponding error checking coding of data bit in his monolithic device will not change.

Embodiment five

Based on embodiment above-mentioned, the embodiment of the present invention is providing a kind of electronic equipment, as shown in figure 3, including processor 10, data storage cell 20, verification and data generating unit 30 and verification and data storage cell 40, in which:

Data storage cell 20, for storing 256 data obtained；

Verification and data storage cell 40, for storing the number with acquisition generated according to the first checksum algorithm obtained According to relevant 13 first verifications and data；

Verification and data generating unit 30, for carrying out school according to data of first checksum algorithm to the acquisition It tests and calculates, generate 13 second verifications and data；First verification and data and second verification and data are carried out Compare, obtains comparison result；The correctness of 256 data obtained is determined according to the comparison result.

In the embodiment of the present invention, the correctness that 256 data obtained are determined according to the comparison result, packet It includes: when the comparison result shows first verification and data and second verification and data difference, determining acquisition There are the data that mistake occurs in 256 data；When the comparison result shows first verification and data and described second When verifying identical with data, determine that there is no the data that mistake occurs in 256 data obtained.

In the embodiment of the present invention, during specific implementation, the verification and data generating unit 30 can be using interior Memory controller realizes, in general, Memory Controller Hub is set together with processor (CPU) being physically, but It is that in logic, Memory Controller Hub is to separate with processor.

In another embodiment of the invention, the electronic equipment further include: processor 10 is used for 256 data It is written in the storage region of the data storage cell 20 of electronic equipment.

In another embodiment of the invention, the data storage cell 20 is specially 32 monolithic devices, wherein institute Stating monolithic device includes 8 bits；Processor 10 is specifically used for the 256 data data storage cell is written In 32 monolithic devices.

In another embodiment of the invention, the verification and data generating unit 30 are specifically used for: from the verification With obtained in data storage cell 40 it is described 13 first verification and data；By described 13 second verifications and data and described 13 The first verification of position and data compare one by one according to check bit, obtain the comparison result；It is determined and is obtained according to the comparison result 256 data correctness.

Wherein, when first verification and data are with second verification and identical data, the comparison result is to be all 0 Or it is all 1, when first verification and data are with second verification and data difference, the comparison result is 13 bit-errors schools Test coding.

In another embodiment of the invention, the verification and data generating unit 30 are also used to: relatively being tied described Fruit shows that second verification and data and described first verify and when data difference, according to the 13 bit-errors check code, The data bit for determining to occur mistake, and corrects the data of the acquisition, and the data after correction is sent to described Processor.

In another embodiment of the invention, the data storage cell 20 is specially x8 dynamic random access memory DRAM。

By one or more technical solutions in the embodiment of the present application, following one or more technology effects may be implemented Fruit:

In the scheme of the embodiment of the present application, getting 256 data, and generated according to the first checksum algorithm with obtain After relevant 13 first verifications of the data taken and data, carried out according to data of first checksum algorithm to the acquisition Verification and calculating generate 13 second verifications and data；By it is described first verification and data and it is described second verification and data into Row compares, and obtains comparison result, and the correctness of 256 data obtained is determined according to the comparison result；Wherein, if institute It states comparison result and shows that first verification and data are different from second verification and data, then deposited in the data of the acquisition In the data that mistake occurs.As it can be seen that getting 256 data in the scheme of the embodiment of the present application and just carrying out an ECC data school Test, compared to the prior art in need to get 512 data, for just carrying out the verification of ECC data, completion can be shortened The time of ECC data verification.

It should be understood by those skilled in the art that, the embodiment of the present invention can provide as method, system or computer program Product.Therefore, complete hardware embodiment, complete software embodiment or reality combining software and hardware aspects can be used in the present invention Apply the form of example.Moreover, it wherein includes the computer of computer usable program code that the present invention, which can be used in one or more, The computer program implemented in usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.) produces The form of product.

The present invention be referring to according to the method for the embodiment of the present invention, the process of equipment (system) and computer program product Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates, Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or The function of being specified in multiple boxes.

These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one The step of function of being specified in a box or multiple boxes.

Specifically, the corresponding computer program instructions of data verification method in the embodiment of the present application can be stored in CD, hard disk, on the storage mediums such as USB flash disk, when the computer program instructions quilt corresponding with data verification method in storage medium One electronic equipment reads or is performed, and the data verification method includes the following steps:

Obtain 256 data；

Obtain 13 first verifications relevant to the data of acquisition and data generated according to the first checksum algorithm；

The data of the acquisition are verified and calculated according to first checksum algorithm, generate 13 second verifications And data；

First verification and data and second verification and data are compared, comparison result is obtained；

The correctness of 256 data obtained is determined according to the comparison result.

It need to be noted that: the above electronic equipment implements the description of item or storage medium embodiment, with above-mentioned side Method description be it is similar, there is with embodiment of the method identical beneficial effect, therefore do not repeat them here.For electronic equipment of the present invention Undisclosed technical detail in embodiment or storage medium embodiment, those skilled in the art please refer to the method for the present invention implementation Example description and understand, for save length, which is not described herein again.

Embodiment six

Based on embodiment above-mentioned, the embodiment of the present invention is providing a kind of data calibration device, included by the device The units such as one acquiring unit, second acquisition unit, generation unit, comparing unit and determination unit can pass through electronic equipment In Memory Controller Hub realize；Certainly it can also be realized by specific logic circuit；During specific embodiment, processing Device can be central processing unit (CPU), microprocessor (MPU), digital signal processor (DSP) or field programmable gate array (FPGA) etc..

Fig. 8 is the composed structure schematic diagram of six data calibration device of the embodiment of the present invention, as shown in figure 8, the data check Device 800 includes first acquisition unit 801, second acquisition unit 802, generation unit 803, comparing unit 804 and determination unit 805, in which:

The first acquisition unit 801, for obtaining 256 data；

The second acquisition unit 802, for obtaining according to the related to the data of acquisition of the first checksum algorithm generation 13 first verification and data；

The generation unit 803, for according to data of first checksum algorithm to the acquisition carry out verification and It calculates, generates 13 second verifications and data；

The comparing unit 804, for first verification and data and second verification and data to be compared, Obtain comparison result；

The determination unit 805, for determining the correctness of 256 data obtained according to the comparison result.

It need to be noted that: the description of apparatus above embodiment, be with the description of above method embodiment it is similar, With the similar beneficial effect of same embodiment of the method, therefore do not repeat them here.For undisclosed skill in apparatus of the present invention embodiment Art details please refers to the description of embodiment of the present invention method and understands, to save length, therefore repeats no more.

It should be understood that " one embodiment " or " embodiment " that specification is mentioned in the whole text mean it is related with embodiment A particular feature, structure, or characteristic is included at least one embodiment of the present invention.Therefore, occur everywhere in the whole instruction " in one embodiment " or " in one embodiment " not necessarily refer to identical embodiment.In addition, these specific features, knot Structure or characteristic can combine in any suitable manner in one or more embodiments.It should be understood that in various implementations of the invention In example, magnitude of the sequence numbers of the above procedures are not meant that the order of the execution order, the execution sequence Ying Yiqi function of each process It can determine that the implementation process of the embodiments of the invention shall not be constituted with any limitation with internal logic.The embodiments of the present invention Serial number is for illustration only, does not represent the advantages or disadvantages of the embodiments.

It should be noted that, in this document, the terms "include", "comprise" or its any other variant are intended to non-row His property includes, so that the process, method, article or the device that include a series of elements not only include those elements, and And further include other elements that are not explicitly listed, or further include for this process, method, article or device institute it is intrinsic Element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including being somebody's turn to do There is also other identical elements in the process, method of element, article or device.

In several embodiments provided herein, it should be understood that disclosed device and method can pass through it Its mode is realized.Apparatus embodiments described above are merely indicative, for example, the division of the unit, only A kind of logical function partition, there may be another division manner in actual implementation, such as: multiple units or components can combine, or It is desirably integrated into another system, or some features can be ignored or not executed.In addition, shown or discussed each composition portion Mutual coupling or direct-coupling or communication connection is divided to can be through some interfaces, the INDIRECT COUPLING of equipment or unit Or communication connection, it can be electrical, mechanical or other forms.

Above-mentioned unit as illustrated by the separation member, which can be or may not be, to be physically separated, aobvious as unit The component shown can be or may not be physical unit；Both it can be located in one place, and may be distributed over multiple network lists In member；Some or all of units can be selected to achieve the purpose of the solution of this embodiment according to the actual needs.

In addition, each functional unit in various embodiments of the present invention can be fully integrated in one processing unit, it can also To be each unit individually as a unit, can also be integrated in one unit with two or more units；It is above-mentioned Integrated unit both can take the form of hardware realization, can also realize in the form of hardware adds SFU software functional unit.

Those of ordinary skill in the art will appreciate that: realize that all or part of the steps of above method embodiment can pass through The relevant hardware of program instruction is completed, and program above-mentioned can store in computer-readable storage medium, which exists When execution, step including the steps of the foregoing method embodiments is executed；And storage medium above-mentioned includes: movable storage device, read-only deposits The various media that can store program code such as reservoir (Read Only Memory, ROM), magnetic or disk.

If alternatively, the above-mentioned integrated unit of the present invention is realized in the form of software function module and as independent product When selling or using, it also can store in a computer readable storage medium.Based on this understanding, the present invention is implemented Substantially the part that contributes to existing technology can be embodied in the form of software products the technical solution of example in other words, The computer software product is stored in a storage medium, including some instructions are used so that computer equipment (can be with It is personal computer, server or network equipment etc.) execute all or part of each embodiment the method for the present invention. And storage medium above-mentioned includes: various Jie that can store program code such as movable storage device, ROM, magnetic or disk Matter.

The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.

Claims (12)

1. a kind of data verification method, comprising:

256 data are written in the storage region of the data storage cell of electronic equipment, and will be read from the storage region 256 data taken out are as the data obtained；

It is verified and is calculated according to 256 data of first checksum algorithm to write-in, generate 13 first verifications and data； It will be in the storage region of 13 first verifications and the data storage cell of data write-in electronic equipment；Wherein, described 13 first Verification and data are verified and are calculated according to the different bits of 32 monolithic devices in data storage cell；

The data of the acquisition are verified and calculated according to first checksum algorithm, generate 13 second verification sum numbers According to；

First verification and data and second verification and data are compared, comparison result is obtained；

The correctness of 256 data obtained is determined according to the comparison result.

2. the method as described in claim 1, which is characterized in that described to determine described 256 obtained according to the comparison result The correctness of position data, comprising:

When the comparison result shows first verification and data and second verification and data difference, acquisition is determined There are the data that mistake occurs in 256 data；When the comparison result shows first verification and data and described second When verifying identical with data, determine that there is no the data that mistake occurs in 256 data obtained.

3. the method as described in claim 1, which is characterized in that the method also includes:

Receive 256 data that another electronic equipment is sent；

Accordingly, 13 first verifications relevant to the data of acquisition and data generated according to the first checksum algorithm is obtained, It include: to receive 13 first verifications and data that another electronic equipment is sent, received 13 first verifications and data are Another electronic equipment carries out 256 data that needs are sent to the electronic equipment according to first checksum algorithm It verifies and calculates and obtain.

4. the method as described in claim 1, which is characterized in that the data by 256 data write-in electronic equipments store In the storage region of unit, specifically:

256 data are written to 32 monolithic devices in the data storage cell, wherein the monolithic device includes 8 bits.

5. method as claimed in claim 4, which is characterized in that according to first checksum algorithm to 256 digits of write-in According to being verified and being calculated, 13 first verifications and data are generated, are specifically included:

The 0th bit and the 4th bit of 32 monolithic devices are verified and calculated, generates described 13 first The 12nd in verification and data；

The first bit and the 5th bit of 32 monolithic devices are verified and calculated, generates described 13 first The 11st in verification and data；

The second bit and the 6th bit of 32 monolithic devices are verified and calculated, generates described 13 first The tenth in verification and data；

The third bit and the 7th bit of 32 monolithic devices are verified and calculated, generates described 13 first The 9th in verification and data；

To the monolithic device of the zero, the four, the eight, the 12nd, the 16th, the 20th and the 28th in 32 monolithic devices The the 0th to the 7th bit in part is verified and is calculated, and the 8th in 13 first verifications and data is generated；

To the first, the five, the nine, the 13rd, the 17th, the 21st and the 29th monolithic in 32 monolithic devices The the 0th to the 7th bit in device is verified and is calculated, and the 7th in 13 first verifications and data is generated；

To the second, the six, the ten, the 14th, the 18th, the 22nd and the 30th monolithic device in 32 monolithic devices The the 0th to the 7th bit in part is verified and is calculated, and the 6th in 13 first verifications and data is generated；

It is single to third, the seven, the 11st, the 15th, the 19th, the 23rd and the 31st in 32 monolithic devices The the 0th to the 7th bit in piece device is verified and is calculated, and the 5th in 13 first verifications and data is generated Position；

To the 0th in the zero, the first, second, and third monolithic device in 32 monolithic devices to third bit into Row verification and calculating generate the 4th in 13 first verifications and data；

4th to the 7th bit of 32 monolithic devices is verified and is calculated, generate it is described 13 first verification and Third position in data；

To the 0th in the the the 8th to the 15th, the 24th to the 31st monolithic device in 32 monolithic devices to Seven bits are verified and are calculated, and the second in 13 first verifications and data is generated；

To the 4th to the seven, the 12nd to the 15th, the 20th to the 23rd, the 28th in 32 monolithic devices The the 0th to the 7th bit into the 31st monolithic device is verified and is calculated, and the 13 first verifications sum number is generated First in；

School is carried out to the 0th to the 7th bit in the 16th to the 31st monolithic device in 32 monolithic devices It tests and calculates, generate the zero-bit in 13 first verifications and data.

6. the method as described in claim 1, which is characterized in that the method also includes:

In two verifications and memory device that described 13 first verifications and data are sequentially written in the data storage cell, Wherein, the verification and memory device include 8 bits.

7. such as method as claimed in any one of claims 1 to 6, which is characterized in that described by first verification and data and institute It states the second verification and data is compared, obtain comparison result, specifically include:

By described 13 second verification and data with described 13 first verify and data according to check bit one by one compared with, acquisition institute State comparison result；

Wherein, when it is described first verification and data with it is described second verify and data it is identical when, the comparison result for be all 0 or It is all 1, when first verification and data are with second verification and data difference, the comparison result is the verification of 13 bit-errors Coding.

8. the method for claim 7, which is characterized in that will it is described first verification and data and it is described second verification with Data are compared, after obtaining comparison result, the method also includes:

When the comparison result shows second verification and data and first verification and data difference, 13 schools are obtained Test table；

The 13 bit check table is searched according to the 13 bit-errors check code, obtains the data bit that mistake occurs；

It is corrected according to 256 data of the data bit to misplace to the acquisition.

9. a kind of electronic equipment, comprising:

Verification and data generating unit, for by the storage region of the data storage cell of 256 data write-in electronic equipment, And using 256 data read out from the storage region as the data obtained；According to the first checksum algorithm to write-in 256 data verified and calculated, generate 13 first verification and data；Wherein, 13 first verifications and data It is to be verified and be calculated according to the different bits of 32 monolithic devices in data storage cell；By 13 first In the storage region of the data storage cell of verification and data write-in electronic equipment；According to first checksum algorithm to described The data of acquisition are verified and are calculated, and 13 second verifications and data are generated；By first verification and data and described the Two verifications and data are compared, and obtain comparison result；256 data obtained are determined according to the comparison result just True property；

Data storage cell, for storing 256 data obtained；

Verification and data storage cell are related to the data of acquisition for storing generating according to the first checksum algorithm for acquisition 13 first verification and data.

10. electronic equipment as claimed in claim 9, which is characterized in that the data storage cell is specially 32 monolithic devices Part, wherein the monolithic device includes 8 bits；The verification and data generating unit are specifically used for described 256 32 monolithic devices in the data storage cell are written in data.

11. the electronic equipment as described in claim 9 or 10, which is characterized in that the data storage cell is specially x8 dynamic Random access memory DRAM.

12. a kind of data calibration device, which includes first acquisition unit, second acquisition unit, generation unit, comparing unit And determination unit, in which:

The first acquisition unit, for by the storage region of the data storage cell of 256 data write-in electronic equipment, and Using 256 data read out from the storage region as the data obtained；

The second acquisition unit, it is raw for being verified and being calculated according to 256 data of first checksum algorithm to write-in At 13 first verifications and data；By the storage region of 13 first verifications and the data storage cell of data write-in electronic equipment In；Wherein, 13 first verifications and data are the different bits according to 32 monolithic devices in data storage cell It is verified and is calculated；

The generation unit, it is raw for the data of the acquisition to be verified and calculated according to first checksum algorithm At 13 second verifications and data；

The comparing unit obtains ratio for being compared first verification and data and second verification and data Relatively result；

The determination unit, for determining the correctness of 256 data obtained according to the comparison result.