CN104991833A - Method and electronic equipment for error detection - Google Patents
Method and electronic equipment for error detection Download PDFInfo
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Abstract
The invention provides a method and a kind of electronic equipment for error detection, which comprises acquisition of 128-bit data and 12-bit first checksum data which is generated according to a first checksum algorithm and related to the acquired data, wherein the acquired data is checked and computed according to the first checksum algorithm, and 12-bit second checksum data is generated; and the first checksum data and the second checksum data are compared to obtain a comparison result, wherein wrong data exists in the acquired data if the comparison result shows that the first checksum data is different from the second checksum data. The method solves the technical problem in the prior art that long time will be spent on completing one time of ECC data checking, and realizes the technical effect of shortening the time spent on completing the one time of ECC checking.
Description
Technical field
The present invention relates to computer realm, particularly relate to a kind of error-detecting method and electronic equipment.
Background technology
ECC (Error Correcting Code is being carried out in prior art, Chinese full name: bug check and correction) data check time, checking algorithm is typically designed to and often reads 256 data and carry out the verification of ECC data, for the checking algorithm of 256 bit data, need 32 bit data to do ECC data verification.A root memory bar DIMM (Dual-Inline-Memory-Modules is only had at computing machine, Chinese full name: dual inline memory module) when, because DIMM provides the data channel of 64, then computing machine needs to carry out 4 read-writes to DIMM, 256 bit data could be write, and then complete an ECC verification.
But present inventor is in the process realizing invention technical scheme in the embodiment of the present application, find that above-mentioned technology at least exists following technical matters:
In prior art, owing to carrying out ECC data verification needs 256 bit data, then need to carry out 4 read-writes to DIMM, visible, exist in prior art, complete the time of an ECC data verification longer technical matters.
Summary of the invention
The invention provides a kind of error-detecting method and electronic equipment, for solving time completing the verification of ECC data of existing in prior art longer technical matters.
On the one hand, the embodiment of the present application provides a kind of error-detecting method, comprising:
Obtain 128 bit data, and 12 the first School Affairs data relevant to the data obtained generated according to the first checksum algorithm;
According to described first checksum algorithm, School Affairs calculating is carried out to the data of described acquisition, generate 12 the second School Affairs data;
Described first School Affairs data and described second School Affairs data are compared, obtain comparative result, wherein, if described comparative result shows that described first School Affairs data are different from described second School Affairs data, then there are the data made a mistake in the data of described acquisition.
Optionally, described acquisition 128 bit data, and 12 the first School Affairs data relevant to the data obtained generated according to the first checksum algorithm, specifically comprise:
By in the storage area of the data storage cell of 128 bit data write electronic equipments, carry out School Affairs calculating according to 128 bit data of described first checksum algorithm to write, generate described 12 the first School Affairs data; And using 128 bit data that read out from described storage area as the data obtained; Or
Receive 128 bit data of another electronic equipment transmission and described 12 the first School Affairs data, wherein, described 12 the first School Affairs data are that another electronic equipment described carries out School Affairs calculating, the School Affairs data of generation according to described first checksum algorithm to needing 128 bit data sent to described electronic equipment.
Optionally, described by the storage area of the data storage cell of 128 bit data write electronic equipments, be specially:
Described 128 bit data are write 32 monolithic devices in described data storage cell, wherein, described monolithic device comprises 4 bits.
Optionally, carry out School Affairs calculating according to 128 bit data of described first checksum algorithm to write, generate described 12 the first School Affairs data, specifically comprise:
Respectively to 32 the first bits in described 32 monolithic devices, 32 the second bits, 32 the 3rd bits and 32 the 4th bits carry out School Affairs calculating, generate first group of 4 bit check and data;
School Affairs calculating is carried out to 16 bits of first group of 4 monolithic device in described 32 monolithic devices, generates the 1st bit check and the data of second group;
To second group of 4 monolithic device in described 32 monolithic devices, the 3rd group of 4 monolithic devices, the 4th group of 4 monolithic devices, 64 bits in the 5th group of 4 monolithic devices carry out School Affairs calculating, generate the 2nd bit check and the data of second group;
To the 4th group of 4 monolithic devices in described 32 monolithic devices, the 5th group of 4 monolithic devices, the 6th group of 4 monolithic devices, 64 bits in the 7th group of 4 monolithic devices carry out School Affairs calculating, generate the 3rd bit check and the data of second group;
To the 3rd group of 4 monolithic devices in described 32 monolithic devices, the 5th group of 4 monolithic devices, the 7th group of 4 monolithic devices, 64 bits in the 8th group of 4 monolithic devices carry out School Affairs calculating, generate the 4th bit check and the data of second group;
School Affairs calculating is carried out to 32 bits in 8 the first monolithic devices in described first group of 4 monolithic device to described 8th group of 4 monolithic devices, generates the 3rd group of the 1st bit check and data;
School Affairs calculating is carried out to 32 bits in 8 the second monolithic devices in described first group of 4 monolithic device to described 8th group of 4 monolithic devices, generates the 3rd group of the 2nd bit check and data;
School Affairs calculating is carried out to 32 bits in 8 the 3rd monolithic devices in described first group of 4 monolithic device to described 8th group of 4 monolithic devices, generates the 3rd group of the 3rd bit check and data;
School Affairs calculating is carried out to 32 bits in 8 the 4th monolithic devices in described first group of 4 monolithic device to described 8th group of 4 monolithic devices, generates the 3rd group of the 4th bit check and data.
Optionally, after obtaining 12 the first School Affairs data relevant to the data obtained generated according to the first checksum algorithm, described method also comprises:
Write in 3 School Affairs memory devices in described data storage cell successively by described 12 the first School Affairs data, wherein, described School Affairs memory device comprises 4 bits.
Optionally, described described first School Affairs data and described second School Affairs data to be compared, obtain comparative result, specifically comprise:
Described 12 the first School Affairs data are obtained from described 3 School Affairs memory devices;
Described 12 the second School Affairs data are compared according to check bit one by one with described 12 the first School Affairs data, obtains described comparative result;
Wherein, when described first School Affairs data are identical with described second School Affairs data, described comparative result is for being 0 entirely or being 1 entirely, and when described first School Affairs data are different from described second School Affairs data, described comparative result is 12 bit-errors check codes.
Optionally, described first School Affairs data and described second School Affairs data are compared described, after obtaining comparative result, described method also comprises:
When described comparative result shows that described second School Affairs data are different from described first School Affairs data, according to described 12 bit-errors check codes, determine the data bit made a mistake, and the data of described acquisition are corrected.
Optionally, described according to described 12 bit-errors check codes, determine the data bit made a mistake, specifically comprise:
Obtain the corresponding relation that 128 data bit in described 32 monolithic devices and error-checking are encoded;
According to described 12 bit-errors check codes and described corresponding relation, determine the data bit made a mistake.
On the other hand, the embodiment of the present application also provides a kind of electronic equipment, comprising:
Data storage cell, for storing 128 bit data of acquisition;
School Affairs data storage cell, for storing 12 the first School Affairs data relevant to the data obtained generated according to the first checksum algorithm of acquisition;
School Affairs data generating unit, for carrying out School Affairs calculating according to described first checksum algorithm to the data of described acquisition, generates 12 the second School Affairs data; Described first School Affairs data and described second School Affairs data are compared, obtain comparative result, wherein, if described comparative result shows that described first School Affairs data are different from described second School Affairs data, then there are the data made a mistake in the data of described acquisition.
Optionally, described electronic equipment also comprises:
Processor, in the storage area for the data storage cell by 128 bit data write electronic equipments.
Optionally, described data storage cell is specially 32 monolithic devices, and wherein, described monolithic device comprises 4 bits; Described processor writes 32 monolithic devices in described data storage cell specifically for just described 128 bit data.
Optionally, described School Affairs data generating unit specifically for:
Described 12 the first School Affairs data are obtained from described School Affairs data storage cell;
Described 12 the second School Affairs data are compared according to check bit one by one with described 12 the first School Affairs data, obtains described comparative result;
Wherein, when described first School Affairs data are identical with described second School Affairs data, described comparative result is for being 0 entirely or being 1 entirely, and when described first School Affairs data are different from described second School Affairs data, described comparative result is 12 bit-errors check codes.
Optionally, described School Affairs data generating unit also for:
When described comparative result shows that described second School Affairs data are different from described first School Affairs data, according to described 12 bit-errors check codes, determine the data bit made a mistake, and the data of described acquisition are corrected, and the data after correcting are sent to described processor.
Optionally, described data storage cell is specially x4 dynamic RAM DRAM.
The one or more technical schemes provided in the embodiment of the present invention, at least have following technique effect or advantage:
In the scheme of the embodiment of the present application, getting 128 bit data, and to generate according to the first checksum algorithm to after relevant 12 the first School Affairs data of data obtained, according to described first checksum algorithm, School Affairs calculating is carried out to the data of described acquisition, generate 12 the second School Affairs data; Described first School Affairs data and described second School Affairs data are compared, obtain comparative result, wherein, if described comparative result shows that described first School Affairs data are different from described second School Affairs data, then there are the data made a mistake in the data of described acquisition.Visible, in the scheme of the embodiment of the present application, get 128 bit data and just carry out an ECC data verification, need to get 256 bit data in prior art, just carry out an ECC data verification, the time of an ECC data verification can have been shortened.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of the error-detecting method in the embodiment of the present application;
Fig. 2 is the configuration schematic diagram of the storage unit in the embodiment of the present application;
Fig. 3 is the structural representation of the electronic equipment in the embodiment of the present application.
Embodiment
The embodiment of the present invention provides a kind of error-detecting method and electronic equipment, an ECC verification is just carried out by reading 128 bit data, solve time completing the verification of ECC data of existing in prior art longer technical matters, achieve the technique effect having shortened the time that ECC data verifies.
Technical scheme in the embodiment of the present invention is solve above-mentioned technical matters, and general thought is as follows:
A kind of error-detecting method, comprising:
Obtain 128 bit data, and 12 the first School Affairs data relevant to the data obtained generated according to the first checksum algorithm;
According to described first checksum algorithm, School Affairs calculating is carried out to the data of described acquisition, generate 12 the second School Affairs data;
Described first School Affairs data and described second School Affairs data are compared, obtain comparative result, wherein, if described comparative result shows that described first School Affairs data are different from described second School Affairs data, then there are the data made a mistake in the data of described acquisition.
As can be seen from such scheme, in the scheme of the embodiment of the present application, get 128 bit data and just carry out an ECC data verification, need to get 256 bit data in prior art, just carry out an ECC data verification, the time of an ECC data verification can have been shortened.
Term "and/or" herein, being only a kind of incidence relation describing affiliated partner, can there are three kinds of relations in expression, and such as, A and/or B, can represent: individualism A, exists A and B simultaneously, these three kinds of situations of individualism B.In addition, character "/" herein, general expression forward-backward correlation is to the relation liking a kind of "or".
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
On the one hand, the present embodiment provides a kind of error-detecting method, as shown in Figure 1, comprising:
S10: obtain 128 bit data, and 12 the first School Affairs data relevant to the data obtained generated according to the first checksum algorithm.
S20: carry out School Affairs calculating to the data of described acquisition according to described first checksum algorithm, generates 12 the second School Affairs data.
S30: described first School Affairs data and described second School Affairs data are compared, obtain comparative result, wherein, if described comparative result shows that described first School Affairs data are different from described second School Affairs data, then there are the data made a mistake in the data of described acquisition.
Method in the embodiment of the present application is applied in x4 dynamic RAM DRAM (DynamicRandom Access Memory), then, in the embodiment of the present application, form 128 bit data be stored as needs 32 x4 DRAM by x4 DRAM.
Next, the method in the embodiment of the present application is described.
First, perform step S10, obtain 128 bit data, and 12 the first School Affairs data relevant to the data obtained generated according to the first checksum algorithm.
Specifically, the error-detecting method in the embodiment of the present application can as data write and reading process in error-detecting, also can as the error-detecting in data transmission procedure, then step S10 at least comprises following two kinds of situations.
The first situation, carries out error-detecting to the data read from data storage cell,
First, the processor of electronic equipment or Memory Controller Hub are by the storage area of the data storage cell of 128 bit data write electronic equipments.In the embodiment of the present application, data storage cell is 32 monolithic devices, i.e. 32 x4 DRAM, and wherein, each monolithic device comprises 4 bits, therefore, forms 128 bit data and stores needs 32 monolithic devices.
Then, carry out School Affairs calculating according to 128 bit data of the first checksum algorithm to write, generate described 12 the first School Affairs data; And using 128 bit data that read out from described storage area as the data obtained.
The second situation, carries out error-detecting to the data in data transmission procedure.
Receive 128 bit data of another electronic equipment transmission and described 12 the first School Affairs data, wherein, described 12 the first School Affairs data are that another electronic equipment described carries out School Affairs calculating, the School Affairs data of generation according to described first checksum algorithm to needing 128 bit data sent to described electronic equipment.
Specifically, another electronic equipment can be another computing machine, then 128 bit data obtained and 12 are position first School Affairs data is the data that this computing machine sends.
Next, the configuration of the embodiment of the present application for the storage unit storing data is described.As shown in Figure 2, be the configuration schematic diagram of storage unit in the embodiment of the present application.
In the embodiment of the present application, data storage cell comprises 32 monolithic devices, is respectively Dev0 to Dev31, specifically, forming 128 bit data bank bits by x4 DRAM needs 32 x4 DRAM, i.e. 32 monolithic devices, each monolithic device comprises 4 bits, is respectively b0 to b3.
Further, School Affairs data storage cell comprises 4 monolithic devices, is respectively Check0 to Check2 and Spare, and School Affairs data storage cell is for storing the School Affairs data generated in data check process.Each monolithic device comprises 4 bits, is respectively b0 to b3.
In prior art, read 256bits and just carry out an ECC verification, in the embodiment of the present application, read 128bits and just carry out an ECC verification, in the embodiment of the present application, the DIMM memory bar of employing is the DIMM continuing to use existing 18 monolithic devices, when reading data, can use two DIMM memory bars, DIMM provides the data channel of 64.Owing to only needing reading 128 bit data just to carry out an ECC verification in the embodiment of the present application, that is, every 1/4 cache lines (capable for 512 bit caches) carries out an ECC verification.And in prior art, need reading 256 bit data just to carry out an ECC verification, that is, every 1/2 cache lines (capable for 512 bit caches) just carries out an ECC verification.
In the embodiment of the present application, for 128 bit data, under precise synchronization pattern (LockStep ChannelMode), read data by two DIMM simultaneously, only need burst read-write cycle (burst), under autonomous channel pattern (Independent Channel Mode), read data by a DIMM simultaneously, only need two burst read-write cycles.And in prior art, for 256 bit data, under precise synchronization pattern, read data by two DIMM simultaneously, need two read-write cycles that happen suddenly, under the pattern of autonomous channel, to read data by a DIMM simultaneously, need 4 to happen suddenly the read-write cycle.Visible, in the embodiment of the present application, compared to existing technologies, utilize less time just can complete an ECC verification.
Further, in the embodiment of the present application, under precise synchronization pattern, need the monolithic device of 32 x4 in two DIMM to store data, then two are comprised to the DIMM of 18 monolithic devices, remain 4 monolithic devices and be used as ECC verification.Under the pattern of autonomous channel, need a DIMM to carry out twi-read, and 16bits is wherein used as ECC verification.
In the embodiment of the present application, 32 monolithic devices can be actual monolithic devices, may not be actual monolithic device, if use a DIMM, and DIMM only has 16+2 monolithic device, need reading could obtain the data of 128bits for twice, then actual monolithic device only has 16, in this case, 32 monolithic devices are not actual monolithic devices.
If use two DIMM, and DIMM has 16+2 monolithic device, then only need to read the data that once just can obtain 128bits, in this case, 32 monolithic devices are actual monolithic devices.
In the embodiment of the present application, for 128 bit data, only can generate 12 bit checks and data, therefore, in 4 monolithic devices as ECC verification, remaining 4bits can be used as standby functions.Although, precise synchronization pattern and autonomous channel pattern all can have 4bits to remain, but autonomous channel pattern needs 8bits just can be used as standby functions, therefore, under the pattern of autonomous channel, this 4bits cannot be utilized, and precise synchronization pattern, 4bits just can use as standby functions, then when there being monolithic device to damage, remaining 4bits can substitute the function of the monolithic device broken down.
Further, for autonomous channel pattern, when reading twice, the data of Check 0 and Check 2 (or Check1) can be stored on Same Physical monolithic device, but data can not cover mutually, but carry out interleaved.
Next, the checksum algorithm of 128bits in the embodiment of the present application is described.Specifically, School Affairs formula is as follows.
Check0 b0＝checksum{Dev 0～31 bit0}
Check0 b1＝checksum{Dev 0～31 bit1}
Check0 b2＝checksum{Dev 0～31 bit2}
Check0 b3＝checksum{Dev 0～31 bit3}
Check1 b0＝checksum{Dev 0,4,8,12,16,20,24,28 all bit 0～3}
Check1 b1＝checksum{Dev 1,5,9,13,17,21,25,29 all bit 0～3}
Check1 b2＝checksum{Dev 2,6,10,14,18,22,26,30 all bit 0～3}
Check1 b3＝checksum{Dev 3,7,11,15,19,23,27,31 all bit 0～3}
Check2 b0＝checksum{Dev 0,1,2,3all bit 0～3}
Check2 b1＝checksum{Dev 4,5,6,7,12,13,14,15,20,21,22,23,28,29,30,31 all bit 0～3}
Check2 b2＝checksum{Dev 8,9,10,11,12,13,14,15,24,25,26,27,28,29,30,31 all bit 0～3}
Check2 b3＝checksum{Dev 16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 all bit 0～3}
Wherein, Check0 b0 represents the first bit check in School Affairs storage unit in first group of School Affairs data and data, and Dev 0 ~ 31 bit0 represents 32 the first bits in data storage cell in 32 monolithic devices, Dev 0,4,8,12,16,20,24,28 all bit 0 ~ 3 represent Dev 0, Dev 4 in data storage cell, Dev 8, Dev 12, Dev 16, these 32 bits of bit 0 ~ 3 in these 8 monolithic devices of Dev 20, Dev 24, Dev 028.Checksum is checksum algorithm, in the embodiment of the present application, can adopt XOR XOR or or the mode of non-NOR carry out School Affairs calculating, then can produce the data of a bit, that is the value of Check0 b0 can be only 0 or 1.
Same, Check0 b1 to Check2 b3 also adopts the checksum algorithm identical with Check0 b0 to carry out School Affairs calculating.Wherein, Check0 b0 to Check1 b3 be 32 bit checks and, Check2 b0 be 16 bit checks and, Check2 b1 to Check2 b3 be 64 bit checks with.
Specifically, adopt the checksum algorithm in the embodiment of the present application, according to 128bits, 12 bit checks and data can be generated, be stored in respectively in Check0 to Check2, then a remaining monolithic device Spare can as monolithic device for subsequent use, and when there being monolithic device to damage, Spare can substitute the function of the monolithic device broken down.
Next, from internal memory, read data instance with processor, the error-detecting method in the embodiment of the present application is described, internal memory here, the data storage cell namely in above-described embodiment.
As shown in Figure 3, while data are write data storage cell 20 by processor (or Memory Controller Hub) 10, data are write School Affairs data generating unit 30, School Affairs data generating unit 30 generates School Affairs data, and by these School Affairs data write School Affairs data storage cell 40, wherein, 50 is the data transmission bus between data storage cell 20 and School Affairs data generating unit 30, and 60 is the data transmission bus between School Affairs data storage cell 40 and School Affairs data generating unit 30.
When processor (or Memory Controller Hub) 10 reads data from data storage cell 20, the data of reading can be sent to School Affairs data generating unit 30, and regenerate School Affairs data according to the data read, then the School Affairs data stored in the School Affairs data regenerated and School Affairs data storage cell 20 are compared, if the School Affairs data of twice are identical, then direct data in data storage cell 20 are sent to processor (or Memory Controller Hub) 10, if the School Affairs data of twice are different, then School Affairs data generating unit 30 can be corrected the data in data storage cell 20, and the data after correcting are sent to processor (or Memory Controller Hub) 10.
In above-described embodiment, be illustrated the checksum algorithm generating School Affairs data, specifically, to internal memory write data with when reading data from internal memory, the checksum algorithm of employing is identical.Next, being relatively described to the School Affairs data of twice generation.
Specifically, 12 the second School Affairs data generated when reading data compared one by one according to check bit with the first School Affairs data of 12 in School Affairs data storage cell 20, obtain comparative result, namely 12 bit-errors check codes, as shown in table 1.
Table 1
Wherein, when described first School Affairs data are identical with described second School Affairs data, described comparative result is for being 0 entirely or being 1 entirely, and when described first School Affairs data are different from described second School Affairs data, described comparative result is 12 bit-errors check codes.
Specifically, when comparing twice School Affairs data, when any a data in Dev 0 to Dev 31 makes a mistake, corresponding error-checking coding is as shown in table 1.Table 1 is the result obtained with the algorithm of XOR, if with NOR algorithm, then can obtain antipodal content, namely 1 in form becomes 0, and 0 becomes 1.
Can be found out by table 1, when each data in Dev 0 to Dev 31 make a mistake, there is unique ECC error-checking coding, therefore, in data check process, the 12 bit-errors check codes obtained are compared according to twice School Affairs data, and the corresponding relation that each data in Dev 0 to Dev 31 and error-checking are encoded, the data bit made a mistake can be determined, such as: the error-checking coding Check0-(b0 obtained, b1, b2, b3), Check1-(b0, b1, b2, b3), Check2-(b0, b1, b2, b3) be 1,000 10001000, then determine that the data bit made a mistake in Dev 0 to Dev 31 is Dev 0 Bit0, again such as: the error-checking obtained is encoded to 0,100 0,100 1000, then determine that the data bit made a mistake in Dev 0 to Dev 31 is Dev 1 Bit1.
In the embodiment of the present application, after determining the data bit made a mistake, need to correct data.Then, the data after correction are sent to processor (or Memory Controller Hub) 10.
Next, the checksum algorithm in the embodiment of the present application is further described, except above-mentioned School Affairs formula, following situation can also be comprised.
The first situation, for (Dev0 ~ Dev3), (Dev4 ~ Dev7), (Dev8 ~ Dev11), (Dev12 ~ Dev15), (Dev16 ~ Dev19), (Dev20 ~ Dev23), (Dev24 ~ Dev27), the grouping of (Dev28 ~ Dev31), any two monolithic devices often in group can exchange mutually, such as: exchanged by Dev 0 and Dev 1, again such as, Dev4 and Dev7 is exchanged.
Next, carry out exchange with Dev 0 and Dev 1 and be described, then the School Affairs data changed in above-mentioned School Affairs formula are Check1 b0 and Check1 b1, specific as follows:
Check1 b0＝checksum{Dev 1,4,8,12,16,20,24,28 all bit 0～3}
Check1 b1＝checksum{Dev 0,5,9,13,17,21,25,29 all bit 0～3}
Corresponding, error-checking coding also can change, as shown in table 2, for Dev 0 and Dev 1 exchange after error-checking coding schedule, can find out, error-checking that in Dev 0 and Dev 1, data bit is corresponding coding exchanges, and error-checking coding corresponding to data bit in other monolithic device can not change.
Table 2
The second situation, for following grouping Dev (0,4,8,12,16,20,24,28), (1,5,9,13,17,21,25,29), (2,6,10,14,18,22,26,30), (3,7,11,15,19,23,27,31) divide into groups, any two monolithic devices often in group can exchange mutually.Such as: Dev 0 and Dev 4 is exchanged, again such as, Dev4 and Dev12 is exchanged.
Next, Dev 0 and Dev 4 carries out exchange and is described, then the School Affairs data changed in above-mentioned School Affairs formula are Check2 b0 and Check2 b1, specific as follows:
Check2 b0＝checksum{Dev 4,1,2,3 all bit 0～3}
Check2 b1＝checksum{Dev 0,5,6,7,12,13,14,15,20,21,22,23,28,29,30,31 all bit 0～3}
Corresponding, error-checking coding also can change, as shown in table 3, for Dev 0 and Dev 4 exchange after error-checking coding schedule, can find out, error-checking that in Dev 0 and Dev 4, data bit is corresponding coding exchanges, and error-checking coding corresponding to data bit in other monolithic device can not change.
Table 3
The third situation, exchanges monolithic device in conjunction with the first situation and the second situation.Such as: Dev 0 and Dev 1 can exchange, Dev 0 and Dev 4 exchanges, then Dev 1 and Dev4 can be exchanged.
Next, Dev 1 and Dev 4 carries out exchange and is described, then the School Affairs data changed in above-mentioned School Affairs formula are Check1 b0, Check1 b1, Check2 b0 and Check2 b1, specific as follows:
Check1 b0＝checksum{Dev 0,1,8,12,16,20,24,28 all bit 0～3}
Check1 b1＝checksum{Dev 4,5,9,13,17,21,25,29 all bit 0～3}
Check2 b0＝checksum{Dev 0,4,2,3 all bit 0～3}
Check2 b1＝checksum{Dev 1,5,6,7,12,13,14,15,20,21,22,23,28,29,30,31 all bit 0～3}
Corresponding, error-checking coding also can change, as shown in table 4, for Dev 1 and Dev 4 exchange after error-checking coding schedule, can find out, error-checking that in Dev 1 and Dev 4, data bit is corresponding coding exchanges, and error-checking coding corresponding to data bit in other monolithic device can not change.
Table 4
On the other hand, the embodiment of the present application also provides a kind of electronic equipment, as shown in Figure 3, comprising: data storage cell 20, for storing 128 bit data of acquisition;
School Affairs data storage cell 40, for storing 12 the first School Affairs data relevant to the data obtained generated according to the first checksum algorithm of acquisition;
School Affairs data generating unit 30, for carrying out School Affairs calculating according to described first checksum algorithm to the data of described acquisition, generates 12 the second School Affairs data; Described first School Affairs data and described second School Affairs data are compared, obtain comparative result, wherein, if described comparative result shows that described first School Affairs data are different from described second School Affairs data, then there are the data made a mistake in the data of described acquisition.
Optionally, described electronic equipment also comprises:
Processor 10, in the storage area for the data storage cell 20 by 128 bit data write electronic equipments.
Optionally, described data storage cell 20 is specially 32 monolithic devices, and wherein, described monolithic device comprises 4 bits; Processor 10 writes 32 monolithic devices in described data storage cell specifically for just described 128 bit data.
Optionally, described School Affairs data generating unit 30 specifically for:
Described 12 the first School Affairs data are obtained from described School Affairs data storage cell 40;
Described 12 the second School Affairs data are compared according to check bit one by one with described 12 the first School Affairs data, obtains described comparative result;
Wherein, when described first School Affairs data are identical with described second School Affairs data, described comparative result is for being 0 entirely or being 1 entirely, and when described first School Affairs data are different from described second School Affairs data, described comparative result is 12 bit-errors check codes.
Optionally, described School Affairs data generating unit 30 also for:
When described comparative result shows that described second School Affairs data are different from described first School Affairs data, according to described 12 bit-errors check codes, determine the data bit made a mistake, and the data of described acquisition are corrected, and the data after correcting are sent to described processor.
Optionally, described data storage cell 20 is specially x4 dynamic RAM DRAM.
By the one or more technical schemes in the embodiment of the present application, following one or more technique effect can be realized:
In the scheme of the embodiment of the present application, getting 128 bit data, and to generate according to the first checksum algorithm to after relevant 12 the first School Affairs data of data obtained, according to described first checksum algorithm, School Affairs calculating is carried out to the data of described acquisition, generate 12 the second School Affairs data; Described first School Affairs data and described second School Affairs data are compared, obtain comparative result, wherein, if described comparative result shows that described first School Affairs data are different from described second School Affairs data, then there are the data made a mistake in the data of described acquisition.Visible, in the scheme of the embodiment of the present application, get 128 bit data and just carry out an ECC data verification, need to get 256 bit data in prior art, just carry out an ECC data verification, the time of an ECC data verification can have been shortened.
Those skilled in the art should understand, embodiments of the invention can be provided as method, system or computer program.Therefore, the present invention can adopt the form of complete hardware embodiment, completely software implementation or the embodiment in conjunction with software and hardware aspect.And the present invention can adopt in one or more form wherein including the upper computer program implemented of computer-usable storage medium (including but not limited to magnetic disk memory, CD-ROM, optical memory etc.) of computer usable program code.
The present invention describes with reference to according to the process flow diagram of the method for the embodiment of the present invention, equipment (system) and computer program and/or block scheme.Should understand can by the combination of the flow process in each flow process in computer program instructions realization flow figure and/or block scheme and/or square frame and process flow diagram and/or block scheme and/or square frame.These computer program instructions can being provided to the processor of multi-purpose computer, special purpose computer, Embedded Processor or other programmable data processing device to produce a machine, making the instruction performed by the processor of computing machine or other programmable data processing device produce device for realizing the function of specifying in process flow diagram flow process or multiple flow process and/or block scheme square frame or multiple square frame.
These computer program instructions also can be stored in can in the computer-readable memory that works in a specific way of vectoring computer or other programmable data processing device, the instruction making to be stored in this computer-readable memory produces the manufacture comprising command device, and this command device realizes the function of specifying in process flow diagram flow process or multiple flow process and/or block scheme square frame or multiple square frame.
These computer program instructions also can be loaded in computing machine or other programmable data processing device, make on computing machine or other programmable devices, to perform sequence of operations step to produce computer implemented process, thus the instruction performed on computing machine or other programmable devices is provided for the step realizing the function of specifying in process flow diagram flow process or multiple flow process and/or block scheme square frame or multiple square frame.
Specifically, the computer program instructions that error-detecting method in the embodiment of the present application is corresponding can be stored in CD, hard disk, on the storage mediums such as USB flash disk, read by an electronic equipment when the computer program instructions corresponding with error-detecting method in storage medium or when being performed, comprise the steps:
Obtain 128 bit data, and 12 the first School Affairs data relevant to the data obtained generated according to the first checksum algorithm;
According to described first checksum algorithm, School Affairs calculating is carried out to the data of described acquisition, generate 12 the second School Affairs data;
Described first School Affairs data and described second School Affairs data are compared, obtain comparative result, wherein, if described comparative result shows that described first School Affairs data are different from described second School Affairs data, then there are the data made a mistake in the data of described acquisition.
Optionally, that store in described storage medium and step: obtain 128 bit data, and to generate according to the first checksum algorithm to relevant 12 the first School Affairs data of data obtained, the computer instruction of correspondence, being specifically performed in process, specifically comprises the steps:
By in the storage area of the data storage cell of 128 bit data write electronic equipments, carry out School Affairs calculating according to 128 bit data of described first checksum algorithm to write, generate described 12 the first School Affairs data; And using 128 bit data that read out from described storage area as the data obtained; Or
Receive 128 bit data of another electronic equipment transmission and described 12 the first School Affairs data, wherein, described 12 the first School Affairs data are that another electronic equipment described carries out School Affairs calculating, the School Affairs data of generation according to described first checksum algorithm to needing 128 bit data sent to described electronic equipment.
Optionally, that store in described storage medium and step: 128 bit data write in the storage area of the data storage cell of electronic equipment, corresponding computer instruction, being specifically performed in process, specifically comprises the steps:
Described 128 bit data are write 32 monolithic devices in described data storage cell, wherein, described monolithic device comprises 4 bits.
Optionally, that store in described storage medium and step: School Affairs calculating is carried out to 128 bit data write according to described first checksum algorithm, generate described 12 the first School Affairs data, corresponding computer instruction, being specifically performed in process, specifically comprises the steps:
Respectively to 32 the first bits in described 32 monolithic devices, 32 the second bits, 32 the 3rd bits and 32 the 4th bits carry out School Affairs calculating, generate first group of 4 bit check and data;
School Affairs calculating is carried out to 16 bits of first group of 4 monolithic device in described 32 monolithic devices, generates the 1st bit check and the data of second group;
To second group of 4 monolithic device in described 32 monolithic devices, the 3rd group of 4 monolithic devices, the 4th group of 4 monolithic devices, 64 bits in the 5th group of 4 monolithic devices carry out School Affairs calculating, generate the 2nd bit check and the data of second group;
To the 4th group of 4 monolithic devices in described 32 monolithic devices, the 5th group of 4 monolithic devices, the 6th group of 4 monolithic devices, 64 bits in the 7th group of 4 monolithic devices carry out School Affairs calculating, generate the 3rd bit check and the data of second group;
To the 3rd group of 4 monolithic devices in described 32 monolithic devices, the 5th group of 4 monolithic devices, the 7th group of 4 monolithic devices, 64 bits in the 8th group of 4 monolithic devices carry out School Affairs calculating, generate the 4th bit check and the data of second group;
School Affairs calculating is carried out to 32 bits in 8 the first monolithic devices in described first group of 4 monolithic device to described 8th group of 4 monolithic devices, generates the 3rd group of the 1st bit check and data;
School Affairs calculating is carried out to 32 bits in 8 the second monolithic devices in described first group of 4 monolithic device to described 8th group of 4 monolithic devices, generates the 3rd group of the 2nd bit check and data;
School Affairs calculating is carried out to 32 bits in 8 the 3rd monolithic devices in described first group of 4 monolithic device to described 8th group of 4 monolithic devices, generates the 3rd group of the 3rd bit check and data;
School Affairs calculating is carried out to 32 bits in 8 the 4th monolithic devices in described first group of 4 monolithic device to described 8th group of 4 monolithic devices, generates the 3rd group of the 4th bit check and data.
Optionally, other computer instruction is also stored in described storage medium, these computer instructions to step: obtain that generate according to the first checksum algorithm with relevant 12 the first School Affairs data of data that are that obtain, after corresponding computer instruction is performed, being performed, comprising the steps: when being performed
Write in 3 School Affairs memory devices in described data storage cell successively by described 12 the first School Affairs data, wherein, described School Affairs memory device comprises 4 bits.
Optionally, that store in described storage medium and step: described first School Affairs data and described second School Affairs data are compared, obtain comparative result, corresponding computer instruction, being specifically performed in process, specifically comprises the steps:
Described 12 the first School Affairs data are obtained from described 3 School Affairs memory devices;
Described 12 the second School Affairs data are compared according to check bit one by one with described 12 the first School Affairs data, obtains described comparative result;
Wherein, when described first School Affairs data are identical with described second School Affairs data, described comparative result is for being 0 entirely or being 1 entirely, and when described first School Affairs data are different from described second School Affairs data, described comparative result is 12 bit-errors check codes.
Optionally, other computer instruction is also stored in described storage medium, these computer instructions with step: described first School Affairs data and described second School Affairs data are compared, obtain comparative result, after corresponding computer instruction is performed, being performed, comprising the steps: when being performed
When described comparative result shows that described second School Affairs data are different from described first School Affairs data, according to described 12 bit-errors check codes, determine the data bit made a mistake, and the data of described acquisition are corrected.
Optionally, that store in described storage medium and step: according to described 12 bit-errors check codes, determine the data bit made a mistake, corresponding computer instruction, being specifically performed in process, specifically comprises the steps:
Obtain the corresponding relation that 128 data bit in described 32 monolithic devices and error-checking are encoded;
According to described 12 bit-errors check codes and described corresponding relation, determine the data bit made a mistake.
Although describe the preferred embodiments of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of the scope of the invention.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (14)
1. an error-detecting method, comprising:
Obtain 128 bit data, and 12 the first School Affairs data relevant to the data obtained generated according to the first checksum algorithm;
According to described first checksum algorithm, School Affairs calculating is carried out to the data of described acquisition, generate 12 the second School Affairs data;
Described first School Affairs data and described second School Affairs data are compared, obtain comparative result, wherein, if described comparative result shows that described first School Affairs data are different from described second School Affairs data, then there are the data made a mistake in the data of described acquisition.
2. the method for claim 1, is characterized in that, described acquisition 128 bit data, and 12 the first School Affairs data relevant to the data obtained generated according to the first checksum algorithm, specifically comprises:
By in the storage area of the data storage cell of 128 bit data write electronic equipments, carry out School Affairs calculating according to 128 bit data of described first checksum algorithm to write, generate described 12 the first School Affairs data; And using 128 bit data that read out from described storage area as the data obtained; Or
Receive 128 bit data of another electronic equipment transmission and described 12 the first School Affairs data, wherein, described 12 the first School Affairs data are that another electronic equipment described carries out School Affairs calculating, the School Affairs data of generation according to described first checksum algorithm to needing 128 bit data sent to described electronic equipment.
3. method as claimed in claim 2, is characterized in that, described by the storage area of the data storage cell of 128 bit data write electronic equipments, is specially:
Described 128 bit data are write 32 monolithic devices in described data storage cell, wherein, described monolithic device comprises 4 bits.
4. method as claimed in claim 3, is characterized in that, carries out School Affairs calculating, generate described 12 the first School Affairs data, specifically comprise according to 128 bit data of described first checksum algorithm to write:
Respectively to 32 the first bits in described 32 monolithic devices, 32 the second bits, 32 the 3rd bits and 32 the 4th bits carry out School Affairs calculating, generate first group of 4 bit check and data;
School Affairs calculating is carried out to 16 bits of first group of 4 monolithic device in described 32 monolithic devices, generates the 1st bit check and the data of second group;
To second group of 4 monolithic device in described 32 monolithic devices, the 3rd group of 4 monolithic devices, the 4th group of 4 monolithic devices, 64 bits in the 5th group of 4 monolithic devices carry out School Affairs calculating, generate the 2nd bit check and the data of second group;
To the 4th group of 4 monolithic devices in described 32 monolithic devices, the 5th group of 4 monolithic devices, the 6th group of 4 monolithic devices, 64 bits in the 7th group of 4 monolithic devices carry out School Affairs calculating, generate the 3rd bit check and the data of second group;
To the 3rd group of 4 monolithic devices in described 32 monolithic devices, the 5th group of 4 monolithic devices, the 7th group of 4 monolithic devices, 64 bits in the 8th group of 4 monolithic devices carry out School Affairs calculating, generate the 4th bit check and the data of second group;
School Affairs calculating is carried out to 32 bits in 8 the first monolithic devices in described first group of 4 monolithic device to described 8th group of 4 monolithic devices, generates the 3rd group of the 1st bit check and data;
School Affairs calculating is carried out to 32 bits in 8 the second monolithic devices in described first group of 4 monolithic device to described 8th group of 4 monolithic devices, generates the 3rd group of the 2nd bit check and data;
School Affairs calculating is carried out to 32 bits in 8 the 3rd monolithic devices in described first group of 4 monolithic device to described 8th group of 4 monolithic devices, generates the 3rd group of the 3rd bit check and data;
School Affairs calculating is carried out to 32 bits in 8 the 4th monolithic devices in described first group of 4 monolithic device to described 8th group of 4 monolithic devices, generates the 3rd group of the 4th bit check and data.
5. method as claimed in claim 4, is characterized in that, after obtaining 12 the first School Affairs data relevant to the data obtained generated according to the first checksum algorithm, described method also comprises:
Write in 3 School Affairs memory devices in described data storage cell successively by described 12 the first School Affairs data, wherein, described School Affairs memory device comprises 4 bits.
6. method as claimed in claim 5, is characterized in that, describedly described first School Affairs data and described second School Affairs data is compared, and obtains comparative result, specifically comprises:
Described 12 the first School Affairs data are obtained from described 3 School Affairs memory devices;
Described 12 the second School Affairs data are compared according to check bit one by one with described 12 the first School Affairs data, obtains described comparative result;
Wherein, when described first School Affairs data are identical with described second School Affairs data, described comparative result is for being 0 entirely or being 1 entirely, and when described first School Affairs data are different from described second School Affairs data, described comparative result is 12 bit-errors check codes.
7. method as claimed in claim 6, is characterized in that, described first School Affairs data and described second School Affairs data are being compared, and after obtaining comparative result, described method also comprises:
When described comparative result shows that described second School Affairs data are different from described first School Affairs data, according to described 12 bit-errors check codes, determine the data bit made a mistake, and the data of described acquisition are corrected.
8. method as claimed in claim 7, is characterized in that, described according to described 12 bit-errors check codes, determines the data bit made a mistake, specifically comprises:
Obtain the corresponding relation that 128 data bit in described 32 monolithic devices and error-checking are encoded;
According to described 12 bit-errors check codes and described corresponding relation, determine the data bit made a mistake.
9. an electronic equipment, comprising:
Data storage cell, for storing 128 bit data of acquisition;
School Affairs data storage cell, for storing 12 the first School Affairs data relevant to the data obtained generated according to the first checksum algorithm of acquisition;
School Affairs data generating unit, for carrying out School Affairs calculating according to described first checksum algorithm to the data of described acquisition, generates 12 the second School Affairs data; Described first School Affairs data and described second School Affairs data are compared, obtain comparative result, wherein, if described comparative result shows that described first School Affairs data are different from described second School Affairs data, then there are the data made a mistake in the data of described acquisition.
10. electronic equipment as claimed in claim 9, it is characterized in that, described electronic equipment also comprises:
Processor, in the storage area for the data storage cell by 128 bit data write electronic equipments.
11. electronic equipments as claimed in claim 10, it is characterized in that, described data storage cell is specially 32 monolithic devices, and wherein, described monolithic device comprises 4 bits; Described processor writes 32 monolithic devices in described data storage cell specifically for just described 128 bit data.
12. electronic equipments as claimed in claim 11, is characterized in that, described School Affairs data generating unit specifically for:
Described 12 the first School Affairs data are obtained from described School Affairs data storage cell;
Described 12 the second School Affairs data are compared according to check bit one by one with described 12 the first School Affairs data, obtains described comparative result;
Wherein, when described first School Affairs data are identical with described second School Affairs data, described comparative result is for being 0 entirely or being 1 entirely, and when described first School Affairs data are different from described second School Affairs data, described comparative result is 12 bit-errors check codes.
13. electronic equipments as claimed in claim 12, is characterized in that, described School Affairs data generating unit also for:
When described comparative result shows that described second School Affairs data are different from described first School Affairs data, according to described 12 bit-errors check codes, determine the data bit made a mistake, and the data of described acquisition are corrected, and the data after correcting are sent to described processor.
14. electronic equipments as claimed in claim 9, it is characterized in that, described data storage cell is specially x4 dynamic RAM DRAM.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108665939A (en) * | 2017-03-31 | 2018-10-16 | 厦门鑫忆讯科技有限公司 | The method and apparatus of ECC is provided for memory |
| CN111279411A (en) * | 2017-11-06 | 2020-06-12 | 高通股份有限公司 | Memory address flipping for determining data content integrity in GPU subsystems |
| CN111352754A (en) * | 2018-12-21 | 2020-06-30 | 航天科工惯性技术有限公司 | Data storage error detection and correction method and data storage device |
| CN111506506A (en) * | 2020-04-15 | 2020-08-07 | 湖南国科微电子股份有限公司 | Test method, device, equipment and readable storage medium |
| CN112688759A (en) * | 2019-10-18 | 2021-04-20 | 青岛海尔空调电子有限公司 | Data receiving and processing method and device |
| CN113282244A (en) * | 2021-06-10 | 2021-08-20 | 辽宁警察学院 | Data storage method and device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101281481A (en) * | 2008-05-23 | 2008-10-08 | 北京时代民芯科技有限公司 | Method for error correcting and detecting for memory anti-single particle overturn |
| US20090164869A1 (en) * | 2007-12-21 | 2009-06-25 | Winbond Electronics Corp. | Memory architecture and configuration method thereof |
| CN101477481A (en) * | 2009-02-06 | 2009-07-08 | 中国科学院计算技术研究所 | Automatic error correction system and method |
| CN101681283A (en) * | 2007-06-28 | 2010-03-24 | 国际商业机器公司 | System and method for error correction and detection in a memory system |
| CN102110028A (en) * | 2009-12-25 | 2011-06-29 | 康佳集团股份有限公司 | NAND flash memory as well as data checking method and device thereof |
| CN104347122A (en) * | 2013-07-31 | 2015-02-11 | 华为技术有限公司 | Accessing and memorizing method and accessing and memorizing device of message type DRAM (Dynamic Random Access Memory) module |
| CN104637542A (en) * | 2013-11-11 | 2015-05-20 | 旺宏电子股份有限公司 | Memory device for storing error correcting code corresponding to data and operation method thereof |
-
2015
- 2015-06-15 CN CN201510330664.9A patent/CN104991833B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101681283A (en) * | 2007-06-28 | 2010-03-24 | 国际商业机器公司 | System and method for error correction and detection in a memory system |
| US20090164869A1 (en) * | 2007-12-21 | 2009-06-25 | Winbond Electronics Corp. | Memory architecture and configuration method thereof |
| CN101281481A (en) * | 2008-05-23 | 2008-10-08 | 北京时代民芯科技有限公司 | Method for error correcting and detecting for memory anti-single particle overturn |
| CN101477481A (en) * | 2009-02-06 | 2009-07-08 | 中国科学院计算技术研究所 | Automatic error correction system and method |
| CN102110028A (en) * | 2009-12-25 | 2011-06-29 | 康佳集团股份有限公司 | NAND flash memory as well as data checking method and device thereof |
| CN104347122A (en) * | 2013-07-31 | 2015-02-11 | 华为技术有限公司 | Accessing and memorizing method and accessing and memorizing device of message type DRAM (Dynamic Random Access Memory) module |
| CN104637542A (en) * | 2013-11-11 | 2015-05-20 | 旺宏电子股份有限公司 | Memory device for storing error correcting code corresponding to data and operation method thereof |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108665939A (en) * | 2017-03-31 | 2018-10-16 | 厦门鑫忆讯科技有限公司 | The method and apparatus of ECC is provided for memory |
| CN111279411A (en) * | 2017-11-06 | 2020-06-12 | 高通股份有限公司 | Memory address flipping for determining data content integrity in GPU subsystems |
| CN111352754A (en) * | 2018-12-21 | 2020-06-30 | 航天科工惯性技术有限公司 | Data storage error detection and correction method and data storage device |
| CN111352754B (en) * | 2018-12-21 | 2023-09-15 | 中国石油天然气集团有限公司 | Error detection and correction method for data storage and data storage device |
| CN112688759A (en) * | 2019-10-18 | 2021-04-20 | 青岛海尔空调电子有限公司 | Data receiving and processing method and device |
| CN112688759B (en) * | 2019-10-18 | 2022-04-22 | 青岛海尔空调电子有限公司 | Data receiving and processing method and device |
| CN111506506A (en) * | 2020-04-15 | 2020-08-07 | 湖南国科微电子股份有限公司 | Test method, device, equipment and readable storage medium |
| CN113282244A (en) * | 2021-06-10 | 2021-08-20 | 辽宁警察学院 | Data storage method and device |
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|---|---|
| CN104991833B (en) | 2018-03-27 |
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