CN102104331B

CN102104331B - Frequency compensating circuit suitable for switched-capacitor direct-current voltage converter

Info

Publication number: CN102104331B
Application number: CN 201010611340
Authority: CN
Inventors: 王科军; 李文宏; 宫艳
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2010-12-29
Filing date: 2010-12-29
Publication date: 2013-07-31
Anticipated expiration: 2030-12-29
Also published as: CN102104331A

Abstract

The invention belongs to the technical field of integrated circuits, in particular to a frequency compensating circuit suitable for a switched-capacitor direct-current voltage converter. The circuit mainly comprises an error amplifier, two in-chip capacitors, an in-chip resistor, an N-channel metal oxide semiconductor (NMOS) transistor, two P-channel metal oxide semiconductor (PMOS) transistors and a current source. The circuit ensures high stability and high output voltage accuracy of a system by a method for inserting a zero-pole point into a loop and pushing an original main pole point away.

Description

A kind of frequency compensated circuit that is applicable to the switching capacity dc voltage changer

Technical field

The invention belongs to technical field of integrated circuits, a kind of frequency compensated circuit that is specifically related to is mainly used in the switching capacity DC/DC transducer.

Background technology

Present Switching Power Supply DC/DC transducer mainly contains two types.A kind of transducer that is based on inductive type.Such transducer adopts the PWM control mode usually, and loop adopts compensation of II class and III class compensation way to guarantee the stability of system usually.Another just is based on capacitive based transducer.

In traditional switching capacity transducer, the common PFM mode of operation that adopts, feedback control loop all is non-linear digital control basically, does not have stability problem, thereby does not need compensating circuit.But the shortcoming of PFM mode of operation is that output voltage ripple is big and output frequency is unpredictable.This has just limited the application of switching capacity type transducer in the noise-sensitive occasion.In order to overcome the above problems, the transducer of this paper design has adopted the input Current limited Control, feed back in the control of input current by the margin of error of loop output voltage, the switch input current is substantially equal to load current under the stable state, thereby ripple is very little, but this scheme feedback control loop is a Linear Control, has stability problem, and compensating circuit must be arranged.The compensating circuit that the present invention proposes designs at the dc voltage changer of this type switching capacity.

Summary of the invention

The objective of the invention is to propose a kind ofly can guarantee system's good stable and output voltage accuracy frequency compensated circuit.This circuit can be applied to import in the loop compensation of current-limiting type switching capacity DC/DC transducer.

The frequency compensated circuit that the present invention proposes, as shown in Figure 1.Comprise an error amplifier, electric capacity in two sheets, resistance in the sheet, a NMOS pipe, two PMOS pipes, a current source; Wherein, by capacitor C 1, C2 in two sheets, resistance R 1 and error amplifier Erramp provide the pole and zero-1/R1C1 of a low frequency in sheet, are used in the compensation loop original dominant pole and improve the direct voltage gain.Two PMOS pipes M1, M2 realize the unit gain inverter functionality of small-signal, are negative feedbacks to guarantee loop.Current source and metal-oxide-semiconductor M3 pipe adopt the structure of source follower, and purpose is that the low-frequency pole that input current limiting tube MP grid is introduced is pushed into high frequency, to satisfy the requirement of unity gain bandwidth GBW and phase margin.

Description of drawings

Fig. 1 compensating circuit structure of the present invention.

Fig. 2 switching capacity transducer integrated stand composition.

Fig. 3 does not add the loop small-signal analysis of compensation.

Loop small-signal analysis after Fig. 4 compensation.

Fig. 5 error amplifier structure chart.

Fig. 6 output voltage steady state picture.

Fig. 7 load transient response figure.

Fig. 8 supply voltage transient response figure.

Embodiment

Fig. 2 is the integrated stand composition of switching capacity.The MP pipe is that the PMOS current limiting tube is managed corresponding to the MP among Fig. 1.The present invention obtains switched capacitor network zero pole distribution by the small-signal modeling to switched capacitor network, and dominant pole P1 is the amount relevant with load RL, and it is worth at 13HZ (Ilload=1mA), 2.5KHZ (Iload=200mA).P2, Z1 about about identical position 100KHZ, can think that one zero limit is right greatly, can ignore the influence of system.Z2 is the 3.3MHZ place at zero point of a high frequency.

After the feedback control loop that does not have compensation being done modeling and being analyzed, as shown in Figure 3, find that unity gain bandwidth GBW has only 2.5KHZ, and the direct voltage gain has only the so little GBW of 31dB. not only can't effectively reduce the noise of transducer, and response speed can be affected also.The not high meeting of direct voltage causes output voltage accuracy not high, also can reduce the line regulation and the load regulation of transducer.In order to overcome the above problems, the compensating circuit that this paper proposes as shown in Figure 1, adds a limit at low frequency 0HZ place, to guarantee enough DC current gain.Near dominant pole P1, insert a zero point-1/R1C1, to offset the influence of dominant pole to the system phase remaining.

（1）

So not only the direct voltage of loop gains to more than the 80dB, and loop GBW is arranged on (switching frequency is 500KHZ) about 100KHZ.Phase margin is above PH=72 °.Therefore not only guarantee the stability of system, and satisfied noise, response speed, the requirement of output voltage accuracy.

Fig. 4 is the loop small-signal analysis figure that adds after compensating.Can see having in the whole loading range to surpass 71 ° phase margin.And DC current gain is very big, by the gain decision of error amplifier.Unity gain bandwidth also meets the set point of expection.

In the analysis in front, we know that switched capacitor network introduced a dominant pole P1 relevant with load.In fact, input voltage source transistor MP will be operated in the saturation region, for the saturation voltage drop that reduces it to improve system effectiveness, the size of MP pipe is very large usually, the size that adopts in the design of this paper is 50000u/0.5u.So big size must be introduced a low-frequency pole at MP pipe grid end, and two dominant poles will appear in circuit so.And the compensation method that 1 part is mentioned only allows the limit of a low frequency, and so this compensation method will be lost efficacy.In order to guarantee the dominant pole of a low frequency, the limit that MP official introduces must be shifted onto enough far, normally outside 5 times the unity gain bandwidth.In the compensating circuit that this paper proposes, as shown in Figure 1, the output of source follower M3 is received the grid end of MP.Be easy to like this guarantee:

Figure 201010611340X100002DEST_PATH_IMAGE004

（2）

Introduce second low-frequency pole thereby eliminated.

In addition in order to guarantee that error amplifier Erramp has less output resistance, also will guarantee enough gains.Error amplifier adopts the dual-stage amplifier structure, as shown in Figure 5.

In addition, because the MP pipe is the PMOS transistor, be negative feedback in order to guarantee whole loop.The phase place of output voltage V out must be consistent with MP gate voltage phase place.Therefore add two metal-oxide-semiconductor M1, M2 has managed the unit gain inverter functionality.

The flow test result

In order to verify this compensating circuit real work effect, this paper adopts Chartered 0.35 μ m 2P4M 5V/3.3V CMOS technology to carry out flow and test.

For observing system after powering on stable case and observe the inhibition ability of loop bandwidth to the ripple of output voltage.Having tested at supply voltage is 4.2V, the output steady state voltage when load current is 100mA, as shown in Figure 6.Can see that the back output voltage that powers on can be stabilized in 1.8V.And by adopting the input Current limited Control, other circuit control of loop bandwidth and some is set rationally, output voltage ripple is only about 3mV.

Fig. 7 has provided load current transient response figure during saltus step between 10mA and the 100mA.Can see that the compensator that this paper proposes can respond fast and can reach stable state when load changing.Under the output voltage towards about the 100mV, about upper punch 70mV.Because the loop DC current gain of this compensator is very big, the output voltage variable quantity of system after reaching stable state behind the load changing is minimum, and load regulation is 0.0027%/mA.Fig. 8 is the transient response figure of supply voltage sudden change, can see for the perturbed system of input voltage can stablize and stable after the output voltage variable quantity very little, line regulation is 3.76mV/V.

Can see that the frequency compensated circuit based on input current-limiting type switching capacity DC/DC transducer that this paper proposes can make system in 0 ~ 200mA load current range, can steady operation, and have load regulation and line regulation preferably.

Claims

1. a frequency compensated circuit that is applicable to the switching capacity dc voltage changer is characterized in that: comprise an error amplifier, electric capacity in two sheets, resistance in the sheet, a NMOS pipe, two PMOS pipes, a current source; Wherein,

The dividing point of resistance (R1) back in parallel one termination output voltage or output voltage in first electric capacity (C1) and the sheet, the inverting input of another termination error amplifier (Erramp); The normal phase input end of error amplifier (Erramp) connects reference voltage, connects second electric capacity (C2) between its inverting input and the output; The grid end of error amplifier (Erramp) output termination NMOS pipe (M1), the source termination power of PMOS pipe (M2), the grid end with receive the drain terminal that NMOS manages (M1) after drain terminal is connected; NMOS pipe (M1) and PMOS pipe (M2) play the unit gain inverter functionality; Current source of the 2nd PMOS pipe (M3) source termination, drain terminal ground connection, the drain terminal of grid termination NMOS pipe (M1);

Wherein, resistance (R1), interior first electric capacity (C1) of sheet, second electric capacity (C2) and an error amplifier (Erramp) are in turn connected into loop in the sheet, the pole and zero of a low frequency is provided, is used in the compensation loop original dominant pole and improve the direct voltage gain; By the unit gain inverter functionality of NMOS pipe (M1), PMOS pipe (M2) realization small-signal, be negative feedback to guarantee loop; Current source and the 2nd PMOS pipe (M3) adopt the structure of source follower, and the low-frequency pole that will import the introducing of current limiting tube (MP) grid is pushed into high frequency, to satisfy the requirement of unity gain bandwidth GBW and phase margin.