CN113381589A - Power supply device and pulse frequency modulation method - Google Patents
Power supply device and pulse frequency modulation method Download PDFInfo
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- CN113381589A CN113381589A CN202010116302.0A CN202010116302A CN113381589A CN 113381589 A CN113381589 A CN 113381589A CN 202010116302 A CN202010116302 A CN 202010116302A CN 113381589 A CN113381589 A CN 113381589A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
Abstract
The power supply device comprises a pulse frequency modulation controller circuit system and a period controller circuit system. The pulse frequency modulation controller circuit system is used for adjusting the change speed of the first signal according to at least one control bit, comparing the first signal with a first reference voltage to generate a second signal, and generating a driving signal according to the output voltage, the second reference voltage and the second signal to a power conversion circuit, wherein the power conversion circuit is used for generating the output voltage according to the driving signal. The period controller circuit system is used for detecting the frequency of the driving signal according to a clock pulse signal with a preset frequency to adjust at least one control bit, wherein the preset frequency is set based on the auditory frequency range of a human ear.
Description
Technical Field
The present disclosure relates to a power supply device, and more particularly, to a power supply device with a pulse frequency modulation mechanism and a modulation method thereof.
Background
Power supply devices are commonly used in various electronic devices to provide stable supply voltage to internal circuits of the electronic devices. In electronic devices for audio-visual applications (e.g., mobile phones, wireless headsets, wireless speakers, etc.). In practical applications, noise may be generated by switching operations in the power supply apparatus. As such, the user may hear these noises while using the electronic device, resulting in a poor user experience.
Disclosure of Invention
In some embodiments, the power supply includes pulse frequency modulation controller circuitry and period controller circuitry. The pulse frequency modulation controller circuit system is used for adjusting the change speed of the first signal according to at least one control bit, comparing the first signal with a first reference voltage to generate a second signal, and generating a driving signal according to the output voltage, the second reference voltage and the second signal to a power conversion circuit, wherein the power conversion circuit is used for generating the output voltage according to the driving signal. The period controller circuit system is used for detecting the frequency of the driving signal according to a clock pulse signal with a preset frequency to adjust at least one control bit, wherein the preset frequency is set based on the auditory frequency range of a human ear.
In some embodiments, the pulse frequency modulation method comprises the operations of: adjusting the change speed of the first signal according to at least one control bit, and comparing the first signal with a first reference voltage to generate a second signal; generating a driving signal to a power conversion circuit according to the output voltage, a second reference voltage and a second signal, wherein the power conversion circuit is used for generating the output voltage according to the driving signal; and detecting a frequency of the driving signal according to a clock pulse signal having a preset frequency to adjust at least one control bit, wherein the preset frequency is set based on a human auditory frequency range.
The features, implementations and functions of the present invention will be described in detail with reference to the drawings.
Drawings
Fig. 1 is a schematic diagram illustrating a power supply apparatus according to some embodiments of the disclosure;
fig. 2A is a schematic diagram illustrating Pulse Frequency Modulation (PFM) controller circuitry of fig. 1 according to some embodiments herein;
fig. 2B is a schematic diagram illustrating the PFM controller circuitry of fig. 1 according to some embodiments of the present disclosure;
FIG. 3 illustrates waveforms of the signals of FIG. 2A (or FIG. 2B) according to some embodiments of the disclosure;
FIG. 4 is a flow diagram illustrating operation of the cycle controller circuitry of FIG. 1 according to some embodiments of the present disclosure;
FIG. 5A is a schematic diagram illustrating waveforms of portions of signals in FIG. 1 according to some embodiments of the present disclosure;
FIG. 5B is a waveform illustrating a portion of the signals of FIG. 1 according to some embodiments of the present disclosure; and
fig. 6 is a flow chart illustrating a PFM method according to some embodiments of the present disclosure.
Detailed Description
All words used herein have their ordinary meaning. The definitions of the above-mentioned words in commonly used dictionaries are provided, and any use of the words discussed herein in this document is by way of illustration only and should not be construed as limiting the scope and meaning of the present disclosure. Likewise, the present disclosure is not limited to the various embodiments shown in this specification.
As used herein, the term "couple" or "connect" refers to two or more elements being in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or the two or more elements operating or acting together. As used herein, the term "circuitry" may be a single system formed by at least one circuit (circuit), and the term "circuitry" may be a device connected by at least one transistor and/or at least one active and passive component in a manner to process a signal.
As used herein, the term "and/or" includes any combination of one or more of the associated listed items. The terms first, second, third and the like are used herein to describe and distinguish between various components. Thus, a first component may also be referred to herein as a second component without departing from the spirit of the disclosure. For ease of understanding, similar components in the various drawings will be designated with the same reference numerals.
Fig. 1 is a schematic diagram illustrating a power supply apparatus 100 according to some embodiments of the disclosure. In some embodiments, the power supply device 100 can be applied to various types of electronic devices (e.g., mobile phones, wireless headsets, bluetooth speakers, etc.). The power supply device 100 can prevent the frequency of the internal electronic signal from falling into the range of human auditory frequency (the frequency is about 20 to 20 kilohertz (kHZ)), so as to prevent the noise of the electronic device from affecting the auditory perception of the user.
The power supply apparatus 100 includes a power conversion circuit 110, a period controller circuitry 120, and a Pulse Frequency Modulation (PFM) controller circuitry 130. The power conversion circuit 110 is driven by the driving signal SDWill voltage VCCIs converted into an output voltage SO. The power conversion circuit 110 includes a buffer 111, a buffer 112, a transistor TP, a transistor TN, an inductor L, and a capacitor C. The transistor TP receives the driving signal S via the buffer 111D. The transistor TN receives the driving signal S via the buffer 112D. The transistor TP is a P-type transistor according to the driving signal SDConducting to charge the capacitor C via the inductor L. Thus, the output voltage SOWill rise. The transistor TN is an N-type transistor which is driven by the driving signal SDConducting to discharge the capacitor C via the inductor L. Thus, the output voltage SOWill drop. The above-mentioned arrangement of the power conversion circuit 110 is used for example, and the present disclosure is not limited thereto. For example, in alternative embodiments, buffer 111 and/or buffer 112 may not be provided. In other words, the transistor TP and/or the transistor TN can directly receive the driving signal SD。
The period controller circuitry 120 has a predetermined frequency (e.g., F in FIG. 5A)CLK) Clock pulse signal SCLKDetecting the drive signal SDTo adjust at least one control bit BI. In some embodiments, the clock pulse signal SCLKIs set based on the range of human auditory frequencies. For example, the predetermined frequency may be set to 32kHZ, which is higher than the highest frequency of the human auditory frequency range, but the present invention is not limited thereto. As will be described later, the period controller circuitry 120 may adjust at least one control bit BI to avoid the driving signal SDFalls within the human auditory frequency range. PFM controller circuitry 130 is based on at least one control bitBI. Reference voltage SREF1Reference voltage SREF2And an output voltage SOGenerating a drive signal SD。
Fig. 2A is a schematic diagram illustrating the PFM controller circuitry 130 of fig. 1 according to some embodiments of the present disclosure. In some embodiments, PFM controller circuitry 130 adjusts signal S on node N1 according to at least one control bit BI1And comparing the signal S1And a reference voltage SREF1To generate a signal S2. The PFM controller circuitry 130 also outputs the voltage S according to the output voltageOReference voltage SREF2And signal S2Generating a drive signal SD。
For ease of illustration, FIG. 2A illustrates an example where at least one control bit BI includes 4 control bits B [0] to B [3 ]. It should be understood that the number of bits in the at least one control bit BI is not limited thereto. PFM controller circuitry 130 includes switched capacitor array circuit 210, switch SW1, current source circuit 215, switch SW2, comparator circuit 220, and inverter circuit 230. Switched capacitor array circuit 210 determines the capacitance of node N1 based on control bits B [0] to B [3 ]. For example, the switched capacitor array circuit 210 includes a plurality of capacitors CU and a plurality of switches SWU. The first terminals of the capacitors CU are coupled to ground. Each of the plurality of switches SWU is coupled between a second terminal of a corresponding one of the plurality of capacitors CU and the node N1 and is turned on according to a corresponding one of the plurality of control bits B [0] B [3 ]. As the number of on switches in the plurality of switches SWU increases, the number of capacitors CU that can be connected in parallel with each other increases. Thus, the higher the capacitance value of node N1. Alternatively, the smaller the number of on switches among the plurality of switches SWU, the smaller the number of capacitors CU that can be connected in parallel with each other. Thus, the lower the capacitance value of node N1.
The above-mentioned arrangement of the switched capacitor array circuit 210 and the number of components (e.g., the switch SWU and the capacitor CU) are only for example and the disclosure is not limited thereto. The number of components in the switched capacitor array circuit 210 may be one or more according to actual requirements.
The current source circuit 215 provides a current signal SI. Switch SW1 coupled to powerBetween the current source circuit 215 and the node N1 according to the enable signal SENIs conducted to transmit the current signal SITo node N1 to charge node N1 to generate signal S1. The higher the capacitance of the node N1, the longer the charging time, so the signal S1The speed of change of (c) becomes slow. Alternatively, the lower the capacitance of node N1, the shorter the charging time, so signal S1The change speed of (2) becomes fast.
The switch SW2 is driven by the driving signal SDSelectively turned on to reset the potential of node N1. In this example, switch SW2 may be implemented as an N-type transistor. Comparator circuit 220 compares reference voltage SREF1And signal S1To generate a signal S3. The inverter circuit 230 is based on the signal S3Generating a signal S2。
Fig. 2B is a schematic diagram illustrating the PFM controller circuitry 130 of fig. 1 according to some embodiments of the present disclosure. Compared to fig. 2A, in this example, the SR latch circuit 250 includes a NAND gate (NAND) circuit G3, a NAND gate circuit G4, and an inverter circuit 252. In other words, in some embodiments, the SR latch circuit 250 may be implemented by a NOR circuit (i.e., FIG. 2A). Alternatively, in some embodiments, the SR latch circuit 250 may also be implemented by a NAND circuit (i.e., fig. 2B).
Fig. 3 is a schematic diagram illustrating waveforms of signals in fig. 2A (or fig. 2B) according to some embodiments of the present disclosure. For easy understanding of the operation of the power supply apparatus 100 of fig. 1, please refer to fig. 1, fig. 2A (or fig. 2B) and fig. 3 together. During the time period T1, the driving signal SDHaving a logical value 1 (i.e. the drive signal S)DElectricity (D) fromFlat high level) and enable signal SENHaving a logic value 0 (i.e. enable signal S)ENIs low). In response to this drive signal SDSwitch TP is turned off and switch TN is turned on. In this way, the capacitor C is discharged via the switch TN, so that the output voltage S isOAnd decreases.
At time t0When outputting the voltage SOLower than (or equal to) reference voltage SREF2The comparator circuit 240 outputs a set signal S having a logic value 1SET. In response to this setting signal SSETAnd signal S having logic value 02The SR latch circuit 250 outputs an enable signal S having a logic value 1EN. Thus, the inverter circuit 260 outputs the driving signal S having a logic value 0D. In response to this drive signal SDSwitch TP is turned on and switch TN is turned off. Under this condition, the capacitor C is charged via the switch TP, so that the output voltage S isOAnd (4) rising. When outputting the voltage SOHigher than the reference voltage SREF2The comparator circuit 240 outputs a set signal S having a logic value 0SET. In addition, in response to the enable signal S having a logic value 1ENThe switch SW1 is turned on, so that the node N1 is controlled by the current signal SIAnd (6) charging. Thus, the signal S1Begins to rise in level.
At time t1, when signal S1Higher than (or equal to) the reference voltage SREF1The comparator circuit 220 outputs a signal S having a logic value 03. In response to this signal S3And a set signal S having a logic value 0SETThe inverter circuit 230 outputs a signal S having a logic value 12. In response to this signal S2And has a logic value setting signal SSETThe SR latch circuit 250 outputs an enable signal S having a logic value 0EN. Thus, the inverter circuit 260 outputs the driving signal S having a logic value 1D. In response to this drive signal SDSwitch TP is turned off and switch TN is turned on. Accordingly, the capacitor C is discharged through the switch TN to make the output voltage SOAnd decreases. By analogy, the power conversion circuit 110 can be controlled by the PFM controller circuitry 130 according to the driving signalNumber SDRegulating the output voltage SO。
Through the above operation, the capacitance value of the node N1 can be changed to adjust the driving signal SDConstant on-time (T)COT. For example, if the capacitance of the node N1 becomes small, the signal S1The change speed of (2) becomes fast. Under this condition, the signal S1 is earlier than the time t1Time t of2Higher than (or equal to) the reference voltage SREF1. Accordingly, the inverter circuit 230 is at time t2Outputting a signal S having a logic value 12Thereby allowing the inverter circuit 260 to more quickly output the driving signal S having a logic value 1D. Alternatively, if the capacitance value of the node N1 becomes large, the signal S1The speed of change of (c) becomes slow. Under this condition, the signal S1Will be later than time t1Time t of3Higher than (or equal to) the reference voltage SREF1. Accordingly, the inverter circuit 230 is at time t3Outputting a signal S having a logic value 12Thereby causing the inverter circuit 260 to output the driving signal S having a logic value 1 more slowlyD。
Fig. 4 is a flow diagram illustrating operation of the cycle controller circuitry 120 of fig. 1 according to some embodiments of the present disclosure. As previously described, the cycle controller circuitry 120 may be based on the clock pulse signal SCLKDetecting the drive signal SDTo adjust at least one control bit BI. In some embodiments, as previously shown in FIG. 1, the cycle controller circuitry 120 includes a counter circuit 122 and a control logic circuit 124. The counter circuit 122 is based on the clock pulse signal SCLKIs reset to the drive signal SDCount the number of pulses to generate a count value SCO. In some embodiments, the counter circuit 122 may be an up counter. The control logic circuit 124 is based on the count value SCOThe operations of fig. 4 are performed to adjust at least one control bit BI. In some embodiments, the control logic 124 may be implemented by one or more digital circuits configured to be implemented with a state machine that performs the operations of FIG. 4. The above-described arrangement of the cycle controller circuitry 120 is for illustration and this disclosure is for the purpose of exampleAnd is not limited thereto.
In operation S410, at least one control bit BI is set to a preset value. For example, the control logic 124 may include a register (not shown) storing a default value of at least one control bit BI. In this operation, the control logic 124 may output at least one control bit BI having a predetermined value through the register. Taking FIG. 2A as an example, the default values of the control bits B [0] to B [3] can be "0111". In response to this preset value, the 3 capacitors CU in the switched capacitor array circuit 210 may be connected in parallel with each other.
In operation S420, the clock pulse signal S is determinedCLKWithin one period of (c), count value SCOWhether or not it is 0. If the count value SCOTo 0, at least one control bit BI is adjusted to speed up the signal S1The rate of change of (c). If the count value SCOAnd if not, maintaining at least one control bit BI as a preset value.
For ease of understanding, please refer to fig. 5A, fig. 5A is a waveform diagram illustrating a portion of signals in fig. 1 according to some embodiments of the disclosure. In FIG. 5A, a clock pulse signal SCLKIs preset frequency FCLKSet to 32kHz, clock pulse signal SCLKIs set to 1/FCLKAnd the current IL is the current flowing through the inductor L.
In the 1 st period P1, the counter circuit 122 is triggered to counter the driving signal SDIs counted, and a plurality of control bits B [0]]～B[3]Is set to a preset value (i.e., operation S410). If in the 1 st period P1 at least one drive signal S is presentDPulse (i.e. count value S)COAt least 1). In this case, the representative drive signal SDIs higher than the frequency FCLKTherefore, it will not fall into the auditory frequency range of human ears. Accordingly, control logic 124 maintains a plurality of control bits B [0]]～B[3]Is a preset value.
Alternatively, if the driving signal S does not appear in the 1 st period P1DPulse (i.e. count value S)COIs 0). In this case, the representative drive signal SDIs lower than the frequency FCLKAnd may fall within the human auditory frequency range. Accordingly, the control logicCircuit 124 adjusts a plurality of control bits B [0]]～B[3](e.g., a plurality of control bits B [0]]～B[3]Switched to "0000") to make the switched capacitor array circuit 210 provide a lower capacitance value to speed up the signal S1The rate of change of (c). Thus, the driving signal S can be increasedDTo avoid falling into the auditory range of the human ear.
With continued reference to FIG. 4, in operation S430, it is determined that the clock signal S is presentCLKIn the next cycle of (2), count value SCOWhether it is greater than or equal to a preset value. If the count value SCOGreater than or equal to a predetermined value, adjusting at least one control bit BI to reduce the signal S1The rate of change of (c). If the count value SCOAnd maintaining the value of at least one control bit BI if the value is less than the preset value.
Referring to fig. 5A, if the driving signal S is in the 2 nd period P2DThe number of pulses is smaller than a predetermined value (e.g., 16/32/48/62, etc.), which indicates that the power conversion circuit 110 is operating under a light load. Accordingly, control logic 124 maintains a plurality of control bits B [0]]～B[3]The numerical value of (c).
Alternatively, in the 2 nd period P2, the driving signal SDThe number of pulses is greater than or equal to the predetermined value, which represents that the power conversion circuit 110 is operated under heavy load. Accordingly, the control logic 124 adjusts the plurality of control bits B [0] in the next cycle (i.e., the 3 rd cycle P3)]～B[3](e.g., a plurality of control bits B [0]]～B[3]Switch to a preset value). Thus, the switched capacitor array circuit 210 can provide a higher capacitance value to reduce the variation speed of the signal S1. By the arrangement, the driving signal S can be avoidedDIs too high to maintain the load current capability of the power conversion circuit 110 under heavy load.
In some embodiments, if in the next cycle, the driving signal SDThe number of pulses is still greater than the predetermined value, which indicates that the power conversion circuit 110 is still operating under heavy load. Accordingly, the control logic 124 may further adjust the plurality of control bits B [0]]～B[3](e.g., a plurality of control bits B [0]]～B[3]Switch to "1111"). Thus, the switched capacitor array circuit 210 can provide a higher capacitance to reduce the signal S1The rate of change of (c). Such asAs shown in FIG. 4, the operations S420 to S430 can be understood as 3 states ST1 to ST 3. At state ST1, a plurality of control bits B [0]]～B[3]With a preset value of "0111", which corresponds to a second highest capacitance value. At state ST2, a plurality of control bits B [0]]～B[3]The value of "000" corresponds to the lowest capacitance value. At state ST3, a plurality of control bits B [0]]～B[3]The value of (d) is "1111". Based on the load condition and the auditory frequency range of human ear, the control logic circuit 124 can refer to these 3 states to sequentially adjust the control bits B [0]]～B[3]。
The number of states described above is merely exemplary and the present disclosure is not limited thereto. The number of states, the predetermined number, and/or the number of elements of the switched capacitor array circuit 210 may be adjusted accordingly according to the actual design requirements. For example, in some embodiments, the switched capacitor array circuit 210 may include a plurality of smaller capacitors (not shown) for trimming the capacitance provided by the switched capacitor array circuit 210 according to additional bits of the at least one control bit BI.
Fig. 5B is a waveform diagram illustrating a portion of signals in fig. 1 according to some embodiments of the present disclosure. Compared to FIG. 5A, in this example, if in the 2 nd period P2, the driving signal SDThe number of pulses is greater than or equal to the predetermined value, the control logic circuit 124 immediately adjusts the plurality of control bits B [0] in the current cycle]～B[3](e.g., a plurality of control bits B [0]]～B[3]Switch to a preset value). In this way, a large current can be supplied in real time in response to the demand of a high load.
Fig. 6 is a flow diagram illustrating a PFM method 600 according to some embodiments of the present disclosure. In operation S610, the signal S is adjusted according to at least one control bit BI1And comparing the signal S1And a reference voltage SREF1To generate a signal S2. In operation S620, according to the output voltage SOReference voltage SREF2And signal S2Generating a drive signal SDTo the power conversion circuit 110. In operation S630, according to the preset frequency FCLKClock pulse signal SCLKDetecting the drive signal SDTo adjust at least one control bit BI, wherein a frequency F is presetCLKIs based on human ear hearingThe frequency range is set.
The above description of the operations can refer to the above embodiments, and therefore, the description thereof is omitted. The operations of the PFM method 600 described above are merely examples and need not be performed in the order of execution in this example. Various operations under the PFM method 600 should be added, replaced, omitted, or performed in a different order as appropriate, without departing from the manner and scope of operation of embodiments herein. Alternatively, one or more operations under the PFM method 600 may be performed simultaneously or partially simultaneously.
In summary, the power supply apparatus and the PFM method in some embodiments of the disclosure can prevent the switching frequency from falling into the hearing range of human ears, thereby improving the hearing feeling of the user.
Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can apply variations to the technical features of the present invention according to the contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.
Description of reference numerals:
100: power supply device
110: power supply conversion circuit
111. 112, 112: buffer device
120: cycle controller circuitry
122: counter circuit
124: control logic circuit
130: pulse Frequency Modulation (PFM) controller circuitry
BI: at least one control bit
C: capacitor with a capacitor element
L: inductance
SCLK: clock pulse signal
SCO: count value
SD: drive signal
SO: output voltage
SREF1、SREF2: reference voltage
TN and TP: transistor with a metal gate electrode
VCC: voltage of
210: switched capacitor array circuit
215: current source circuit
220. 240: comparator circuit
230. 260: inverter circuit
250: SR latch circuit
B < 0 >, B < 1 >, B < 2 >, B < 3 >: at least one control bit
CU: capacitor with a capacitor element
G1, G2: NOR gate circuit
N1: node point
S1、S2、S3: signal
SEN: enable signal
SI: current signal
SSET: setting signal
SW1, SW2, SWU: switch with a switch body
252: inverter circuit
G3, G4: NAND gate circuit
T1: time period
t0、t1、t2、t3: time of day
TCOT: constant on-time
S410, S420 and S430: operation of
ST1, ST2, ST 3: status of state
FCLK: preset frequency
P1, P2, P3: period of time
IL: electric current
600: PFM method
S610, S620, S630: operation of
Claims (10)
1. A power supply device comprising:
the pulse frequency modulation controller circuit system is used for adjusting the change speed of a first signal according to at least one control bit, comparing the first signal with a first reference voltage to generate a second signal, and generating a driving signal to a power supply conversion circuit according to an output voltage, the second reference voltage and the second signal, wherein the power supply conversion circuit is used for generating the output voltage according to the driving signal; and
and the period controller circuit system is used for detecting the frequency of the driving signal according to a clock pulse signal with a preset frequency to adjust the at least one control bit, wherein the preset frequency is set based on the auditory frequency range of the human ear.
2. The power supply device according to claim 1, wherein the period controller circuitry is configured to adjust the at least one control bit to avoid the frequency of the drive signal falling within the human auditory frequency range.
3. The power supply apparatus of claim 1, wherein the pulse frequency modulation controller circuitry comprises:
a switched capacitor array circuit for determining a capacitance value of a node according to the at least one control bit;
a first switch, configured to be turned on according to an enable signal to output a current signal, so as to charge the node to generate the first signal;
a second switch selectively turned on according to the driving signal to reset a potential of the node;
a comparator circuit for comparing the first reference voltage with the first signal to generate a third signal; and
the inverter circuit is used for generating the second signal according to the third signal.
4. The power supply device according to claim 3, wherein the switched capacitor array circuit comprises:
at least one capacitor; and
at least one third switch coupled between the at least one capacitor and the node, wherein each of the at least one third switch is configured to turn on according to a corresponding control bit of the at least one control bit.
5. The power supply apparatus of claim 1, wherein the pulse frequency modulation controller circuitry comprises:
a comparator circuit for comparing the output voltage with the second reference voltage to generate a set signal;
the SR latch circuit is used for generating an enable signal according to the setting signal and the second signal; and
the inverter circuit is used for generating the driving signal according to the enabling signal.
6. The power supply apparatus according to claim 1, wherein the period controller circuitry is configured to count a number of pulses of the driving signal in one period of the clock pulse signal to generate a count value, and to adjust the at least one control bit according to the count value.
7. The power supply apparatus according to claim 6, wherein the period controller circuitry is configured to adjust the at least one control bit to increase the variation speed of the first signal if the count value is 0.
8. The power supply apparatus according to claim 6, wherein the period controller circuitry is configured to adjust the at least one control bit at the period or a next period of the clock signal to reduce the change speed of the first signal if the count value is greater than or equal to a predetermined value.
9. The power supply device according to claim 1, wherein the preset frequency is higher than a highest frequency in the human auditory frequency range.
10. A method of pulse frequency modulation, comprising:
adjusting the change speed of a first signal according to at least one control bit, and comparing the first signal with a first reference voltage to generate a second signal;
generating a driving signal to a power conversion circuit according to an output voltage, a second reference voltage and the second signal, wherein the power conversion circuit is used for generating the output voltage according to the driving signal; and
detecting a frequency of the driving signal according to a clock pulse signal having a preset frequency to adjust the at least one control bit, wherein the preset frequency is set based on a human auditory frequency range.
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| CN1621988A (en) * | 2003-11-26 | 2005-06-01 | 圆创科技股份有限公司 | Pulse-frequency modulation type voltage regulator capable of extending least OFF time |
| US20050258811A1 (en) * | 2004-04-27 | 2005-11-24 | Masahiro Matsuo | Switching regulator and method for changing output voltages thereof |
| CN1783681A (en) * | 2004-12-01 | 2006-06-07 | 崇贸科技股份有限公司 | Suitching type controller |
| CN1937378A (en) * | 2005-08-12 | 2007-03-28 | 英飞凌科技股份公司 | Method and apparatus for switching on a voltage supply of a semiconductor circuit and corresponding semiconductor circuit |
| CN101771404A (en) * | 2010-01-08 | 2010-07-07 | 北京巨数数字技术开发有限公司 | LED control chip |
| CN102104331A (en) * | 2010-12-29 | 2011-06-22 | 复旦大学 | Frequency compensating circuit suitable for switched-capacitor direct-current voltage converter |
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