CN218387309U

CN218387309U - Self-adaptive on-time control circuit, power converter, chip and electronic equipment

Info

Publication number: CN218387309U
Application number: CN202222348915.4U
Authority: CN
Inventors: 王程左; 江佳; 容浚源
Original assignee: Shenzhen Goodix Technology Co Ltd
Current assignee: Shenzhen Goodix Technology Co Ltd
Priority date: 2022-09-02
Filing date: 2022-09-02
Publication date: 2023-01-24
Anticipated expiration: 2032-09-02

Abstract

The self-adaptive on-time control circuit comprises a load detection circuit, an on-time generation circuit, a first comparator and a pulse generator, wherein the load detection circuit is used for receiving the output voltage and the reference voltage of the switch circuit and outputting a voltage difference mean value; the conduction time generating circuit is used for receiving the voltage difference mean value and generating a conduction time signal, and the conduction time signal is used for controlling the conduction time of a transistor in the switch circuit; the first comparator is used for receiving the output voltage and the reference voltage of the switch circuit and outputting a first comparison signal; the pulse generator is used for receiving the first comparison signal and the conducting time signal and outputting a control pulse signal, and the control pulse signal is used for controlling the conduction and the disconnection of at least one transistor in the switch circuit. The self-adaptive on-time control circuit can self-adaptively adjust the on-time according to the load size, so that the ripple frequency of the output voltage of the circuit is large enough, and the load capacity of the circuit can be improved.

Description

Self-adaptive on-time control circuit, power converter, chip and electronic equipment

Technical Field

The present application relates to the field of power control technologies, and more particularly, to an adaptive on-time control circuit, a power converter, a chip, and an electronic device.

Background

In a bluetooth SoC chip for controlling a real Wireless Stereo (TWS) headset, a power management module, a radio frequency bluetooth module, and an audio decoding module are generally integrated. The power supply quality of the audio decoding module is one of the key factors influencing the sound quality performance of the earphone. The frequency range of signals audible to the human ear is typically 20-20kHz, which requires that the power supply of the audio decoder has a low noise component in the 20kHz range. Secondly, for portable applications such as headsets, there is also a need to reduce power consumption and extend standby time.

The conventional audio power supply is generally implemented by a Pulse Width Modulation (PWM) control mode DC-DC buck in combination with a Low Dropout Regulator (LDO) for voltage stabilization. PWM control can push the ripple frequency of the output voltage well above 20kHz by setting the switching frequency directly, and the LDO is used to further reduce the noise component in the audio band. The PWM control mode DC-DC has the disadvantage of low efficiency under light load, so that the power consumption is large when the music is paused, which is not beneficial to extending the stand-by time of the earphone.

Compared with a PWM control mode, a traditional Constant On-time (COT) control mode has the advantages of fast transient response and simple structure, so that the basic power consumption of a circuit is very low, but the ripple frequency of the output voltage of the circuit changes along with the size of a load. If the on-time is set to be small to ensure that the frequency of the output voltage ripple wave in the full music load range is far higher than 20kHz, the maximum loading capacity is limited; if the on-time is set to be large to improve the loading capability, the ripple frequency of the output voltage enters the audio band when the music load is small.

Therefore, how to adaptively adjust the on-time according to the load size makes the ripple frequency of the output voltage of the circuit sufficiently large, and at the same time, the on-load capability of the circuit can be improved is a technical problem to be solved urgently.

SUMMERY OF THE UTILITY MODEL

In a first aspect of the embodiments of the present application, a self-adaptive on-time control circuit is provided, where the self-adaptive on-time control circuit includes a load detection circuit, an on-time generation circuit, a first comparator, and a pulse generator; the load detection circuit is used for receiving the output voltage and the reference voltage of the switch circuit and outputting a voltage difference mean value; the on-time generation circuit is used for receiving the voltage difference mean value and generating an on-time signal, and the on-time signal is used for controlling the on-time of a transistor in the switch circuit; the first comparator is used for receiving the output voltage of the switch circuit and the reference voltage and outputting a first comparison signal; the pulse generator is configured to receive the first comparison signal and the on-time signal, and output a control pulse signal, where the control pulse signal is used to control on and off of at least one transistor in the switch circuit.

In one possible implementation, the load detection circuit includes a transconductance amplifier, a first amplifying resistor, and a low pass filter; the first amplifying resistor comprises a first end and a second end, the first end of the first amplifying resistor is coupled to the output end of the transconductance amplifier, and the second end of the first amplifying resistor is grounded; the transconductance amplifier comprises a positive phase input end, a negative phase input end and an output end, the positive phase input end of the transconductance amplifier receives the output voltage signal voltage, the negative phase input end of the transconductance amplifier receives the reference voltage signal voltage, and the output end of the transconductance amplifier is coupled to the first end of the first amplifying resistor and then outputs an amplified voltage; the low-pass filter comprises an input end and an output end, the input end of the low-pass filter is coupled with the output end of the transconductance amplifier and used for receiving the amplified voltage, and the output end of the low-pass filter outputs the voltage difference mean value.

In a possible embodiment, the low-pass filter has a turning frequency of less than 100kHz.

In one possible embodiment, the on-time generating circuit comprises an N-bit analog-to-digital converter; the N-bit analog-to-digital converter comprises an input end and an output end, the input end of the N-bit analog-to-digital converter is coupled with the output end of the low-pass filter and used for receiving the voltage difference mean value, and the output end of the N-bit analog-to-digital converter outputs an N-bit value.

In a possible implementation, the on-time generating circuit further includes an N-bit to M-bit encoder; the N-bit to M-bit encoder comprises an input end and an output end, the input end of the N-bit to M-bit encoder is coupled with the output end of the N-bit analog-to-digital converter and used for receiving an N-bit value, and the output end of the N-bit to M-bit encoder is coupled with the first input end of the pulse generator and used for outputting an M-bit value.

In one possible implementation, the N-bit value and the M-bit value are both binary numbers, and N and M are both positive integers greater than 1.

In one possible embodiment, the N-bit value is proportional to the magnitude of the mean voltage difference.

In one possible implementation, the M-bit value and the N-bit value are inversely proportional in size. In one possible implementation, when the number of bits of the N-bit value is the same as the number of bits of the M-bit value, the N-bit value is bitwise inverted to obtain the M-bit value.

A power converter according to a second aspect of the embodiments of the present application is characterized by comprising a switching circuit having a transistor and the adaptive on-time control circuit in the first aspect or any one of the possible implementations of the first aspect.

In one possible implementation, the power converter includes a local oscillator clock, and the time required for the local oscillator clock to count from 0 to the M-bit value is the on time.

In one possible embodiment, the switching circuit includes a driver, a first transistor, and a second transistor; the driver comprises a first input end, a first output end and a second output end, the first input end of the driver receives the control pulse signal, the first output end of the driver is connected with the grid electrode of the first transistor, and the second output end of the driver is connected with the grid electrode of the second transistor.

In one possible embodiment, the switching circuit further comprises a zero-crossing detection circuit comprising a second comparator; the positive phase input end of the second comparator is connected with the drain electrode of the first transistor and the drain electrode of the second transistor, and the negative phase input end of the second comparator is grounded; the output end of the second comparator outputs a second comparison signal, and the driver further comprises a second input end which receives the second comparison signal.

In a possible implementation, when the first comparison signal output by the first comparator is a positive value, the pulse generator outputs the control pulse signal; when the first input end of the driver receives the control pulse signal, the first output end of the driver outputs a first conduction signal to trigger the first transistor to be conducted, the first transistor is turned off after the conduction time, and then the second output end of the driver outputs a second conduction signal to start the second transistor to follow current.

In a possible embodiment, the driver keeps the second transistor turned on when the second comparison signal output by the second comparator is a negative value, and turns off the second transistor when the second comparison signal is a positive value.

In one possible embodiment, the switching circuit further comprises an inductor, a capacitor, a power supply, a load, a first feedback resistor, and a second feedback resistor;

the first end of the inductor is connected with the drains of the first transistor and the second transistor, the second end of the inductor is connected with the first end of the capacitor, and the second end of the capacitor is grounded; the positive electrode of the power supply is connected with the source electrode of the first transistor, and the negative electrode of the power supply is grounded; the first end of the load is connected with the first end of the capacitor, and the second end of the load is grounded; the first end of the first feedback resistor is connected with the first end of the load, the second end of the first feedback resistor is connected with the first end of the second feedback resistor, and the second end of the second feedback resistor is grounded.

A chip provided in a third aspect of embodiments of the present application includes an audio processing circuit and the power converter in the second aspect or any possible implementation manner of the second aspect, where the power converter supplies power to the audio processing circuit.

In a fourth aspect of the embodiments of the present application, an electronic device includes the chip in any one of the possible implementations of the third aspect or the third aspect, and the electronic device is a bluetooth headset or a bluetooth sound.

The embodiment of the application provides a self-adaptive turn-on time control circuit, which can detect the load size in real time and generate corresponding turn-on time according to the load size. When the load detection circuit detects that the difference value between the output voltage of the switch circuit and the reference voltage is larger, the conduction time generation circuit automatically reduces the conduction time, so that the switching frequency of the switch circuit is improved; when the load detection circuit detects that the difference value between the output voltage of the switch circuit and the reference voltage is small, the conduction time generation circuit automatically increases the conduction time, so that the load carrying capacity of the switch circuit is improved. The self-adaptive on-time control circuit introduces the load detection circuit and the on-time generation circuit, and optimizes the contradiction that the higher the load carrying capacity of the switch circuit in the traditional COT control mode is, the lower the ripple frequency is when the load is light.

The embodiment of the application further provides a power converter, which comprises a zero-crossing detection circuit besides the self-adaptive conduction time control circuit, so that the switching circuit can work in a discrete conduction mode within a full-load range, the energy loss under the condition of light load is reduced, and the light-load efficiency is improved.

The adaptive conduction time control circuit and the zero-crossing detection circuit in the power converter provided by the embodiment of the application realize the working modes of adaptive adjustment of conduction time and discrete conduction. Carry on power converter's chip can use on electronic equipment such as bluetooth headset and bluetooth stereo set, can reduce the noise component on the one hand, promotes tone quality performance, and on the other hand can also reduce the consumption, extension stand-by time.

Drawings

Fig. 1 is a schematic diagram of an adaptive on-time control circuit according to an embodiment of the present disclosure;

fig. 2 is a circuit diagram of a load detection circuit provided in an embodiment of the present application;

FIG. 3 is a circuit diagram of an on-time generator according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of an adaptive on-time adjustment process provided in an embodiment of the present application;

fig. 5 is a schematic structural diagram of a power converter according to an embodiment of the present application;

fig. 6 is a circuit diagram of a power converter according to an embodiment of the present application;

fig. 7 is a waveform diagram illustrating an operation of a power converter according to an embodiment of the present application;

fig. 8 is a circuit diagram of another power converter provided in an embodiment of the present application;

FIG. 9 is a waveform diagram of the operation of the power converter of FIG. 8;

fig. 10 is a waveform of ripple of an output voltage varying with load according to an embodiment of the present application

Fig. 11 is a waveform of ripple of an output voltage according to the on-time provided by the embodiment of the present application;

fig. 12 is an operating waveform diagram of a process of adaptively adjusting on-time according to an embodiment of the present application;

fig. 13 is a schematic structural diagram of a chip and an electronic device according to an embodiment of the present disclosure.

Detailed Description

The technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Furthermore, the terms "first," "second," and the like, are used solely to distinguish between similar objects and are not intended to indicate or imply relative importance or to implicitly indicate a number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature.

As shown in fig. 1, the present embodiment provides an adaptive on-time control circuit 22, where the adaptive on-time control circuit 22 includes a load detection circuit 221, an on-time generation circuit 222, a first comparator 223, and a pulse generator 224;

the load detection circuit 221 is configured to receive the output voltage of the switch circuit and the reference voltage, and output a voltage difference average value;

the on-time generating circuit 222 is configured to receive the voltage difference average value and generate an on-time signal, where the on-time signal is used to control the on-time of a transistor in the switch circuit;

the first comparator 223 is configured to receive the output voltage of the switching circuit and the reference voltage, and output a first comparison signal;

the pulse generator 224 is configured to receive the first comparison signal and the on-time signal, and output a control pulse signal, where the control pulse signal is used to control the on and off of at least one transistor in the switch circuit.

In the embodiment of the present application, the adaptive on-time control circuit 22 is introduced into the switch circuit, the adaptive on-time control circuit 22 is configured to control the switch circuit, the load detection circuit 221 can detect the load magnitude in real time, and the on-time generation circuit 222 can generate a control pulse signal with a corresponding on-time according to the load magnitude.

The load detection circuit 221, the on-time generation circuit 222, the first comparator 223 and the pulse generator 224 together form the adaptive on-time control circuit 22, so that the ripple frequency of the output voltage of the switching circuit is sufficiently large, the load carrying capacity of the switching circuit can be improved, and the contradiction between the higher the load carrying capacity of the switching circuit and the lower the ripple frequency in the light load in the conventional COT control mode is optimized.

As an alternative embodiment, referring to fig. 2, the load detection circuit 221 may include a transconductance amplifier 2211, a first amplifying resistor 2212 and a low-pass filter 2213, and is configured to receive the output voltage Vfb and the reference voltage Vref of the switching circuit and output the voltage difference average.

In this embodiment, the load detection circuit 221 determines the load of the switching circuit by detecting a difference between the output voltage Vfb of the switching circuit and the reference voltage Vref, and determines that the load of the switching circuit decreases when the difference between the output voltage Vfb of the switching circuit and the reference voltage Vref is increased. The load detection circuit 221 has a simple structure and is sensitive to detection, and the output voltage difference average value is convenient for the subsequent processing of the on-time generation circuit 222. In this embodiment, the first amplifying resistor 2212 may include a first terminal and a second terminal, the first terminal of the first amplifying resistor 2212 is coupled to the output terminal of the transconductance amplifier 2211, and the second terminal of the first amplifying resistor 2212 is grounded.

The transconductance amplifier 2211 may include a positive phase input terminal, a negative phase input terminal, and an output terminal, the positive phase input terminal of the transconductance amplifier 2211 receives the output voltage Vfb of the switching circuit, the negative phase input terminal of the transconductance amplifier 2211 receives the reference voltage Vref, and the output terminal of the transconductance amplifier 2211 is coupled to the first terminal of the first amplifying resistor and then outputs an amplified voltage.

In this embodiment, the transconductance amplifier 2211 and the first amplifying resistor 2212 jointly amplify the difference between the output voltage Vfb and the reference voltage Vref by a factor Gm × Ro, so as to obtain the amplified voltage. Where Gm is the transconductance gain of the transconductance amplifier 2211 and Ro is the resistance of the first amplifying resistor 2212.

The transconductance amplifier 2211 and the first amplifying resistor 2212 together provide an amplification factor to amplify the difference between the output voltage Vfb and the reference voltage Vref, so as to facilitate the subsequent processing of the on-time generating circuit 222. The transconductance amplifier 2211 and the first amplifying resistor 2212 are simple in structure, and the amplification factor is convenient to adjust.

In this embodiment, the low pass filter 2213 includes an input terminal and an output terminal, the input terminal of the low pass filter 2213 is coupled to the output terminal of the transconductance amplifier 2211 and receives the amplified voltage, and the output terminal of the low pass filter 2213 outputs the voltage difference average value. The low-pass filter 2213 can effectively weaken the influence of the ripple frequency change of the output voltage caused by the load change, thereby improving the detection precision of the difference value between the output voltage Vfb and the reference voltage Vref.

Generally, in order to prevent noise generated when the output voltage ripple frequency enters the audio band of 20Hz to 20kHz when the load of the switching circuit is small, the output voltage ripple frequency is greater than 20kHz in the full load range, and a better choice is to make the output voltage ripple frequency greater than 100kHz in the full load range.

As an alternative embodiment, the turning frequency of the low-pass filter 2213 can be set to be less than 100kHz. At the corner frequency, the low pass filter 2213 can have a good filtering effect in the full load range.

It is understood that in other embodiments, the load detection circuit 221 may have different implementations. In another embodiment, the load detection circuit 221 may determine the load size by detecting a switching frequency of the switching circuit, and may specifically detect a time interval between two times of turning on of a transistor in the switching circuit, and when detecting that the switching frequency of the switching circuit increases, determine that the load of the switching circuit increases. In yet another embodiment, the load detection circuit 221 may further determine the load size by detecting the load current of the switching circuit, and when the load current of the switching circuit is detected to increase, determine that the load of the switching circuit increases.

Different implementation modes of the load detection circuit 221 can adapt to different switch circuits, and the load detection circuit can also be combined to be used for the same switch circuit, so that the accuracy of load detection of the switch circuit and the effect of self-adaptive on-time control are improved.

As an alternative embodiment, referring to fig. 3, the on-time generating circuit 222 may include an N-bit adc 2221; the N-bit adc 2221 comprises an input terminal and an output terminal, the input terminal of the N-bit adc 2221 is coupled to the output terminal of the low pass filter 2213, receives the average voltage difference, and the output terminal of the N-bit adc 2221 outputs an N-bit value.

In this embodiment, the N-bit adc 2221 may convert the average value of the inputted voltage differences into an N-bit digital signal, that is, the N-bit value. The N-bit value is proportional to the voltage difference average, and the N-bit value output by the N-bit adc 2221 is larger when the voltage difference average is larger.

As an alternative embodiment, the input voltage range of the N-bit adc 2221 may be divided into 2^N intervals, i.e. 2 ^N And (4) each interval. And each input voltage interval may correspond to a different N-bit value.

Optionally, table 1 provides a specific embodiment of the input voltage interval division of the N-bit analog-to-digital converter 2221, where N is 3, and the maximum voltage value is 1.800V.

As shown in table 1, the input voltage range of the N-bit ADC 2221 is unevenly divided into 8 input voltage intervals, each input voltage interval has a corresponding N-bit value, the larger the input voltage interval is, the larger the corresponding N-bit value is, wherein the N-bit value is set as a 3-bit binary number, and the ADC represents the N-bit ADC 2221.

For example, when the average value of the voltage difference inputted to the ADC is 0.5V, the average value of the voltage difference of 0.5V is within the 1 st voltage interval [0.00v,0.650v ] of the ADC, and as can be obtained from table 1, the N-bit value of the output corresponding to the 1 st voltage interval of the ADC is 000. That is, in the embodiment shown in table 1, when the average voltage difference of the ADC input is 0.5V, the N-bit value of the ADC output will be 000.

TABLE 1

ADC input voltage interval	Value of voltage interval	N-bit value of ADC output

ADC 8 th voltage interval	[1.400V，1.800V]	111

ADC 7 th voltage interval	[1.275V，1.400V)	110

ADC 6 th voltage interval	[1.150V，1.275V)	101

ADC 5 th voltage interval	[1.025V，1.150V)	100

ADC 4 th voltage interval	[0.900V，1.025V)	011

ADC 3 rd voltage interval	[0.775V，0.900V)	010

ADC 2 nd voltage interval	[0.650V，0.775V)	001

ADC 1 st voltage interval	[0.00V，0.650V)	000

It should be noted that the division of the input voltage interval and the selection of the N-bit value of the N-bit analog-to-digital converter 2221 in the embodiment of the present application are not limited to the above specific values, and those skilled in the art may determine the specific values of each parameter according to the actual circuit design requirement.

Alternatively, in other embodiments, the input voltage range of the N-bit adc 2221 may be divided equally into 2^N input voltage intervals.

Alternatively, in other embodiments, the highest voltage value of the input voltage interval of the N-bit adc 2221 may be selected according to the power supply voltage value of the switch circuit. For example, when the power supply voltage of the switching circuit is a single fixed value of 3.3V, 3.3V can be used as the highest voltage value of the input voltage interval. However, when the power supply voltage of the switching circuit is in a converted voltage range of 3.3V to 4.3V, it is necessary to select an appropriate maximum voltage value of the input voltage interval according to actual requirements of circuit design.

The N-bit adc 2221 converts the average value of the analog signal voltage difference into a corresponding N-bit value of the digital signal by dividing the voltage interval, so that the adc rule can be adjusted according to the actual circuit requirement, which is very flexible, and the N-bit value can be further processed conveniently.

As an alternative embodiment, the on-time generating circuit 222 may further include an N-bit to M-bit encoder 2222; the N-to-M-bit encoder 2222 comprises an input terminal and an output terminal, the input terminal of the N-to-M-bit encoder 2222 is coupled to the output terminal of the N-to-analog converter 2221 for receiving the N-bit value, and the output terminal of the N-to-M-bit encoder 2222 is coupled to the first input terminal of the pulse generator 224 for outputting the M-bit value.

In this embodiment, the time required for the clock to count from 0 to the M value is the on time.

Alternatively, the clock may be a system clock, for example, when the adaptive on-time control circuit 22 is applied in a power converter, the system clock may be a local oscillator clock of the power converter.

In this embodiment, the M-bit value and the N-bit value are inversely proportional, and the smaller the N-bit value, the larger the M-bit value output by the N-to-M-bit encoder 2222.

Optionally, the N-bit value and the M-bit value are both binary numbers, and N and M are both positive integers greater than 1.

Optionally, when the number of bits of the N-bit value is the same as that of the M-bit value, the N-bit value may be inverted bitwise to obtain the M-bit value.

The N-bit to M-bit encoder 2222 can flexibly set up encoding rules, and, in combination with the N-bit analog-to-digital converter 2221, can be applied to different switching circuits and different usage scenarios of the same switching circuit.

In this embodiment, referring to fig. 4, when the smaller average voltage difference output by the load detection circuit 221 is in the lower input voltage interval of the ADC, it is determined that the difference between the output voltage Vfb of the switching circuit and the reference voltage Vref is smaller. The smaller voltage difference mean value is converted by the N-bit analog-to-digital converter 2221 to obtain a smaller N-bit value, and the N-bit value is in direct proportion to the voltage difference mean value. The smaller N-bit value is encoded by the N-to-M-bit encoder 2222 and then converted to a larger M-bit value, which is inversely proportional to the size of the N-bit value. The larger M-bit value may result in a larger on-time.

In a general view, when the load detection circuit 221 detects that the difference between the switching circuit output voltage Vfb and the reference voltage Vref is small, the on-time generation circuit 222 generates a larger M-bit value, i.e., an on-time signal. The larger on-time signal may result in a larger on-time.

For example, when the voltage difference mean value Vb or Vc output by the load detection circuit 221 is located in a second voltage interval with a lower ADC input voltage interval, the voltage difference mean value Vb or Vc is converted by the N-bit analog-to-digital converter 2221 to obtain a smaller N-bit value N2, the smaller N-bit value N2 is encoded by the N-bit to M-bit encoder 2222 and then converted into a larger M-bit value M2, and the larger M-bit value M2 may generate a larger on-time ton2. The larger on-time ton2 can improve the loading capacity of the switching circuit, thereby effectively improving the working efficiency of the switching circuit.

For another example, when the voltage difference mean Va output by the load detection circuit 221 is located in the 2^N voltage interval with a higher ADC input voltage interval, the voltage difference mean Va is converted by the N-bit analog-to-digital converter 2221 to obtain a larger N-bit value N1, the larger N-bit value N1 is further encoded by the N-bit to M-bit encoder 2222 and then converted into a smaller M-bit value M1, and the smaller M-bit value M1 can generate a smaller on-time ton1. The shorter on-time ton1 can increase the operating frequency of the switching circuit, thereby ensuring that the operating circuit has a higher voltage ripple frequency even under light load, and effectively reducing the noise component in the audio band.

Optionally, the value range of N may be determined by the load resolution accuracy of the switch circuit design, and the smaller the load range corresponding to each ADC input voltage interval is, the more the number of ADC input voltage intervals is, the larger N should be designed to be.

Optionally, the value range of M may be determined by a maximum value of the conduction time of the switch circuit (that is, a maximum load carrying capacity of the switch circuit), and the larger the load carrying capacity required by the switch circuit is, the larger the conduction time value of the transistor of the switch circuit is, and the larger the corresponding M bit value is.

As an alternative embodiment, referring to fig. 5 together, the present embodiment further provides a power converter 20, where the power converter 20 includes a switching circuit 21 having a transistor and the adaptive on-time control circuit 22.

In this embodiment, the power converter 20 includes a local oscillator clock, and the time required for the local oscillator clock to count from 0 to the M-bit value is the on time.

Referring to fig. 6, in the present embodiment, the switch circuit 21 includes a driver 2101, a first transistor 2102 and a second transistor 2103. The driver 2101 comprises a first input end, a first output end and a second output end, the first input end of the driver 2101 receives the control pulse signal, the first output end of the driver 2101 is connected with the gate of the first transistor 2102, and the second output end of the driver 2101 is connected with the gate of the second transistor 2103.

In this embodiment, when the first comparison signal output by the first comparator 223 of the adaptive on-time control circuit 22 is a positive value, the pulse generator 224 outputs the control pulse signal;

when the first input terminal of the driver 2101 receives the control pulse signal, the first output terminal of the driver 2101 outputs a first on signal PG to trigger the first transistor 2102 to turn on, after the on time, the first transistor 2102 is turned off, and then the second output terminal of the driver 2101 outputs a second on signal NG to turn on the second transistor 2103 for follow current.

The driver 2101 may be used to enhance the driving capability of the control pulse signal on the one hand and to generate the first and second on signals PG and NG with dead time on the other hand, avoiding the first and

second transistors

2102 and 2103 to pass through.

In this embodiment, the switch circuit 21 may further include an inductor L, a capacitor C, a power source Vin, a load RL, a first feedback resistor Rf1, and a second feedback resistor Rf2, and the total output voltage of the switch circuit 21 is Vout.

A first terminal of the inductor L is connected to the drains of the first transistor 2102 and the second transistor 2103, a second terminal of the inductor L is connected to a first terminal of the capacitor C, and a second terminal of the capacitor C is grounded. The positive electrode of the power source Vin is connected to the source of the first transistor 2102, and the negative electrode of the power source Vin is grounded. The first end of the load RL is connected with the first end of the capacitor C, and the second end of the load RL is grounded. A first end of the first feedback resistor Rf1 is connected to a first end of the load RL, a second end of the first feedback resistor Rf1 is connected to a first end of the second feedback resistor Rf2, and a second end of the second feedback resistor Rf2 is grounded.

The switching circuit 21 divides the voltage by the first feedback resistor Rf1 and the second feedback resistor Rf2 in series to obtain the output voltage Vfb, which can be calculated by the following formula:

Vfb＝Vout*Rf2/(Rf1+Rf2)，

referring to fig. 7, when the first comparator 223 detects that the output voltage Vfb is smaller than the reference voltage Vref, a first comparison signal is output; the pulse generator 224 is configured to receive the first comparison signal and the on-time signal, and output a control pulse signal Duty; when the first input terminal of the driver 2101 receives the control pulse signal Duty, the first output terminal and the second output terminal of the driver 2101 output the first on signal PG and the second on signal NG, respectively.

When the control pulse signal Duty is at a high potential, the first conducting signal PG is 0, which triggers the first transistor 2102 to conduct, at this time, the second conducting signal NG is 0, the second transistor 2103 is in an off state, the inductor L is charged, and the inductor current IL continuously increases. After the on-time ton, the control pulse signal Duty is at a low level, at this time, the first on-signal PG is 1, the first transistor 2102 is turned off, the second on-signal NG is 1, and the second transistor 2103 is turned on for inductor L freewheeling. Until the first comparator 223 again detects that the output voltage Vfb is less than the reference voltage Vref, the next cycle is turned on.

As an alternative embodiment, please refer to fig. 8, the switch circuit 21 further includes a Zero-crossing Detection circuit ZCD (Zero-crossing Detection, ZCD) including the second comparator 2104. A positive phase input terminal of the second comparator 2104 is connected to the drain of the first transistor 2102 and the drain of the second transistor 2103, and a negative phase input terminal of the second comparator 2104 is grounded; the output terminal of the second comparator 2104 outputs a second comparison signal, and the driver 2101 further includes a second input terminal, where the second input terminal of the driver 2101 receives the second comparison signal.

In this embodiment, when the second comparison signal output by the second comparator 2104 is a negative value, the driver 2101 keeps the second transistor 2103 on, and when the second comparison signal is a positive value, the driver 2101 turns off the second transistor 2103.

In this embodiment of the application, the zero-cross detection circuit ZCD may enable the switch circuit 21 to operate in a Discrete Conduction Mode (DCM) within a full load range, so as to reduce energy loss of the switch circuit 21 under a light load condition and improve light load efficiency.

Specifically, referring to fig. 9, when the first comparator 223 detects that the output voltage Vfb is smaller than the reference voltage Vref, the control pulse signal Duty is at a high level, the first on signal PG is 0, the first transistor 2102 is triggered to be turned on, the second on signal NG is 0, the second transistor 2103 is in an off state, the inductor L is charged, the inductor current IL continuously increases, and the output voltage Vfb gradually increases to be greater than the reference voltage Vref.

After the on-time ton, the control pulse signal Duty is at a low level, at this time, the first on-signal PG is 1, the first transistor 2102 is turned off, the second on-signal NG is 1, and the second transistor 2103 is turned on for inductor L freewheeling.

At this time, the second comparator 2104 compares the drain voltage Vsw of the second transistor 2103 with the ground Gnd, and when the drain voltage Vsw of the second transistor 2103 is lower than the ground Gnd, that is, the second comparison signal output by the second comparator 2104 is a negative value, the inductor current IL flows from the Vsw terminal to the Vout terminal, the second transistor 2103 is still kept turned on, and the inductor current IL gradually decreases. Until the drain voltage Vsw of the second transistor 2103 is higher than the ground Gnd, that is, the second comparison signal outputted by the second comparator 2104 is positive, the inductor current IL flows from the terminal Vout to the terminal Vsw, the inductor current IL flows to the ground through the second transistor 2103, and the load RL is not supplied with energy, so that in order to reduce the power loss during light load, the second on signal NG outputted by the driver 2101 is 0 at this time, the second transistor 2103 is turned off, and the inductor current IL is 0. The capacitor C discharges to supply energy to the load RL and the output voltage Vfb gradually decreases until the first comparator 223 again detects that the output voltage Vfb is less than the reference voltage Vref, and the next cycle is started.

In this embodiment, the ripple of the output voltage Vfb of the switching circuit 21 is affected by the load variation and the variation of the on-time ton.

Referring to fig. 10, td is a time delay, the load2 is greater than the load1, the load current of the load1 is Iload1, the load current of the load2 is Iload2, the inductor current corresponding to the load1 is IL _ load1, the inductor current corresponding to the load2 is IL _ load2, the output voltage corresponding to the load1 is Vfb _ load1, and the output voltage corresponding to the load2 is Vfb _ load2.

When the on-time ton is unchanged and the load2 is greater than the load1, the peak values of the inductor current IL _ load1 and the inductor current IL _ load2 are unchanged, but the frequency of the inductor current IL _ load2 is greater than the frequency of the inductor current IL _ load1. The load current Iload2 is greater than the load current Iload1. The peak value of the output voltage Vfb _ load2 is smaller than that of the output voltage Vfb _ load1, and the ripple frequency of the output voltage Vfb _ load2 is larger than that of the output voltage Vfb _ load1. When the on-time ton is constant, the load of the switching circuit increases, the peak value of the corresponding output voltage Vfb decreases, and the ripple frequency increases.

Referring to fig. 11, td is a delay, the on-time ton2 is greater than the on-time ton1, the load current is Iload, the inductor current corresponding to the on-time ton1 is IL _ ton1, the inductor current corresponding to the on-time ton2 is IL _ ton2, the output voltage corresponding to the on-time ton1 is Vfb _ ton1, and the output voltage corresponding to the on-time ton2 is Vfb _ ton2.

When the load is not changed and the on-time ton2 is greater than the on-time ton1, the load current Iload is not changed, the peak value of the inductor current IL _ ton2 is greater than the peak value of the inductor current IL _ ton1, the frequency of the inductor current IL _ ton2 is less than the frequency of the inductor current IL _ ton1, the peak value of the output voltage Vfb _ ton2 is greater than the peak value of the output voltage Vfb _ ton1, and the ripple frequency of the output voltage Vfb _ ton2 is less than the ripple frequency of the output voltage Vfb _ ton1. When the load is constant, the on-time ton increases, the peak value of the corresponding output voltage Vfb increases, and the ripple frequency decreases.

As can be seen from the conclusions of fig. 10 and 11, in order to improve the load carrying capability while the ripple frequency of the output voltage of the switching circuit is sufficiently large, the on-time ton may be reduced to increase the operating frequency when the load of the switching circuit is reduced; when the load of the switching circuit becomes large, the on time ton can be also made large to improve the load carrying capability.

Fig. 12 is a waveform diagram illustrating a process of adaptively adjusting the on-time by the adaptive on-time control circuit 22 according to an embodiment of the present application.

In this embodiment, the load detection circuit 221 amplifies a difference between the output voltage Vfb of the switching circuit and the reference voltage Vref and filters the difference to obtain a voltage difference mean value, and the on-time generation circuit 222 determines a degree of adaptation between a load of the switching circuit and the on-time ton by determining an ADC input voltage interval in which the voltage difference mean value is located, and then generates the corresponding on-time ton.

Referring to fig. 4 and 12, in one embodiment, the average voltage difference at time t0 is Va, which is higher than the input voltage interval of the ADC.

When the load suddenly increases at time t1, and the sampling time of the N-bit analog-to-digital converter 2221 is at time t0, the on time at this time is still the on time ton1 corresponding to the ADC voltage interval in which the voltage difference mean value Va is located, the peak value of the output voltage Vfb shifts down, the voltage difference (Vfb-Vref) between the output voltage Vfb and the reference voltage Vref decreases, the voltage difference mean value Vb obtained after amplification and filtering by the load detection circuit 22 also decreases, and the voltage difference mean value Vb is smaller than the voltage difference mean value Va.

At the sampling time t2 of the N-bit analog-to-digital converter 2221, referring to fig. 4, the ADC voltage interval in which the voltage difference mean value Vb is located corresponds to a new on-time ton2, the on-time ton2 is greater than the on-time ton1, and in subsequent use, due to update of the on-time, the peak value of the output voltage Vfb moves up, and the voltage difference (Vfb-Vref) between the output voltage Vfb and the reference voltage Vref is amplified and filtered by the load detection circuit 22 to obtain the voltage difference mean value Vc, which is greater than the voltage Vb, but referring to fig. 4, since the voltage Vb and the voltage Vc are in the same voltage interval of the ADC input voltage interval, the on-time is still the on-time ton2.

In the embodiment of the present application, the adaptive on-time control circuit 22 may detect the load magnitude in real time, and may also decrease the on-time ton when the load of the switching circuit decreases, so as to increase the operating frequency; when the load of the switching circuit becomes large, the on time ton can be also made large to improve the load carrying capability. The adaptive on-time control circuit 22 provided in the embodiment of the present application can adaptively adjust the on-time according to the load size, so that the ripple frequency of the output voltage of the circuit is large enough, the load carrying capacity of the circuit can be improved,

the embodiment of the present application further provides a chip 11, please refer to fig. 13, where the chip 11 includes the power converter 20 and an audio processing circuit 30, and the power converter 20 is configured to convert a voltage of a power supply and supply power to the audio processing circuit 30.

Optionally, the chip 11 may further include a radio frequency bluetooth circuit 40.

The embodiment of the present application further provides an electronic device 5, please refer to fig. 13 together, where the electronic device 5 includes the chip 11, and the electronic device 5 is a bluetooth headset or a bluetooth sound.

As an alternative embodiment, the electronic device 5 may comprise a power supply 10 and a chip 11.

In this embodiment, the electronic device 5 may be powered by a power supply 10, and the power supply 10 may be a lithium battery, i.e., a lithium polymer battery, which has the characteristics of light weight, high plasticity, and high energy. The power converter 20 is connected to the power source 10 for converting the voltage of the power source 10 to provide different power supply voltages. The radio frequency bluetooth circuit 40 is used for connecting with an external bluetooth device and acquiring an input signal. The audio processing circuit 30 is configured to decode and amplify the input signal, and then output a sound signal.

In this application embodiment, carry on power converter 20's chip 11 can be used in electronic equipment such as bluetooth headset and bluetooth stereo set, can reduce the noise component on the one hand, promotes tone quality performance, and on the other hand can also reduce the consumption, extension stand-by time.

It should be understood that the embodiments of the present application can be applied to power conversion of an audio processing system, including but not limited to power conversion of an audio processing system with a bluetooth headset and a bluetooth speaker, and the embodiments of the present application are also applicable to other products with an audio processing system, etc.

The preferred embodiments of the present application have been described in detail with reference to the accompanying drawings, however, the present application is not limited to the details of the above embodiments, and various simple modifications can be made to the technical solution of the present application within the technical idea of the present application, and these simple modifications are all within the protection scope of the present application.

Claims

1. A self-adaptive on-time control circuit is characterized by comprising a load detection circuit, an on-time generation circuit, a first comparator and a pulse generator;

the load detection circuit is used for receiving the output voltage and the reference voltage of the switch circuit and outputting a voltage difference mean value;

the conduction time generation circuit is used for receiving the voltage difference average value and generating a conduction time signal, and the conduction time signal is used for controlling the conduction time of a transistor in the switch circuit;

the first comparator is used for receiving the output voltage of the switch circuit and the reference voltage and outputting a first comparison signal;

the pulse generator is used for receiving the first comparison signal and the conducting time signal and outputting a control pulse signal, and the control pulse signal is used for controlling the on and off of a transistor in the switch circuit.

2. The adaptive on-time control circuit of claim 1, wherein the load detection circuit comprises a transconductance amplifier, a first amplifying resistor, and a low pass filter;

the first amplifying resistor comprises a first end and a second end, the first end of the first amplifying resistor is coupled to the output end of the transconductance amplifier, and the second end of the first amplifying resistor is grounded;

the transconductance amplifier comprises a positive phase input end, a negative phase input end and an output end, the positive phase input end of the transconductance amplifier receives the output voltage, the negative phase input end of the transconductance amplifier receives the reference voltage, and the output end of the transconductance amplifier is coupled to the first end of the first amplifying resistor and then outputs an amplifying voltage;

the low-pass filter comprises an input end and an output end, the input end of the low-pass filter is coupled with the output end of the transconductance amplifier and receives the amplified voltage, and the output end of the low-pass filter outputs the voltage difference mean value.

3. The adaptive on-time control circuit of claim 2, wherein the low pass filter has a corner frequency of less than 100kHz.

4. The adaptive on-time control circuit of claim 2, wherein the on-time generation circuit comprises an N-bit analog-to-digital converter;

the N-bit analog-to-digital converter comprises an input end and an output end, the input end of the N-bit analog-to-digital converter is coupled with the output end of the low-pass filter and used for receiving the voltage difference mean value, and the output end of the N-bit analog-to-digital converter outputs an N-bit value.

5. The adaptive on-time control circuit of claim 4, wherein the on-time generation circuit further comprises an N-bit to M-bit encoder;

the N-bit to M-bit encoder comprises an input end and an output end, the input end of the N-bit to M-bit encoder is coupled with the output end of the N-bit analog-to-digital converter and used for receiving an N-bit value, and the output end of the N-bit to M-bit encoder is coupled with the first input end of the pulse generator and used for outputting an M-bit value.

6. The adaptive on-time control circuit of claim 5, wherein the N-bit value and the M-bit value are both binary numbers, and both N and M are positive integers greater than 1.

7. The adaptive on-time control circuit of claim 6, wherein the N-bit value is proportional to the voltage difference average magnitude.

8. The adaptive on-time control circuit of claim 7, wherein the magnitude of the M-bit value and the N-bit value are inversely proportional.

9. The adaptive on-time control circuit of claim 8, wherein the N-bit value is inverted bitwise to obtain the M-bit value when the N-bit value is the same as the M-bit value.

10. A power converter comprising a switching circuit having a transistor and the adaptive on-time control circuit of any of claims 1-9.

11. The power converter according to claim 10, wherein the power converter comprises a local oscillator clock, and the on time is the time required for the local oscillator clock to count from 0 to an M-bit value.

12. The power converter of claim 11, wherein the switching circuit comprises a driver, a first transistor and a second transistor;

the driver comprises a first input end, a first output end and a second output end, the first input end of the driver receives the control pulse signal, the first output end of the driver is connected with the grid electrode of the first transistor, and the second output end of the driver is connected with the grid electrode of the second transistor.

13. The power converter of claim 12, wherein the switching circuit further comprises a zero crossing detection circuit comprising a second comparator;

the positive phase input end of the second comparator is connected with the drain electrode of the first transistor and the drain electrode of the second transistor, and the negative phase input end of the second comparator is grounded;

the output end of the second comparator outputs a second comparison signal, and the driver further comprises a second input end which receives the second comparison signal.

14. The power converter according to claim 12, wherein the pulse generator outputs the control pulse signal when the first comparison signal output by the first comparator is a positive value;

when the first input end of the driver receives the control pulse signal, the first output end of the driver outputs a first conduction signal to trigger the first transistor to be conducted, the first transistor is turned off after the conduction time, and then the second output end of the driver outputs a second conduction signal to start the second transistor to follow current.

15. The power converter according to claim 13, wherein the driver keeps the second transistor turned on when the second comparison signal output by the second comparator is a negative value, and turns off the second transistor when the second comparison signal is a positive value.

16. The power converter of claim 12, wherein the switching circuit further comprises an inductor, a capacitor, a power source, a load, a first feedback resistor, and a second feedback resistor;

17. A chip comprising audio processing circuitry and a power converter according to any of claims 10-16 for converting the voltage of a power supply and powering the audio processing circuitry.

18. An electronic device comprising the chip of claim 17, wherein the electronic device is a bluetooth headset or a bluetooth sound.