CN102103534A - Function test system for SOC - Google Patents
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Abstract
The invention provides a function test system for a system on chip (SOC). The function test system for the SOC comprises a test machine, a manipulator which is controlled by the test machine and used for testing a chip to be tested, a test sub board, and a test main board provided with a liquid crystal display. The test main board controls the test machine and the manipulator to work; the test sub board transmits state information of the current test item and test result information to the test main board through a serial port protocol; the test state information and the test result information comprise printed information and test item information; in the serial port protocol, the test item information is started with a pound sign-shaped character and ended with a star-shaped character, and the debugging printed information is not started with the pound sign-shaped character; the test main board transmits the final test result information of the chip to the manipulator through a test interface of the manipulator; and the manipulator counts the situation of finishing the chip test. The function test system can support manual tests and tests controlled by the manipulator; moreover, the test efficiency is high and the test cost is low.
Description
[technical field]
The present invention relates to the function test system of a kind of SOC, can support artificial manual test, also support mechanical arm control test.
[background technology]
The function of SOC (Functional Test-FT) test is last test before the product export.Requirement is carried out functional test to SOC, filter out the encapsulation wrong, the SOC chip (SOC is called system level chip) that performance is not up to standard.
How can effectively carry out the test job of SOC chip, be that academia, industrial community and each research unit are all in the problem of making great efforts to solve.The special test macro of general in the prior art employing adds signal to the SOC that is tested, and whether the corresponding output end from SOC receives the SOC corresponding output signal then, qualified to judge this SOC chip.Test analog-digital converter function such as the relatively more extensive popular SOC test macro of uses at present such as the 93000SOC test macro that uses SCUD-1A, Agilent science and technology, import a fixing signal at input end, whether turn back to corresponding detection system through output behind the analog to digital converter of chip to be measured, it is correct to go to analyze output signal by test macro.Adopting the test of this method undoubtedly is more accurate a bit, but shortcoming also clearly, the one, the software development difficulty is bigger, another undoubtedly is exactly the testing cost height, moreover is exactly the function that real simulation practical application possibly can't be accomplished for test as the controller of these classes such as LCD, Sensor by this class testing system.
[summary of the invention]
The technical problem to be solved in the present invention is to provide the function test system of a kind of SOC, has brought high efficiency method of testing in the chip testing of the SOC series that the daughter board chip is more or less the same.
The present invention is achieved in that the function test system of a kind of SOC, comprises tester table and is controlled by the mechanical arm that tester table is used to test chip to be measured; Also comprise test daughter board, testing host, described testing host control tester table and mechanical arm work, described test daughter board is passed to testing host through serial port protocol with the status information and the test result information of current test event, after all test events finish, described testing host sends to mechanical arm with the last test object information of the chip test interface by described mechanical arm, and mechanical arm carries out the statistics that chip testing finishes situation; Described test mode information and test result information include type information and test item information; With the beginning of # character, the * EOC is represented test item information in the described serial port protocol, not the expression debug print information that starts with the # character.Described testing host receives type information, then directly calls the printf function, prints on the LCDs of mainboard.
The present invention has following advantage: comprise tester table and be controlled by the mechanical arm that tester table is used to test chip to be measured; Also comprise the testing host of testing daughter board, being provided with LCDs, described testing host control tester table work and mechanical arm work, described test daughter board is passed to testing host through serial port protocol with the status information and the test result information of current test event, and described test mode information and test result information comprise type information and test item information; Described testing host sends to mechanical arm with the last test object information of the chip test interface by described mechanical arm, and mechanical arm carries out the statistics that chip testing finishes situation.The present invention can support artificial manual test, also supports mechanical arm control test, the testing efficiency height, and testing cost is low.
[description of drawings]
Fig. 1 is a system architecture diagram of the present invention.
Fig. 2 is the display mode synoptic diagram of display screen of the present invention.
The synoptic diagram that Fig. 3 communicates by letter for test interface between testing host of the present invention and the mechanical arm.
[embodiment]
The present invention is further illustrated in conjunction with the embodiments with reference to the accompanying drawings.
The function test system of SOC as shown in Figure 1, comprises tester table and is controlled by the mechanical arm that tester table is used to test chip to be measured; Also comprise the testing host of testing daughter board, being provided with LCDs, described testing host control tester table work and mechanical arm work, described test daughter board is passed to testing host through serial port protocol with the status information and the test result information of current test event, after all test events finish, described testing host sends to mechanical arm with the last test object information of the chip test interface by described mechanical arm, and mechanical arm carries out the statistics that chip testing finishes situation; Described test mode information and test result information include type information and test item information; With the beginning of # character, the * EOC is represented test item information in the described serial port protocol, not the expression debug print information that starts with the # character.Described testing host receives type information, then directly calls the printf function, prints on the LCDs of mainboard; Described testing host prints to zones different on the LCDs and has adopted different font colors according to dissimilar type informations; Described test item information comprises Begin order, Start order, Result order and End order; The test of described Begin order expression chip formally begins, and has the model of chip to be measured and the version number of testing software subsequently; Described certain test item of Start order expression formally begins, and with the name of test item, testing host can be counted test event quantity subsequently, can add 1 to a Start count value whenever; The test result of described certain test item of Result order expression is returned, subsequently with test result, the name of test item of returning this result and the name of next test item, testing host receiving Result when order, can extract the current test item name of return results, with before the name used during Start compare, to have passed through a certain Start in the middle of preventing; The test of described End order expression all items finishes, subsequently with tested altogether what numerical value, the main control chip of testing host can compare the own inner item number that the count value and the End order of project are with, and checks whether equate, so that know whether test leakage is arranged; Described test daughter board is when testing, and the pin that system will test the chip connection to be measured on the daughter board all is set to export 0.
Wherein the function of each hardware module is as follows:
A mechanical arm: mainly be connection design with the FT tester table, in the application of reality, all replace manual test by mechanical arm, comprise that work such as putting chip to be measured, startup test, end of test (EOT) statistical test situation, analysis yield all is that special-purpose board is finished, and therefore will design the communication interface of corresponding mechanical test and other control signal wire in main board;
The B testing host: mainly be the test that is used to start daughter board, switching daughter board power supply receives the test result that daughter board sends, and shows the status information of daughter board transmission etc., requires the main control chip of testing host to need to satisfy following MCU or the CPU that requires at least like this:
Serial ports (or other chips to be measured also have simultaneously communication interface),
A LCD interface,
Several general input/output ports;
The C display screen: a module must using when display screen is manual test and debugging, do not need to explain as the use in the debug process, then be in each test item of debugging, check where daughter board has run to;
D tests daughter board (chip to be measured): can be as the daughter board part of this system as long as have the SOC of the communication interface that serial ports or other mainboards have, different only is that design is fit to the method for testing of this chip to be measured and adjusts test code, all test items are write as the form of table, every end of test (EOT) is all returned test result, when overtime, the test daughter board does not also return normal test result and gives testing host, and it is Time out and the power supply that disconnects daughter board that testing host is then declared the test daughter board.
Principle of work of the present invention is:
Earlier chip to be measured is placed on the tester table, the detection acupuncture needle of the mechanical arm on its tester table places on the pin of chip to be measured, and the startup testing host carries out work, testing host drives the test daughter board test chip is tested, and the test daughter board is that each test item to be measured of chip is tested one by one.The test daughter board is passed to testing host through serial port protocol with the status information and the test result information of current test event, testing host display screen on supplies manual test with test result information through printing to after certain format conversion by mainboard, when each test item of chip to be measured all test finish after, the test interface of testing host by mechanical arm sends to the mechanical arm mechanical arm with the last test result of chip and carries out the statistics that chip testing finishes situation.Wherein the display mode of display screen is:
The screen separated into two parts is shown as shown in Figure 2, the part 10 of blue background is called Main win (seeing shown in Figure 2), its size is 320 * 240 (can adjust in mainboard software according to the application need of reality), the part 20 of black background is called Print win (seeing shown in Figure 2) in addition, and its size is all remaining parts of screen.
Main win is mainly used in and shows chip model to be measured, and which project chip software version to be measured number has tested, and test result is as important information how.
Print win is used to print Debugging message, all prints on this win regardless of the Debugging message or the Debugging message of chip to be measured that are main control chip.
Wherein said test item information comprises Begin order, Start order, Result order and End order; The test of described Begin order expression chip formally begins, and has the model of chip to be measured and the version number of testing software subsequently; Described certain test item of Start order expression formally begins, and with the name of test item, testing host can be counted test event quantity subsequently, can add 1 to a Start count value whenever; The test result of described certain test item of Result order expression is returned, subsequently with test result, the name of test item of returning this result and the name of next test item, main control chip is when receiving the Result order, can extract the current test item name of return results, with before the name used during Start compare, to have passed through a certain Start in the middle of preventing; The test of described End order expression all items finishes, subsequently with tested altogether what numerical value, main control chip can compare the item number of own inner count value to project with End order band, check whether equal so that know whether test leakage is arranged; Described test daughter board is when testing, and the pin that system will test the test chip connection on the daughter board all is set to export 0.As:
The Begin order
Bebinning character command type character command context EOC character
This is a string character * about chip model and version number of testing software for #B
For example: #BRK2806, V2009.02.04*
Represent that this is a Begin order, the content of order is RK2806, V2009.02.04
The Start order
For example: #SUART*
Represent that this is a Start order, what begin to test is the UART module
The Result order
For example: #R00UART, I2S*
Represent that this is a Result order, the module of current rreturn value is UART, and rreturn value is 00, and next test event is I2S, if arrived last test item, does not have next test item, and this order can become such #R00I2S*
Represent that this is a Result order, the module of current rreturn value is I2S, and rreturn value is 00, does not have next test item
The End order
For example: #END1E*
Represent that this is an End order, has tested the 1E item altogether.
Adopt after this agreement, what project order no matter later chip to be measured is, no matter what projects are arranged, how the model of die does not become, no matter how how the version date of software becomes, the firmware of main control chip is programming again all, and mainboard just has been the equal of a more stable testing auxiliary device.
Be described further below in conjunction with a specific embodiment.
SOC chip with a consumer electronics places on the tester table earlier, the detection acupuncture needle of the mechanical arm on its tester table places on the pin of chip to be measured, and the startup testing host carries out work, testing host drives the test daughter board test chip is tested, and the test daughter board is that each test item to be measured of chip is tested one by one.As I2C (Inter-Integrated Circuit) bus is a kind of twin wire universal serial bus by the exploitation of PHILIPS company, is used to connect microcontroller and peripherals thereof.We adopt outside or inner RTC (real-time timepiece chip) to test as the peripherals of I2C in the application.Concrete grammar: SOC is by I2C mouth initialization RTC controller to be measured, and initial time value of RTC (such as 2010.11.05 2 09:10:10 minute second in: week date hour) is set and starts RTC work, after certain time interval, go to read the value of RTC again, the value of reading and initial value and interlude addition are compared, does the value of reading equal initial value and adds interval time? if it is correct then the function (encapsulation and the controller that comprise pin) out of question of this I2C controller to be measured is described, test daughter board and through serial port protocol the status information (test I 2C) and the test result information (whether this bus of I2C is normal) of current test event are passed to testing host this moment, testing host display screen on supplies manual test with test result information through printing to after certain format conversion by mainboard, when each test item of chip to be measured all test finish after, the test interface of testing host by mechanical arm sends to the mechanical arm mechanical arm with the last test result of chip and carries out the statistics (whether the SOC chip of adding up this consumer electronics normal) that chip testing finishes situation.
What deserves to be mentioned is:
The certain time sequence of having communicated by letter between mainboard and the mechanical arm, main control chip is told mechanical arm test result according to this sequential.This sequential has the mechanical arm decision, we can only satisfy this sequential (concrete sequential can according to being used to select the mechanical arm of different producers to carry out corresponding modification), and the mechanical arm agreement that below adopted the FT tester table of " silicon product science and technology (Suzhou) company limited " is an example.
That the chances are is such for the sequential of mainboard software output: as shown in Figure 3
Rreturn value as follows
| HD4-HD1 | Implication |
| 0000 | Invalid rreturn value |
| 0111 | Success |
| 1011 | Failure |
| 1101 | The USB failure |
Wherein 1101 is RSTs that the client can be used for adding up special test picture, as above is set to USB failure output 1101 values in the table, and the user can add up this test result distribution and this unidirectional test yield according to 1101 output valve so.
Test daughter board of the present invention is when testing, and the pin that system will test the test chip connection on the daughter board all is set to export 0, solves reverse irrigated current.
The power supply that native system designs chip to be measured is to be controlled fully by main control chip, so under the situation of also not opening chip power to be measured, should supply with without any voltage, if but the pin that is connected with chip to be measured is not handled well, will make electric current pour in down a chimney to the circuit of chip to be measured, such as the pin that links to each other is high level, at this moment just have electric current and pour in down a chimney in the past, we have reached 1.6V by the actual voltage that pours in down a chimney back VB that measures.
These voltages that pour in down a chimney are influential to our test, it is so big that these pour in down a chimney voltage, cause not close fully by chip to be measured sometime, dependence is poured in down a chimney voltage and just can be worked, like this when main control chip really goes to open the power supply of chip to be measured, it is a lot of to find that chip to be measured has tested, like this main control chip at statistical test what results that draw later on just and End order the result who sends inconsistent, will think and make mistakes.
The situation of another possibility is, pour in down a chimney the voltage that voltage reaches CPU work, and do not reach the operating voltage of SDRAM, like this ARM run back operation SDRAM will abort, when main control chip really removes to open chip power to be measured by the time, because abort has appearred in ARM, can not normally move, therefore main control chip also just can not receive chip to be measured by the ready state that state indication pin returns, and will think that chip to be measured is problematic, can't start shooting.We have run into this situation really, and are easy to occur, and continuous race is gone up hundreds of and will be occurred once, and are after afterwards reverse irrigated current being solved, just again out of question.The method that solves reverse irrigated current is: all pin that are connected with chip to be measured all are set to export 0.
It should be noted that: the test request of each module of test daughter board
(1) the inside modules logic will be surveyed entirely
(2) external pin also will measure
(3) will survey under the various dominant frequency situations, the problem that has shows not come out when low frequency, and what also have shows not come out when high frequency
(4) test duration also lacks as far as possible, because factory testing was charged by second
(5) as long as the module testing function return test result to or mistake, other values generally do not receive
(6) test of module is finished by machine entirely, and nobody's participation can not be asked for help and be seen the result, or requires the people to do action accordingly.
Such as: whether not talkative test LCD interface allows the people look to show normal.
Perhaps test the real-time clock interface, the very important person goes the time of pinching to be certain about inaccurate.
Perhaps test video input interface, the very important person goes to see whether the image that photographed is normal.
Perhaps test the SD card, the very important person goes removable card, and normally whether inquiry read-write card.
(7) most important, the test code that guarantee you is correct, and module has coming out that problem can survey.
In communication, it should be noted that: do not power at chip to be measured, closed electricity and power on after in these time periods of resetting, two lines that the data of the serial ports of chip to be measured send and receive all are low level, and we know the low level start that represents to communicate by letter according to the agreement of serial ports, if therefore these time periods are not handled well, we will receive 0 data always, perhaps serial ports also can count off according to the stop bit mistake.So we must look for a method to solve this problem.
The method that this system adopts is that chip to be measured has individual state to indicate pin (mainboard chip certain not the GPIO mouth of usefulness), when chip does not power on, or closed, or electrification reset during this period of time in, this pin all is low level, only after the code of chip to be measured runs, after the intact serial ports of initialization, just can be changed to high level to state indication pin, main control chip receives that state indication pin is that high level just can enable later the serial ports interruption, begin to have received data, the data that receive after this have been valid data all just.
After test is finished, close before the power supply of chip to be measured in addition, main control chip must fall the serial ports impeding shutdown, does not receive data, otherwise after closing chip power to be measured, will interrupt always, receives a pile 0.
The present invention can realize: in the design of this system, the total interface of testing host does not substantially need to revise, when the test circuit of changing chip to be measured with draw the unified interconnected several pins of communicating by letter with testing host after just passable, come subtest if need to use the functional module of some other chip in the test process of daughter board, can directly adopt on the testing host this resource easily of interface fully as the daughter board of main control chip, adaptability is by force as long as chip to be measured can have the communication interface consistent with testing host and just can adopt this test macro.
In a word, the method of testing of traditional SOC has mostly just just been tested the encapsulation situation, the magnitude of voltage that adopts resistance, electric current to gather each pin determines whether encapsulation is normal, can the maximum like this encapsulation that can only test pin and test that can not be real operate as normal to each functional module of SOC, causes no small hidden danger.This method of testing is then different, can not only guarantee that chip can work together in situation about normally powering on, and can each module that can also test it work normally, finishes the conversion and the transmission of necessary data, signal, clock etc.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (5)
1. the function test system of a SOC comprises tester table and is controlled by the mechanical arm that tester table is used to test chip to be measured; It is characterized in that: also comprise test daughter board, testing host, described testing host control tester table and mechanical arm work, described test daughter board is passed to testing host through serial port protocol with the status information and the test result information of current test event, after all test events finish, described testing host sends to mechanical arm with the last test object information of the chip test interface by described mechanical arm, and mechanical arm carries out the statistics that chip testing finishes situation; Described test mode information and test result information include type information and test item information; With the beginning of # character, the * EOC is represented test item information in the described serial port protocol, not the expression debug print information that starts with the # character.
2. the function test system of SOC according to claim 1, it is characterized in that: described testing host is provided with LCDs, and described testing host receives type information, then directly calls the printf function, prints on the LCDs of testing host.
3. the function test system of SOC according to claim 2 is characterized in that: described testing host prints to zones different on the LCDs and has adopted different font colors according to dissimilar type informations.
4. the function test system of SOC according to claim 1 is characterized in that: described test item information comprises Begin order, Start order, Result order and End order; The test of described Begin order expression chip formally begins, and has the model of chip to be measured and the version number of testing software subsequently; Described certain test item of Start order expression formally begins, and with the name of test item, testing host can be counted test event quantity subsequently, can add 1 to a Start count value whenever; The test result of described certain test item of Result order expression is returned, subsequently with test result, the name of test item of returning this result and the name of next test item, main control chip is when receiving the Result order, can extract the current test item name of return results, with before the name used during Start compare, to have passed through a certain Start in the middle of preventing; The test of described End order expression all items finishes, subsequently with tested altogether what numerical value, main control chip can compare the item number of own inner count value to project with End order band, check whether equal so that know whether test leakage is arranged.
5. the function test system of SOC according to claim 1 is characterized in that: described test daughter board is when testing, and system will test the pin that the test chip on the daughter board connects and all be set to export 0.
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| CN111880754A (en) * | 2020-06-30 | 2020-11-03 | 厦门汉印电子技术有限公司 | Automatic test method, medium, computer device and system for printing device |
| CN111880754B (en) * | 2020-06-30 | 2022-05-31 | 厦门汉印电子技术有限公司 | Automatic testing method and medium for printing equipment, computer equipment and system |
| CN112213621A (en) * | 2020-09-22 | 2021-01-12 | 长江存储科技有限责任公司 | Wafer testing system and wafer testing method |
| CN112559267A (en) * | 2020-12-11 | 2021-03-26 | 海光信息技术股份有限公司 | Inter-integrated circuit bus I2C slave and I2C controller test method |
| CN112559267B (en) * | 2020-12-11 | 2022-08-23 | 海光信息技术股份有限公司 | Inter-integrated circuit bus I2C slave and I2C controller test method |
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