CN101710168A - Method and device thereof for testing system level of video SoC chip - Google Patents
Method and device thereof for testing system level of video SoC chip Download PDFInfo
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Abstract
The invention relates to a method for testing the system level of a video SoC chip, which comprises the following steps: generating a modulating signal; performing digital-to-analogue conversion on the modulating signal and transmitting the converted modulating signal to the tested chip; receiving a video signal output by the tested chip; performing analogue-to-digital conversion on the video signal and comparing slopes; and judging whether mosaic exists in the video or not according to a slope comparison result so as to obtain a chip test result. A device adopted by the method of the invention is connected with a computer and a machine station when in use, comprises a digital signal modulation generating module, a digital-to-analogue conversion module, an analogue-to-digital conversion module and a receiving and comparing module, and can realize the simultaneous testing of more than three chips. Compared with the conventional testing method, the method of the invention has the characteristics of lowering test cost, shortening product introduction time, achieving a high coverage rate and a low rate of escapement and realizing the mass production test of digital audio/video chips on a low-end machine station.
Description
Technical field
The invention belongs to the chip testing field, particularly a kind of system class testing method of chip and device thereof.
Background technology
The test of integrated circuit, the system level testing that particularly comprises video SoC (SOC (system on a chip)) chip of audio frequency and video function is the work of a complexity, each functional module of audio frequency and video integrated circuit (IC) chip contains structures such as logical signal, mixed signal, storer, some chip has also comprised the RF structure, makes system level testing become complicated more difficult.
If each functional module of difference in functionality is carried out repeatedly the through type test, test speed is slow on the one hand, and testing efficiency is low, is easy to cause chip to damage; Testing cost will be too expensive on the other hand.
Survey in the factory in most integrated circuit envelopes in the market, common board all can't satisfy the system level testing requirement of audio frequency and video SOC (system on a chip) (SoC) integrated circuit (IC) chip, and the higher board of configuration, the selection of envelope being surveyed factory has proposed requirements at the higher level, directly causes the rising of chip testing cost and chip price.
In order to overcome above weak point, the present invention proposes a kind of system class testing method and device thereof of video SoC chip.
Summary of the invention
The system class testing method of a kind of video SoC chip that the present invention proposes may further comprise the steps:
S1. the data of module receiving computer transmission take place in digital signal modulation, store in the electrically-erasable nonvolatile memory, and board sends reset signal to field programmable gate array, make the zero clearing that resets together of proving installation of the present invention and chip under test;
S2. field programmable gate array reading of data from the electrically-erasable nonvolatile memory, deliver to the digital-to-analogue conversion module, the digital-to-analogue conversion module generates corresponding simulative debugging signal according to clock signal, sends chip under test to, and chip under test is carried out demodulating and decoding;
S3. outputting video signal behind the chip under test demodulating and decoding, be transferred to the analog digital modular converter, the field programmable gate array clocking is given the analog digital modular converter, control analog digital modular converter converts vision signal to digital signal, be transferred to field programmable gate array then, field programmable gate array is made slope ratio;
S4. carry out slope ratio than the time, undergo mutation if find corresponding slope, then thinking has video mosaic; If no mosaic in the N frame in the past (N is any natural number that can freely be provided with) is then thought and is relatively passed through; Receive comparison module and send enable signal, output to computing machine by interface module, to board, tested chip is sorted out in the instruction that the board basis receives by the result of computer control output by/failure.
The system class testing method of described video SoC chip, for fear of at black-level period, slope is that 0 situation is thought normal condition by mistake, adds black level and detect on the G road of luminance signal that superposeed: if sampled value is not higher than setting value, then think to be in black-level period.
The system class testing method of described video SoC chip, field programmable gate array satisfy the ability of handling analog to digital conversion output more than three tunnel simultaneously, can test video SoC chip more than three tunnel simultaneously.
The device that a kind of system class testing method of video SoC chip uses is connected with board with computing machine when this device uses, and comprises: module, digital-to-analogue conversion module, analog digital modular converter take place and receive comparison module in the digital signal modulation.
Wherein, module takes place and comprises field programmable gate array and electrically-erasable nonvolatile memory in described digital signal modulation, and described field programmable gate array comprises interface module, control module and memory interface module;
Described field programmable gate array is by described interface module, control module, with Data Transport Protocol and computing machine communication data transmission, by memory interface module and the communication of electrically-erasable nonvolatile memory, the data on the computing machine are downloaded in the electrically-erasable nonvolatile memory again.
Wherein, described digital-to-analogue conversion module is come out the data read in the electrically-erasable nonvolatile memory that is stored in field programmable gate array by memory interface module, carries out digital-to-analog conversion by digital analog converter, produce simulation output, generate the modulated-analog signal that needs;
Wherein, described analog digital modular converter comprises filtering circuit and analog-digital converter, and the vision signal from chip under test output is converted to digital signal by the analog digital modular converter, sends to the reception comparison module;
Wherein, described reception comparison module also has field programmable gate array, and the rgb signal with each road video of analog digital modular converter output carries out slope ratio respectively;
Described reception comparison module carry out slope ratio than the time, undergo mutation if find corresponding slope, then thinking has video mosaic; If no mosaic in the N frame in the past (N is any natural number that can freely be provided with) is then thought and is relatively passed through; Receive comparison module and send enable signal, output to computer by interface module, to board, test chip is sorted out in the instruction that the board basis receives by the result of computer control output by/failure;
Described reception comparison module, for fear of at black-level period, slope is that 0 situation is thought normal condition by mistake, on the G road of luminance signal that superposeed, adds black level and detects, if sampled value is not higher than setting value, then thinks to be in black-level period;
The invention solves the system level testing demand that realizes digital audio/video SoC chip volume production at the low side tester table, its beneficial effect is: low to the board requirement, the general board of industry that has installed this device additional can meet the demands; Good with the property surveyed, can satisfy three above chips to test simultaneously; Debugging is convenient, and the coverage rate height satisfies the requirement of product quality system, and testing cost is low.
Description of drawings:
Fig. 1 realizes the system construction drawing that a plurality of chips are tested simultaneously for the device that adopts the inventive method;
Fig. 2 is the process flow diagram of the inventive method;
Fig. 3 is structure and the connection layout that module takes place in the digital signal modulation in apparatus of the present invention;
Fig. 4 is the structure and the connection layout of analog digital modular converter in apparatus of the present invention;
Fig. 5 is the structure of module and a specific embodiment that is connected take place for digital signal modulation in apparatus of the present invention a structure and be connected block diagram;
Fig. 6 is the structured flowchart of an embodiment of analog digital modular converter in apparatus of the present invention;
Fig. 7 is the structured flowchart that receives an embodiment of comparison module in apparatus of the present invention;
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is specifically described.
Adopt system construction drawing that the device of the inventive method realizes that a plurality of chips test simultaneously as shown in Figure 1.
A kind of system class testing method of video SoC chip, as shown in Figure 2, based on proving installation as shown in Figure 3 and Figure 4, concrete steps are as follows:
The data of on-site programmable gate array FPGA (301) receiving computer in the S1. described digital signal generation module (30) transmission store among the Flash (302), and board sends reset signal to FPGA (301), make the zero clearing that resets together of external hanging device and chip.
S2. after resetting, FPGA (301) delivers to DAC chip (310) from Flash (302) reading of data, and DAC chip (310) generates corresponding simulative debugging signal according to clock signal, sends chip under test to, makes the chip under test demodulating and decoding.
S3. the rgb video signal of chip under test demodulating and decoding output, be transferred to analog digital conversion chip ADC chip (320) by the VGA line, FPGA (301) provides clock signal and gives ADC chip (320), control its vision signal and change into digital signal, be transferred to FPGA (301), allow FPGA (301) make slope ratio.
4 tunnel analog digital switching signals that the comparison module of S4.FPGA (301) will be imported, totally 12 road rgb signals carry out slope ratio respectively; Slope ratio is a comparative unit with 8 points, undergos mutation if find corresponding slope, and then thinking has mosaic; For fear of at black-level period, slope is that 0 situation is thought normal condition by mistake, on the G road of luminance signal that superposeed, adds black level and detects, if sampled value is not higher than setting value, then to think to be in black-level period. comparison module compares 255 two field pictures altogether after resetting; If do not have mosaic in 5 frames in the past, then to think and relatively pass through. the enable pass of comparison module is crossed the EPP bus, control by PC. the vision signal of contrast chip decoding, make the result that test is passed through or failed, board is sorted out tested chip according to the instruction that receives.
Utilize FPGA (301) can also compare the real-time upgrading of module, as chip in practice, the phenomenon of image error and blank screen is arranged, analyze it and produce reason, be updated to FPGA (301) again, just can avoid these defective productss to come into the market, guarantee the quality and prestige of product.
The employed device of a kind of system class testing method of video SoC chip, as shown in Figure 1, be connected with board with computing machine, comprise the digital signal modulation and module (30), digital-to-analogue conversion module (31), analog digital modular converter (32) take place and receive comparison module (33).
Wherein, module (30) takes place in the digital signal modulation, as shown in Figure 5, has comprised FPGA (301) and Flash (302), and described FPGA inside is integrated with EPP communication (strengthening parallel) interface, EPP control module and Flash interface;
Earlier generate data with algorithm on computers, FPGA is by inner integrated EPP interface, the EPP control module, with EPP agreement and dataphone transmission data, again by inner integrated flash interface and flash communication, data are downloaded among the Flash, and its advantage is that different modulation signals can generate different data, so open structure can satisfy different SoC chip testing requirements.
Digital-to-analogue conversion module (31) as shown in Figure 5, has comprised digital-to-analogue conversion chip (310).FPGA comes out the data read that is stored among the flash by the flash interface, carries out interpolation arithmetic again, totally one road clock, and 20 circuit-switched data, 21 signal wires are linked the DAC chip, generate the modulated-analog signal of needs by the DAC chip.
Analog digital modular converter (32) as shown in Figure 6, has comprised analog digital conversion chip (320) and filtering circuit, and chip output video RGB three road signals are converted into digital signal by the ADC chip, send to FPGA;
Receive comparison module (33), as shown in Figure 7, FPGA and flash have been comprised, FPGA grasps the digital signal of ADC chip output, utilize its inner integrated video comparison module to carry out slope ratio, its comparative approach is as follows: 4 road AD signals that will import, and totally 12 road rgb signals carry out slope ratio respectively; Slope ratio is a comparative unit with 8 points, undergos mutation if find corresponding slope, and then thinking has mosaic; For fear of at black-level period, slope is that 0 situation is thought normal condition by mistake, on the G road of luminance signal that superposeed, adds black level and detects, if sampled value is not higher than setting value, then to think to be in black-level period. comparison module compares 255 two field pictures altogether after resetting; If do not have mosaic in 5 frames in the past, then think and relatively pass through. the enable pass of comparison module is crossed the EPP bus, is controlled by PC. and the result of output Pass/Fail is to board, and board is sorted out chip according to the instruction that receives.
FPGA satisfies the ability of handling 4 ADC chip outputs simultaneously in the present embodiment, so can 4 surveys together.
It should be understood that above-mentioned example just to explanation of the present invention, rather than limitation of the present invention, any innovation and creation that do not exceed in the connotation scope of the present invention all fall within protection scope of the present invention.
Claims (10)
1. the system class testing method of a video SoC chip is characterized in that, may further comprise the steps:
S1. the data of module receiving computer transmission take place in digital signal modulation, store in the electrically-erasable nonvolatile memory, and board sends reset signal to field programmable gate array, make the zero clearing that resets together of proving installation of the present invention and chip under test;
S2. field programmable gate array reading of data from the electrically-erasable nonvolatile memory, deliver to the digital-to-analogue conversion module, the digital-to-analogue conversion module generates corresponding simulative debugging signal according to clock signal, sends chip under test to, and chip under test is carried out demodulating and decoding;
S3. outputting video signal behind the chip under test demodulating and decoding, be transferred to the analog digital modular converter, the field programmable gate array clocking is given the analog digital modular converter, control analog digital modular converter converts vision signal to digital signal, be transferred to field programmable gate array then, field programmable gate array is made slope ratio;
S4. carry out slope ratio than the time, undergo mutation if find corresponding slope, then thinking has video mosaic; If no mosaic in the N frame in the past (N is any natural number that can freely be provided with) is then thought and is relatively passed through; Receive comparison module and send enable signal, output to computing machine by interface module, to board, tested chip is sorted out in the instruction that the board basis receives by the result of computer control output by/failure.
2. the system class testing method of a kind of video SoC chip as claimed in claim 1, be connected with board with computing machine when its device that adopts uses, it is characterized in that: comprise the digital signal modulation and module, digital-to-analogue conversion module, analog digital modular converter take place and receive comparison module.
3. the system level testing device of a kind of video SoC chip as claimed in claim 2, it is characterized in that: module takes place and comprises field programmable gate array and electrically-erasable nonvolatile memory in described digital signal modulation, and described field programmable gate array comprises interface module, control module and memory interface module.
4. the system level testing device of a kind of video SoC chip as claimed in claim 3, it is characterized in that: described field programmable gate array is by described interface module, control module, with Data Transport Protocol and computing machine communication data transmission, by memory interface module and the communication of electrically-erasable nonvolatile memory, the data on the computing machine are downloaded in the electrically-erasable nonvolatile memory again.
5. the system level testing device of a kind of video SoC chip as claimed in claim 2, described digital-to-analogue conversion module, by memory interface module the data read in the electrically-erasable nonvolatile memory that is stored in field programmable gate array is come out, carry out digital-to-analog conversion by digital analog converter, produce simulation output, generate the modulated-analog signal that needs.
6. the system level testing device of a kind of video SoC chip as claimed in claim 2, it is characterized in that: described analog digital modular converter, comprise filtering circuit and analog-digital converter, vision signal from chip under test output, be converted to digital signal by the analog digital modular converter, send to the reception comparison module.
7. the system level testing device of a kind of video SoC chip as claimed in claim 2, it is characterized in that: described reception comparison module, also have field programmable gate array, the rgb signal with each road video of analog digital modular converter output carries out slope ratio respectively.
8. the system level testing device of a kind of video SoC chip as claimed in claim 7 is characterized in that: described reception comparison module carry out slope ratio than the time, undergo mutation if find corresponding slope, then thinking has video mosaic; If no mosaic in the N frame in the past (N is any natural number that can freely be provided with) is then thought and is relatively passed through; Receive comparison module and send enable signal, output to computer by interface module, to board, test chip is sorted out in the instruction that the board basis receives by the result of computer control output by/failure.
9. the system level testing device of a kind of video SoC chip as claimed in claim 7, it is characterized in that: described reception comparison module is for fear of at black-level period, slope is that 0 situation is thought normal condition by mistake, on the G road of luminance signal that superposeed, adding black level detects, if sampled value is not higher than setting value, then think to be in black-level period.
10. the system class testing method of a kind of video SoC chip as claimed in claim 1 is characterized in that: field programmable gate array satisfies the ability of handling three above analog to digital conversion outputs simultaneously, can test chip more than three tunnel simultaneously.
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| CN 200910155128 CN101710168B (en) | 2009-12-02 | 2009-12-02 | Method and device thereof for testing system level of video SoC chip |
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| CN 200910155128 CN101710168B (en) | 2009-12-02 | 2009-12-02 | Method and device thereof for testing system level of video SoC chip |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102103534A (en) * | 2010-12-06 | 2011-06-22 | 福州瑞芯微电子有限公司 | Function test system for SOC |
| CN102184132A (en) * | 2011-04-28 | 2011-09-14 | 谭洪舟 | Method and system for testing video processing chip |
| CN103176120A (en) * | 2011-12-22 | 2013-06-26 | 英业达股份有限公司 | Signal simulating device and signal recording and simulating test method |
| CN104347120A (en) * | 2013-08-07 | 2015-02-11 | 上海华虹宏力半导体制造有限公司 | Method for increasing concurrent-testing amount of memory tester |
| CN113009318A (en) * | 2021-02-25 | 2021-06-22 | 合肥宏晶微电子科技股份有限公司 | Test equipment and test method for video processing chip |
-
2009
- 2009-12-02 CN CN 200910155128 patent/CN101710168B/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102103534A (en) * | 2010-12-06 | 2011-06-22 | 福州瑞芯微电子有限公司 | Function test system for SOC |
| CN102103534B (en) * | 2010-12-06 | 2012-08-29 | 福州瑞芯微电子有限公司 | Function test system for SOC |
| CN102184132A (en) * | 2011-04-28 | 2011-09-14 | 谭洪舟 | Method and system for testing video processing chip |
| CN103176120A (en) * | 2011-12-22 | 2013-06-26 | 英业达股份有限公司 | Signal simulating device and signal recording and simulating test method |
| CN104347120A (en) * | 2013-08-07 | 2015-02-11 | 上海华虹宏力半导体制造有限公司 | Method for increasing concurrent-testing amount of memory tester |
| CN104347120B (en) * | 2013-08-07 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | Realize that memory test instrument improves the method with number is surveyed |
| CN113009318A (en) * | 2021-02-25 | 2021-06-22 | 合肥宏晶微电子科技股份有限公司 | Test equipment and test method for video processing chip |
| CN113009318B (en) * | 2021-02-25 | 2023-07-18 | 宏晶微电子科技股份有限公司 | Testing equipment and testing method for video processing chip |
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| CN101710168B (en) | 2013-07-31 |
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