CN112992261B - Memory test system - Google Patents
Memory test system Download PDFInfo
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- CN112992261B CN112992261B CN201911304012.2A CN201911304012A CN112992261B CN 112992261 B CN112992261 B CN 112992261B CN 201911304012 A CN201911304012 A CN 201911304012A CN 112992261 B CN112992261 B CN 112992261B
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- 238000012360 testing method Methods 0.000 title claims abstract description 193
- 230000015654 memory Effects 0.000 title claims abstract description 155
- 238000004891 communication Methods 0.000 claims abstract description 22
- 238000012545 processing Methods 0.000 claims abstract description 8
- 230000006870 function Effects 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 101100498818 Arabidopsis thaliana DDR4 gene Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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Abstract
The invention provides a memory test system, comprising: the test main board is provided with a memory slot for inserting the memory to be tested; the central processing unit is arranged on the test main board; the current testing module is connected with the memory slot and is used for measuring the working current of the memory to be tested; the test control module is in communication connection with the test main board and the current test module and is used for controlling the test main board to enter a BIOS setting page so as to set test parameters of the memory to be tested, controlling the CPU on the test main board to run memory test software after the test main board is controlled to be started so as to test the memory to be tested through the test parameters and controlling the current test module to obtain working current of the memory to be tested. The invention can effectively modify the test parameters of the memory to be tested, is simple and universal, has wide coverage, and can further improve the yield of the memory to be tested.
Description
Technical Field
The disclosed embodiments of the present invention relate to the field of computers, and more particularly, to a memory testing system.
Background
Currently, memories include UDIMM (desktop memory), sodim (notebook memory), and the like, and various manufacturing defects exist during production, and production tests are generally performed after production, so that defective products can be screened out.
At present, most of memory products are applied to an x86 compatible machine, so that an x86 motherboard is generally used to test the memory products together with memory test software, and the memory test software is a software capable of running in an x86 CPU 120, but only the memory test software is used, and memory voltage, time sequence, frequency and the like need to be modified from motherboard BIOS codes, so that the memory voltage, time sequence, frequency and the like of an x86 platform cannot be effectively modified, and the current value of the memory during operation cannot be measured, and the coverage area is narrow.
Disclosure of Invention
According to an embodiment of the present invention, a memory test system is provided to solve the above-mentioned problems.
According to aspects of the present invention, an exemplary memory test system is disclosed, comprising: the test main board is provided with a memory slot for inserting the memory to be tested; the central processing unit is arranged on the test main board; the current testing module is connected with the memory slot and is used for measuring the working current of the memory to be tested; the test control module is in communication connection with the test main board and the current test module and is used for controlling the test main board to enter a BIOS setting page so as to set test parameters of the memory to be tested, controlling the CPU on the test main board to run memory test software after the test main board is controlled to be started so as to test the memory to be tested through the test parameters and controlling the current test module to obtain working current of the memory to be tested.
In some embodiments, the test control module comprises a memory and a controller, wherein the memory is communicatively connected to the controller, and memory test software is stored in the memory; the controller is in communication connection with the test main board through a USB interface.
In some embodiments, the controller is configured to simulate functions of a USB keyboard and a mouse, so as to control the test motherboard to enter a BIOS setup page through the USB keyboard and the mouse, so as to set test parameters of the memory to be tested; the controller is used for simulating the function of the USB flash disk through the memory so as to control the central processing unit on the test main board to run the memory test software through the USB flash disk, and the memory to be tested is tested through the test parameters.
In some embodiments, the controller is configured to simulate a function of a usb disk through the memory, so as to control the cpu on the test motherboard to run different memory test software in different test phases through the usb disk.
In some embodiments, the current testing module comprises: the adapter plate is inserted into the memory slot; the current acquisition circuit is arranged on the adapter plate, is electrically connected with the memory to be tested, and is in communication connection with the controller through a CAN interface or a UART interface.
In some embodiments, the device further comprises a temperature control module, wherein the temperature control module comprises a temperature control circuit and a high-temperature cover electrically connected with the temperature control circuit, wherein the temperature control circuit is in communication connection with the controller through a CAN interface or a UART interface, and the Gao Wenzhao is arranged on the memory to be tested so that the memory to be tested is located in the Gao Wenzhao.
In some embodiments, the test motherboard is further in communication connection with the controller through a UART interface, so as to send a test result obtained by testing the memory to be tested through the test parameter to the controller.
In some embodiments, the controller is communicatively connected to the test motherboard via a GPIO interface to control the test motherboard to power on, reset, and power off.
In some embodiments, the test parameters include an operation timing sequence, an operation voltage, and an operation frequency of the memory to be tested.
In some embodiments, a CPU socket is disposed on the test motherboard, where the CPU is inserted into the CPU socket, and the CPU socket and the memory socket are located on the same surface of the test motherboard.
The invention has the beneficial effects that: the test control module is used for controlling the test main board to enter the BIOS setting page so as to set the test parameters of the memory to be tested, and controlling the CPU of the test main board to run the memory test software after the test main board is started so as to test the memory to be tested through the test parameters, thereby effectively setting the test parameters of the memory to be tested, effectively modifying the test parameters of the memory to be tested, being simple and universal, having wide coverage, and realizing the acquisition of the current when the memory to be tested is tested through the current test module, and further improving the yield of the memory to be tested.
Drawings
The invention will be further described with reference to the accompanying drawings and embodiments, in which:
FIG. 1 is a schematic diagram of a memory test system according to an embodiment of the invention.
FIG. 2 is a schematic diagram of a memory test system according to an embodiment of the invention.
Detailed Description
In order to make the technical scheme of the present invention better understood by those skilled in the art, the technical scheme of the present invention will be further described in detail with reference to the accompanying drawings and the detailed description.
Fig. 1 is a schematic diagram of a memory test system according to an embodiment of the invention. The memory test system 100 includes a test motherboard 110, a CPU (central processing unit ) 120, a current test module 130, and a test control module 140.
The test motherboard 110 is provided with a memory slot 111 for inserting a memory to be tested. The test motherboard 110 may be an x86 motherboard. The Memory to be tested may be a DIMM (Dual-Inline Memory Modules), such as UDIMM (desktop Memory), SODIMM (notebook Memory), and the like. DIMMs may include DDR (Double Data Rate), e.g., DDR3 and DDR4.
The CPU 120 is disposed on the test motherboard 110, and the CPU 120 is used for running memory test software to test the memory to be tested.
The current test module 130 is communicatively connected to the memory under test. The current testing module 130 is used for measuring the working current of the memory to be tested.
The test control module 140 is communicatively coupled to the test motherboard 110 and the current test module 130. The test control module 140 is configured to control the test motherboard 110 to enter a BIOS setup page to set a test parameter of the memory to be tested, and after the test motherboard 110 is controlled to be started, control the CPU 120 on the test motherboard 110 to run the memory test software to test the memory to be tested according to the test parameter, and control the current test module 130 to obtain a working current of the memory to be tested.
In an example, the test parameters of the memory to be tested include an operation timing, an operation voltage, and an operation frequency of the memory to be tested.
In this embodiment, the test control module 140 controls the test motherboard 110 to enter the BIOS setting page to set the test parameters of the memory to be tested, and controls the CPU 120 on the test motherboard 110 to run the memory test software after the test motherboard 110 is started to test the memory to be tested through the test parameters, so as to effectively set the test parameters of the memory to be tested, thereby effectively modifying the test parameters of the memory to be tested, being simple and universal, having wide coverage, and realizing current collection when testing the memory to be tested through the current test module 130, and further improving the yield of the memory to be tested.
In some embodiments, as shown in FIG. 2, the test control module 140 includes a memory 142 and a controller 141, wherein the memory 142 is communicatively coupled to the controller 141, and memory test software is stored in the memory 142.
The controller 141 is communicatively connected to the test motherboard 110 via a USB (Universal Serial Bus ) interface 1 b. Specifically, the controller 141 includes a USB interface 1b, the test motherboard 110 includes a USB interface 1b, and the USB interface 1b of the controller 141 is connected to the USB interface 1b of the test motherboard 110, so as to realize the communication connection between the controller 141 and the test motherboard 110 through the USB interface 1 b.
The controller 141 is used for simulating functions of the USB keyboard and the mouse to control the test motherboard 110 to enter the BIOS setup page through the USB keyboard and the mouse to set the test parameters of the memory to be tested. The controller 141 simulates functions of the USB keyboard and the mouse through a communication protocol of the keyboard and the mouse, so that the controller 141 can be used as the USB keyboard and the mouse, and further controls the test motherboard 110 to enter the BIOS setting page through the USB keyboard and the mouse, and further sets test parameters of the memory to be tested on the BIOS setting page.
The controller 141 is configured to simulate the function of the usb through the memory 142, so as to control the test motherboard 110 to run the memory test software through the usb, so as to test the memory to be tested through the test parameters. The controller 141 simulates the function of the usb through the communication protocol of the usb, so that the controller 141 can be used as the usb through the memory 142, and then the CPU 120 on the test motherboard 110 runs the memory test software through the guidance of the usb, and tests the memory to be tested through the test parameters. In an example, the controller 141 is configured to simulate the function of the usb disk through the memory 142, so as to control the CPU 120 on the test motherboard 110 to run different memory test software at different test stages through the usb disk. Thus, different tests on the memory to be tested are realized in different test stages.
In this embodiment, the test control module 140 simulates the functions of the USB keyboard, the mouse and the USB disk, so as to effectively set the test parameters of the memory to be tested, and test the memory to be tested through the test parameters, which is simple and universal.
In some embodiments, as shown in fig. 2, the current test module 130 includes a patch panel 131 and a current collection circuit 132. The interposer 131 is inserted into the memory slot 111. The current collection circuit 132 is disposed on the adapter plate 131 and is in communication connection with the memory to be tested. In one example, as shown in fig. 2, the current acquisition circuit 132 is communicatively coupled to the controller 141 via a CAN (Controller Area Network ) interface 1 a. In an example, the adapter plate 131 is connected to the to-be-tested memory, and when the to-be-tested memory is connected to the adapter plate 131, the current collection circuit 132 on the adapter plate 131 is electrically connected to the pin of the to-be-tested memory, so that the current collection circuit 132 can collect the working current of the to-be-tested memory. The current acquisition circuit 132 is in communication connection with the controller 141 through the CAN interface 1a, the controller 141 sends a current acquisition instruction to the current acquisition circuit 132 through the CAN interface 1a, the current acquisition circuit 132 responds to the current acquisition instruction, the acquired working current of the memory to be tested is returned to the controller 141, and the controller 141 further acquires the working current of the memory to be tested acquired by the current acquisition circuit 132. Specifically, the interposer 131 is provided with a CAN interface 1a, the controller 141 includes the CAN interface 1a, and the CAN interface 1a of the controller 141 is connected with the CAN interface 1a on the interposer 131, so as to realize the communication connection between the current acquisition circuit 132 and the controller 141 through the CAN interface 1 a. In other examples, the current collection circuit 132 may also be communicatively coupled to the controller 141 via a UART (Universal Asynchronous Receiver/Transmitter) interface.
In some embodiments, as shown in fig. 2, the memory test system 100 further includes a temperature control module 150, wherein the temperature control module 150 includes a temperature control circuit 151 and a high temperature enclosure 152 electrically connected to the temperature control circuit 151. In one example, as shown in fig. 2, the temperature control circuit 151 is communicatively connected to the controller 141 through the CAN interface 1a, and the high temperature enclosure 152 is disposed above the memory to be tested, so that the memory to be tested is located within the Gao Wenzhao. In other examples, the temperature control circuit 151 may also be communicatively coupled to the control 141 via a UART interface.
The controller 141 sends a temperature setting instruction to the temperature control circuit 151, and the temperature control circuit 151 receives the temperature setting instruction of the controller 141 and controls the high temperature cover 152 to heat up or stop heating up so that the memory to be tested is at a corresponding temperature, and then the memory to be tested is tested at the corresponding temperature, so that the working temperature of the memory to be tested is tested. When the memory to be tested is tested, the temperature of the memory to be tested can be 85 degrees or 65 degrees. In one example, a heating wire and a temperature sensor are disposed within the high temperature enclosure 152, wherein the heating wire and the temperature sensor are electrically connected to the temperature control circuit 151, respectively. The temperature control circuit 151 receives the temperature setting instruction of the controller 141, controls the heating wire in the high temperature cover 152 to heat so as to enable the high temperature cover 152 to heat, feeds back the temperature in the Gao Wenzhao through the temperature sensor, and controls the heating wire in the high temperature cover 152 to stop heating when the temperature in the Gao Wenzhao reaches the corresponding temperature so as to enable the high temperature cover 152 to keep the corresponding temperature.
In some embodiments, as shown in fig. 2, the test motherboard 110 is further communicatively connected to the controller 141 through a UART (Universal Asynchronous Receiver/Transmitter, universal asynchronous receiver Transmitter) interface 1c, so as to send a test result obtained by testing the memory to be tested through the test parameters to the controller 141. Specifically, the controller 141 includes a UART interface 1c, the test main board 110 includes a UART interface 1c, and the UART interface 1c of the controller 141 is connected to the UART interface 1c of the test main board 110, so as to realize the communication connection between the controller 141 and the test main board 110 through the UART interface 1 c.
In some embodiments, as shown in fig. 2, the controller 141 is communicatively connected to the test motherboard 110 through a GPIO (General purpose input/output) interface 1d to control the test motherboard 110 to be turned on, reset, and turned off. Specifically, the controller 141 includes a GPIO interface 1d, the test motherboard 110 includes a GPIO interface 1d, and the UART interface 1c of the controller 141 is connected to the GPIO interface 1d of the test motherboard 110, so as to realize the communication connection between the controller 141 and the test motherboard 110 through the GPIO interface 1 d.
In some embodiments, as shown in fig. 2, controller 141 also includes an ethernet interface 1f. The external device is communicatively connected to the controller 141 via the ethernet interface 1f, and the external device may then send relevant information to the controller 141, for example, a start test instruction.
It should be noted that, the controller 141 is in communication connection with the test motherboard 110, the current collecting circuit 132, the temperature control circuit 151, the external device, etc. through different interfaces, and the controller 141 has a communication module therein, or the controller 141 communicates with the test motherboard 110, the current collecting circuit 132, the temperature control circuit 151, the external device, etc. through an external communication module and a corresponding interface thereof.
In some embodiments, as shown in fig. 2, the test control module 140 further includes a power supply 143, where the power supply 143 is electrically connected to the test motherboard 110 to provide a supply voltage to the test motherboard 110. The power supply 143 may be controlled by the controller 141 to supply power, and when the controller 141 sends a power supply command, the power supply 143 is operated to supply power, and when the controller sends a power failure command, the power supply 143 is not operated to stop supplying power. The power supply 143 may also remain electrically connected to the test motherboard 110 at all times.
The CPU 120 is disposed on the test motherboard 110, specifically, as shown in fig. 2, the test motherboard 110 is provided with a CPU socket 112, and the CPU 120 is inserted into the CPU socket 112, and in an example, the CPU socket 112 and the memory socket 111 are located on the same surface of the test motherboard 110. It should be noted that only the portion of the test motherboard 110 relevant to the present invention is described in the present invention, and the test motherboard 110 may also include other portions, which are not limited herein.
Those skilled in the art will readily appreciate that many modifications and variations are possible in the device and method while maintaining the teachings of the invention. Accordingly, the above disclosure should be viewed as limited only by the scope of the appended claims.
Claims (9)
1. A memory test system, comprising:
the test main board is provided with a memory slot for inserting the memory to be tested;
the central processing unit is arranged on the test main board;
the current testing module is connected with the memory slot and is used for measuring the working current of the memory to be tested;
the test control module is in communication connection with the test main board and the current test module and is used for controlling the test main board to enter a BIOS setting page so as to set test parameters of the memory to be tested, controlling the central processing unit on the test main board to run memory test software after controlling the test main board to start up so as to test the memory to be tested through the test parameters and controlling the current test module to obtain working current of the memory to be tested;
the test control module comprises a memory and a controller, wherein the memory is in communication connection with the controller, and memory test software is stored in the memory; the controller is in communication connection with the test main board through a USB interface.
2. The memory test system of claim 1, wherein,
the controller is used for simulating the functions of a USB keyboard and a mouse so as to control the test main board to enter a BIOS setting page through the USB keyboard and the mouse and set the test parameters of the memory to be tested;
the controller is used for simulating the function of the USB flash disk through the memory so as to control the central processing unit on the test main board to run the memory test software through the USB flash disk, and the memory to be tested is tested through the test parameters.
3. The memory test system of claim 2, wherein,
the controller is used for simulating the functions of the USB flash disk through the memory so as to control the central processing unit on the test main board to run different memory test software in different test stages through the USB flash disk.
4. The memory testing system of claim 1, wherein the current testing module comprises:
the adapter plate is inserted into the memory slot;
the current acquisition circuit is arranged on the adapter plate, is electrically connected with the memory to be tested, and is in communication connection with the controller through a CAN interface or a UART interface.
5. The memory test system of claim 1, further comprising a temperature control module, wherein the temperature control module comprises a temperature control circuit and a high temperature cover electrically connected to the temperature control circuit, wherein the temperature control circuit is communicatively connected to the controller via a CAN interface or a UART interface, and the Gao Wenzhao is disposed above the memory under test such that the memory under test is located within the Gao Wenzhao.
6. The memory test system of claim 1, wherein the test motherboard is further communicatively coupled to the controller via a UART interface to send test results obtained from testing the memory under test via the test parameters to the controller.
7. The memory test system of claim 1, wherein,
the controller is in communication connection with the test main board through a GPIO interface so as to control the test main board to start, reset and shut down.
8. The memory test system of any one of claims 1-7, wherein the test parameters include an operating timing, an operating voltage, and an operating frequency of the memory under test.
9. The memory test system of claim 8, wherein,
the test main board is provided with a CPU slot, wherein the CPU is inserted into the CPU slot, and the CPU slot and the memory slot are positioned on the same surface of the test main board.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911304012.2A CN112992261B (en) | 2019-12-17 | 2019-12-17 | Memory test system |
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| CN201911304012.2A CN112992261B (en) | 2019-12-17 | 2019-12-17 | Memory test system |
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| CN112992261B true CN112992261B (en) | 2024-04-05 |
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Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101604275A (en) * | 2008-06-13 | 2009-12-16 | 鸿富锦精密工业（深圳）有限公司 | BIOS test macro and method of testing thereof |
| CN102103534A (en) * | 2010-12-06 | 2011-06-22 | 福州瑞芯微电子有限公司 | Function test system for SOC |
| CN102289399A (en) * | 2011-09-01 | 2011-12-21 | 深圳芯智汇科技有限公司 | System and method for testing main board of computer |
| CN102789405A (en) * | 2011-05-16 | 2012-11-21 | 鸿富锦精密工业（深圳）有限公司 | Automated testing method and system for mainboard |
| CN102866939A (en) * | 2012-09-05 | 2013-01-09 | 记忆科技(深圳)有限公司 | Test device for internal memory |
| CN102880534A (en) * | 2012-07-20 | 2013-01-16 | 曙光信息产业(北京)有限公司 | Testing method for memory voltage of Loongson server motherboard |
| CN103035301A (en) * | 2011-10-06 | 2013-04-10 | 鸿富锦精密工业（深圳）有限公司 | Testing method and testing device for parameters of memory bar |
| CN103973534A (en) * | 2014-05-28 | 2014-08-06 | 广州视源电子科技股份有限公司 | Analog U disk sharing method and analog U disk sharing equipment |
| CN104459518A (en) * | 2014-11-27 | 2015-03-25 | 北京时代民芯科技有限公司 | Function automation testing system and testing method based on SoPC chip |
| CN204256724U (en) * | 2014-12-13 | 2015-04-08 | 海太半导体（无锡）有限公司 | A kind of server memory testing apparatus |
| CN104681093A (en) * | 2014-12-26 | 2015-06-03 | 复旦大学 | Semiconductor memory device electrical parameter test system |
| CN106326054A (en) * | 2016-08-25 | 2017-01-11 | 天津市英贝特航天科技有限公司 | Automatic test system and method of mainboard PCI external device |
| CN107132468A (en) * | 2016-02-26 | 2017-09-05 | 富泰华工业（深圳）有限公司 | Mainboard test device and method of testing |
| CN109062745A (en) * | 2018-07-26 | 2018-12-21 | 郑州云海信息技术有限公司 | A kind of test terminal with testing service device hardware temperatures |
| CN109100636A (en) * | 2018-07-11 | 2018-12-28 | 青岛北洋天青数联智能股份有限公司 | Circuit board detection method, device, system and test host computer |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001176294A (en) * | 1999-12-17 | 2001-06-29 | Hitachi Ltd | Test method, manufacturing method, and test device for memory chip, test method, manufacturing method, test device for memory module, and manufacturing method for computer |
-
2019
- 2019-12-17 CN CN201911304012.2A patent/CN112992261B/en active Active
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101604275A (en) * | 2008-06-13 | 2009-12-16 | 鸿富锦精密工业（深圳）有限公司 | BIOS test macro and method of testing thereof |
| CN102103534A (en) * | 2010-12-06 | 2011-06-22 | 福州瑞芯微电子有限公司 | Function test system for SOC |
| CN102789405A (en) * | 2011-05-16 | 2012-11-21 | 鸿富锦精密工业（深圳）有限公司 | Automated testing method and system for mainboard |
| CN102289399A (en) * | 2011-09-01 | 2011-12-21 | 深圳芯智汇科技有限公司 | System and method for testing main board of computer |
| CN103035301A (en) * | 2011-10-06 | 2013-04-10 | 鸿富锦精密工业（深圳）有限公司 | Testing method and testing device for parameters of memory bar |
| CN102880534A (en) * | 2012-07-20 | 2013-01-16 | 曙光信息产业(北京)有限公司 | Testing method for memory voltage of Loongson server motherboard |
| CN102866939A (en) * | 2012-09-05 | 2013-01-09 | 记忆科技(深圳)有限公司 | Test device for internal memory |
| CN103973534A (en) * | 2014-05-28 | 2014-08-06 | 广州视源电子科技股份有限公司 | Analog U disk sharing method and analog U disk sharing equipment |
| CN104459518A (en) * | 2014-11-27 | 2015-03-25 | 北京时代民芯科技有限公司 | Function automation testing system and testing method based on SoPC chip |
| CN204256724U (en) * | 2014-12-13 | 2015-04-08 | 海太半导体（无锡）有限公司 | A kind of server memory testing apparatus |
| CN104681093A (en) * | 2014-12-26 | 2015-06-03 | 复旦大学 | Semiconductor memory device electrical parameter test system |
| CN107132468A (en) * | 2016-02-26 | 2017-09-05 | 富泰华工业（深圳）有限公司 | Mainboard test device and method of testing |
| CN106326054A (en) * | 2016-08-25 | 2017-01-11 | 天津市英贝特航天科技有限公司 | Automatic test system and method of mainboard PCI external device |
| CN109100636A (en) * | 2018-07-11 | 2018-12-28 | 青岛北洋天青数联智能股份有限公司 | Circuit board detection method, device, system and test host computer |
| CN109062745A (en) * | 2018-07-26 | 2018-12-21 | 郑州云海信息技术有限公司 | A kind of test terminal with testing service device hardware temperatures |
Non-Patent Citations (1)
| Title |
|---|
| 孙灯亮.DDR1&2&3信号完整性测试分析技术探析.国外电子测量技术.2006,79-83. * |
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